SAMSUNG K7A323600M-QC14

K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
Document Title
1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
History
Draft Date
Remark
0.0
1. Initial draft
May. 10. 2001
Advance
0.1
1. Add 165FBGA package
Aug. 29. 2001
Preliminary
0.2
1. Update JTAG scan order
2. Speed bin merge.
From K7A3236(18)09M to K7A3236(18)00M.
3. AC parameter change.
tOH(min)/tHZC(min) from 0.8 to 1.5 at -25
tOH(min)/tHZC(min) from 1.0 to 1.5 at -22
tOH(min)/tHZC(min) from 1.0 to 1.5 at -20
Dec. 31. 2001
Preliminary
0.3
1. Change pin out for 165FBGA
- x18/x36 ; 11B => from A to NC , 2R ==> from NC to A .
Feb. 14. 2002
Preliminary
0.4
1. Insert pin at JTAG scan order of 165FBGA in connection with pin out change
- x18/x36 ; insert Pin ID of 2R to BIT number of 69
Apr. 20. 2002
Preliminary
0.5
1. Add Icc, Isb,Isb1 and Isb2 values
May.10. 2002
Preliminary
1.0
1. Correct the pin name of 100TQFP.
Oct. 15. 2002
Final
1.1
1. Add the Industrial temperature range.
Mar. 19, 2003
Final
1.2
1. Change the Stand-by current (Isb)
Before
After
Isb - 25 : 120
170
- 22 : 110
160
- 20 : 100
150
- 16 :
90
140
- 15 :
90
140
- 14 :
90
140
Isb1
:
90
110
Isb2
:
80
100
Oct. 17, 2003
Final
2.0
1. Delete the 119BGA and 165FBGA package.
2. Delete the 225MHz, 167MHz and 150MHz speed bin
Nov. 18, 2003
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Nov. 2003
Rev 2.0
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
32Mb SB/SPB Synchronous SRAM Ordering Information
Org.
Part Number
K7B321825M-QC65/75
Mode
VDD
Speed
SB ; Access Time(ns)
SPB ; Cycle Time(MHz)
SB
3.3
6.5/7.5ns
SPB(2E1D)
3.3
250/200/138MHz
SB
3.3
6.5/7.5ns
SPB(2E1D)
3.3
250/200/138MHz
2Mx18
K7A321800M-QC(I)25/20/14
K7B323625M-Q)C65/75
1Mx36
K7A323600M-QC(I)25/20/14
-2-
PKG
Temp
C
; Commercial
Temp.Range
Q: 100TQFP
I
; Industrial
Temp.Range
Nov. 2003
Rev 2.0
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• V DD= 3.3V +0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Contention only for TQFP ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A Package
• Operating in commeical and industrial temperature range.
The K7A323600M and K7A321800M are 37,748,736-bit
Synchronous Static Random Access Memory designed for
high performance second level cache of Pentium and
Power PC based System.
It is organized as 1M(2M) words of 36(18) bits and integrates address and control registers, a 2-bit burst address
counter and added some new functions for high performance cache RAM applications; G W, BW , LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by G W, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS 1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP ) or address status cache controller( ADSC) inputs. Subsequent burst addresses are generated internally in the system′s burst sequence and are
controlled by the burst address advance(ADV) input.
LBO pin is DC operated and determines burst
sequence(linear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A323600M and K7A321800M are fabricated using
SAMSUNG′s high performance CMOS technology and is
available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Symbol
-25
-20
-14
Unit
Cycle Time
tCYC
4.0
5.0
7.2
ns
Clock Access Time
tCD
2.6
3.1
4.0
ns
Output Enable Access Time
tOE
2.6
3.1
4.0
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
BURST CONTROL
LOGIC
CONTROL
REGISTER
ADV
ADSC
A0~A1
A0~A19
or A0~A20
ADSP
ADDRESS
REGISTER
A2~A19
or A2~A20
DATA-IN
REGISTER
CONTROL
REGISTER
CS1
CS2
CS2
GW
BW
1Mx36 , 2Mx18
MEMORY
ARRAY
BURST
ADDRESS A′0~A′1
COUNTER
WEx
(x=a,b,c,d or a,b)
OUTPUT
REGISTER
CONTROL
LOGIC
BUFFER
OE
ZZ
DQa0 ~ DQd 7 or DQa0 ~ DQb7
DQPa ~ DQPd
DQPa,DQPb
-3-
Nov. 2003
Rev 2.0
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
A6
A7
CS 1
CS 2
WEd
WEc
WEb
WEa
CS 2
V DD
V SS
CLK
GW
BW
OE
ADS C
ADS P
ADV
A8
A9
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100 Pin TQFP
(20mm x 14mm)
43
44
45
46
47
48
49
50
A 10
A 11
A 12
A 13
A 14
A 15
A 16
41
V DD
A 17
40
V SS
42
39
A 19
A 18
38
N.C.
35
A2
37
34
A3
A0
33
A4
36
32
A1
31
K7A323600M(1Mx36)
A5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LBO
DQPc
DQc 0
DQc 1
V DDQ
V SSQ
DQc 2
DQc 3
DQc 4
DQc 5
V SSQ
V DDQ
DQc 6
DQc 7
N.C.
V DD
N.C.
V SS
DQd 0
DQd 1
V DDQ
V SSQ
DQd 2
DQd 3
DQd 4
DQd 5
V SSQ
V DDQ
DQd 6
DQd 7
DQPd
100
PIN CONFIGURATION (TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb7
DQb6
V DDQ
V SSQ
DQb5
DQb4
DQb3
DQb2
V SSQ
V DDQ
DQb1
DQb0
V SS
N.C.
V DD
ZZ
DQa7
DQa6
V DDQ
V SSQ
DQa5
DQa4
DQa3
DQa2
V SSQ
V DDQ
DQa1
DQa0
DQPa
PIN NAME
SYMBOL
A 0 - A 19
PIN NAME
TQFP PIN NO.
SYMBOL
Address Inputs
32,33,34,35,36,37,39
42,43,44,45,46,47,48,
49,50,81,82,99,100
ADV
Burst Address Advance
83
ADSP
Address Status Processor 84
ADSC
Address Status Controller 85
CLK
Clock
89
CS 1
Chip Select
98
CS 2
Chip Select
97
CS 2
Chip Select
92
WE x(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
Output Enable
86
GW
Global Write Enable
88
BW
Byte Write Enable
87
ZZ
Power Down Input
64
LBO
Burst Mode Control
31
PIN NAME
TQFP PIN NO.
V DD
V SS
Power Supply(+3.3V)
Ground
15,41,65,91
17,40,67,90
N.C.
No Connect
14,16,38,66
DQa0~a7
DQb0~b7
DQc0 ~ c7
DQd0~d7
DQPa~P d
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
V DDQ
Output Power Supply
(3.3V or 2.5V)
Output Ground
4,11,20,27,54,61,70,77
V SSQ
5,10,21,26,55,60,71,76
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-4-
Nov. 2003
Rev 2.0
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
A6
A7
CS 1
CS 2
N.C.
N.C.
WEb
WEa
CS 2
V DD
V SS
CLK
GW
BW
OE
ADS C
ADS P
ADV
A8
A9
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100 Pin TQFP
(20mm x 14mm)
47
48
49
50
A 14
A 15
A 16
A 17
41
V DD
46
40
V SS
A 13
39
A 20
45
38
N.C.
A 12
37
A0
44
36
A1
A 11
35
A2
43
34
A3
A 18
33
A4
42
32
A 19
31
K7A321800M(2Mx18)
A5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LBO
N.C.
N.C.
N.C.
V DDQ
V SSQ
N.C.
N.C.
DQb0
DQb1
V SSQ
V DDQ
DQb2
DQb3
N.C.
V DD
N.C.
V SS
DQb4
DQb5
V DDQ
V SSQ
DQb6
DQb7
DQPb
N.C.
V SSQ
V DDQ
N.C.
N.C.
N.C.
100
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A 10
N.C.
N.C.
V DDQ
V SSQ
N.C.
DQPa
DQa7
DQa6
V SSQ
V DDQ
DQa5
DQa4
V SS
N.C.
V DD
ZZ
DQa3
DQa2
V DDQ
V SSQ
DQa1
DQa0
N.C.
N.C.
V SSQ
V DDQ
N.C.
N.C.
N.C.
PIN NAME
SYMBOL
PIN NAME
A 0 - A 20
Address Inputs
ADV
ADSP
ADSC
CLK
CS 1
CS 2
CS 2
W Ex(x=a,b)
OE
GW
BW
ZZ
LBO
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
TQFP PIN NO.
SYMBOL
32,33,34,35,36,37,39
42,43,44,45,46,47,48,
49,50 80,81,82,99,100
83
84
85
89
98
97
92
93,94
86
88
87
64
31
PIN NAME
TQFP PIN NO.
V DD
V SS
Power Supply(+3.3V)
Ground
15,41,65,91
17,40,67,90
N.C.
No Connect
1,2,3,6,7,14,16,25,28,29
30,38,51,52,53,56,57
66,75,78,79,95,96
DQa 0 ~ a 7
DQb 0 ~ b 7
DQPa, Pb
Data Inputs/Outputs
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
V DDQ
Output Power Supply
(3.3V or 2.5V)
Output Ground
4,11,20,27,54,61,70,77
V SSQ
5,10,21,26,55,60,71,76
Note : 1. A 0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-5-
Nov. 2003
Rev 2.0
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
FUNCTION DESCRIPTION
The K7A323600M and K7A321800M are synchronous SRAM designed to support the burst address accessing sequence of the
Power PC based microprocessor. All inputs (with the exception of O E, LBO and ZZ) are sampled on rising clock edges. The start and
duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with
ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with O E. In read operation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are carried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when W Ex are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS 1.
All byte write is done by GW(regaedless of BW and W Ex.), and each byte write is performed by the combination of B W and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that samples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of O E). Data is clocked into the data input register when WE x sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WE b, WE c or WEd) sampled low. The W Ea control DQa 0 ~ DQa7 and DQPa, WE b controls DQb 0 ~ DQb 7
and DQPb, WEc controls DQc 0 ~ DQc 7 and DQPc, and WEd control DQd 0 ~ DQd 7 and DQPd. Read or write cycle may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
LBO PIN
(Interleaved Burst)
Case 1
HIGH
A1
0
0
1
1
First Address
Fourth Address
Case 2
A0
0
1
0
1
A1
0
0
1
1
Case 3
A0
1
0
1
0
A1
1
1
0
0
Case 4
A0
0
1
0
1
A1
1
1
0
0
BQ TABLE
LBO PIN
A0
1
0
1
0
(Linear Burst)
Case 1
LOW
A1
0
0
1
1
First Address
Fourth Address
Case 2
A0
0
1
0
1
A1
0
1
1
0
Case 3
A0
1
0
1
0
A1
1
1
0
0
Case 4
A0
0
1
0
1
A1
1
0
0
1
A0
1
0
1
0
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed .
ASYNCHRONOUS TRUTH TABLE
Operation
ZZ
OE
I/O STATUS
Sleep Mode
H
X
High-Z
L
L
DQ
Read
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Notes
1. X means "Don′ t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE , otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
-6-
Nov. 2003
Rev 2.0
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS 1
CS2
CS 2
ADV
WRITE
CLK
ADDRESS ACCESSED
OPERATION
H
X
X
ADSP ADSC
X
L
X
X
↑
N/A
Not Selected
L
L
X
L
X
X
X
↑
N/A
Not Selected
L
X
H
L
X
X
X
↑
N/A
Not Selected
L
L
X
X
L
X
X
↑
N/A
Not Selected
L
X
H
X
L
X
X
↑
N/A
Not Selected
L
H
L
L
X
X
X
↑
External Address
Begin Burst Read Cycle
L
H
L
H
L
X
L
↑
External Address
Begin Burst Write Cycle
L
H
L
H
L
X
H
↑
External Address
Begin Burst Read Cycle
X
X
X
H
H
L
H
↑
Next Address
Continue Burst Read Cycle
H
X
X
X
H
L
H
↑
Next Address
Continue Burst Read Cycle
X
X
X
H
H
L
L
↑
Next Address
Continue Burst Write Cycle
H
X
X
X
H
L
L
↑
Next Address
Continue Burst Write Cycle
X
X
X
H
H
H
H
↑
Current Address
Suspend Burst Read Cycle
H
X
X
X
H
H
H
↑
Current Address
Suspend Burst Read Cycle
X
X
X
H
H
H
L
↑
Current Address
Suspend Burst Write Cycle
H
X
X
X
H
H
L
↑
Current Address
Suspend Burst Write Cycle
Notes : 1. X means "Don ′t Care".
2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE ).
WRITE TRUTH TABLE(x36)
GW
BW
WEa
WEb
WEc
WE d
OPERATION
H
H
X
X
H
L
H
H
X
X
READ
H
H
READ
H
L
L
H
L
H
H
H
H
WRITE BYTE a
L
H
H
WRITE BYTE b
H
L
H
H
L
L
WRITE BYTE c and d
H
L
L
L
L
L
WRITE ALL BYTEs
L
X
X
X
X
X
WRITE ALL BYTEs
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑) .
WRITE TRUTH TABLE(x18)
GW
BW
WEa
WEb
OPERATION
H
H
X
X
READ
H
L
H
H
READ
H
L
L
H
WRITE BYTE a
H
L
H
L
WRITE BYTE b
H
L
L
L
WRITE ALL BYTEs
L
X
X
X
WRITE ALL BYTEs
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
-7-
Nov. 2003
Rev 2.0
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
ABSOLUTE MAXIMUM RATINGS*
SYMBOL
RATING
UNIT
Voltage on V DD Supply Relative to V SS
PARAMETER
V DD
-0.3 to 4.6
V
Voltage on V DDQ Supply Relative to V SS
V DDQ
V DD
V
Voltage on Input Pin Relative to VSS
VI N
-0.3 to VDD+0.3
V
Voltage on I/O Pin Relative to VSS
V IO
-0.3 to VDDQ+0.3
V
Power Dissipation
PD
1.6
W
TSTG
-65 to 150
°C
Commercial
T OPR
0 to 70
°C
Industrial
T OPR
-40 to 85
°C
TBIAS
-10 to 85
°C
Storage Temperature
Operating Temperature
Storage Temperature Range Under Bias
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O(0°C ≤ TA ≤ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
Typ.
MAX
UNIT
V DD
3.135
3.3
3.465
V
V DDQ
3.135
3.3
3.465
V
V SS
0
0
0
V
OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
Typ.
MAX
UNIT
V DD
3.135
3.3
3.465
V
V DDQ
2.375
2.5
2.9
V
V SS
0
0
0
V
CAPACITANCE* (TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
TEST CONDITION
MIN
MAX
UNIT
C IN
V IN=0V
-
5
pF
C OUT
V OUT=0V
-
7
pF
*Note : Sampled not 100% tested.
-8-
Nov. 2003
Rev 2.0
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS (VDD =3.3V+0.165V/-0.165V , T A=0°C to +70°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
Input Leakage Current(except ZZ)
IIL
V DD = Max ; V IN=VSS to V DD
-2
+2
µA
Output Leakage Current
IOL
Output Disabled, VOUT=V SS to V DDQ
-2
+2
µA
-25
-
460
Operating Current
ICC
Device Selected, I OUT=0mA,
ZZ≤V IL , Cycle Time ≥ tCYC Min
-20
-
410
-14
-
310
Device deselected, I OUT=0mA,
-25
-
170
ZZ≤V IL , f=Max,
-20
-
150
All Inputs ≤0.2V or ≥ V DD-0.2V
-14
-
140
ISB
mA
1,2
mA
ISB1
Device deselected, I OUT=0mA,
ZZ ≤0.2V,
f = 0, All Inputs=fixed (VDD-0.2V or
0.2V)
-
110
mA
ISB2
Device deselected, I OUT=0mA,
ZZ≥V DD-0.2V, f=Max, All Inputs ≤ V IL
or ≥V IH
-
100
mA
Output Low Voltage(3.3V I/O)
V OL
IOL =8.0mA
-
0.4
V
Output High Voltage(3.3V I/O)
V OH
IOH=-4.0mA
2.4
-
V
Output Low Voltage(2.5V I/O)
V OL
IOL =1.0mA
-
0.4
V
Output High Voltage(2.5V I/O)
V OH
IOH=-1.0mA
Input Low Voltage(3.3V I/O)
V IL
nput High Voltage(3.3V I/O)
Standby Current
NOTES
2.0
-
V
-0.3*
0.8
V
V IH
2.0
V DD+0.3**
V
Input Low Voltage(2.5V I/O)
V IL
-0.3*
0.7
V
Input High Voltage(2.5V I/O)
V IH
1.7
V DD+0.3**
V
3
3
Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.
2. Data states are all zero.
3. In Case of I/O Pins, the Max. VIH =V DDQ+0.3V.
V IH
VSS
VS S -1.0V
20% t CYC (MIN)
TEST CONDITIONS
(V DD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or V DD=3.3V+0.165V/-0.165V,V DDQ=2.5V+0.4V/-0.125V, TA=0to70°C)
Input
Input
Input
Input
Input
PARAMETER
Pulse Level(for 3.3V I/O)
Pulse Level(for 2.5V I/O)
Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
VALUE
0 to 3.0V
0 to 2.5V
1.0V/ns
1.0V/ns
1.5V
V DDQ/2
See Fig. 1
-9-
Nov. 2003
Rev 2.0
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
Output Load(A)
Output Load(B),
(for tLZC, tLZOE , tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50Ω
Dout
Zo=50Ω
30pF*
VL=1.5V for 3.3V I/O
V DDQ /2 for 2.5V I/O
319Ω / 1667Ω
Dout
353Ω / 1538Ω
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS (VDD=3.3V+0.165V/-0.165V, T A=0°C to +70°C)
-25
Parameter
Symbol
Min
-20
MAX
MIN
-14
MAX
Min
Max
Unit
Cycle Time
tCYC
4.0
-
5.0
-
7.2
-
ns
Clock Access Time
tCD
-
2.6
-
3.1
-
4.0
ns
Output Enable to Data Valid
tOE
-
2.6
-
3.1
-
4.0
ns
Clock High to Output Low-Z
tLZC
0
-
0
-
0
-
ns
Output Hold from Clock High
tO H
1.5
-
1.5
-
1.5
-
ns
Output Enable Low to Output Low-Z
tLZOE
0
-
0
-
0
-
ns
Output Enable High to Output High-Z
tHZOE
-
2.6
-
3.0
-
3.5
ns
Clock High to Output High-Z
tHZC
1.5
2.6
1.5
3.0
1.5
3.5
ns
Clock High Pulse Width
tCH
1.7
-
2.0
-
2.5
-
ns
Clock Low Pulse Width
tCL
1.7
-
2.0
-
2.5
-
ns
Address Setup to Clock High
tAS
1.2
-
1.4
-
1.5
-
ns
Address Status Setup to Clock High
tSS
1.2
-
1.4
-
1.5
-
ns
Data Setup to Clock High
tDS
1.2
-
1.4
-
1.5
-
ns
Write Setup to Clock High (GW, BW , WE X)
tWS
1.2
-
1.4
-
1.5
-
ns
Address Advance Setup to Clock High
tADVS
1.2
-
1.4
-
1.5
-
ns
Chip Select Setup to Clock High
tCSS
1.2
-
1.4
-
1.5
-
ns
Address Hold from Clock High
tAH
0.3
-
0.4
-
0.5
-
ns
Address Status Hold from Clock High
tSH
0.3
-
0.4
-
0.5
-
ns
Data Hold from Clock High
tDH
0.3
-
0.4
-
0.5
-
ns
Write Hold from Clock High (G W, BW,
tWH
0.3
-
0.4
-
0.5
-
ns
Address Advance Hold from Clock High
tADVH
0.3
-
0.4
-
0.5
-
ns
Chip Select Hold from Clock High
tCSH
0.3
-
0.4
-
0.5
-
ns
ZZ High to Power Down
tPDS
2
-
2
-
2
-
cycle
ZZ Low to Power Up
tPUS
2
-
2
-
2
-
cycle
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
- 10 -
Nov. 2003
Rev 2.0
- 11 -
Data Out
OE
ADV
CS
WRITE
ADDRESS
ADSC
ADSP
CLOCK
tCSS
tAS
tSS
A1
tADVS
tCSH
tWS
tAH
tSH
Q 1-1
A2
tHZOE
tSH
Q2-1
tCD
tOH
Q2-2
A3
Q2-3
(ADV INSERTS WAIT STATE)
BURST CONTINUED WITH
NEW BASE ADDRESS
NOTES : WRITE = L means GW = L, or G W = H, BW = L, WEx = L
CS = L means CS1 = L, CS2 = H and CS 2 = L
CS = H mean s CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tLZOE
tOE
tADVH
tWH
tSS
tCL
tCYC
tCH
TIMING WAVEFORM OF READ CYCLE
Q2-4
Q3-1
Q3-2
Q3-3
Undefined
Don′t Care
Q3-4
tHZC
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
Nov. 2003
Rev 2.0
- 12 -
Data Out
Data In
OE
ADV
CS
WRITE
ADDRESS
ADSC
ADSP
CLOCK
Q0-3
tCSS
tAS
tSS
Q0-4
A1
tHZOE
tCSH
tAH
tSH
D1-1
tCL
tCYC
tCH
A2
D2-1
D2-2
(ADV SUSPENDS BURST)
D2-2
D2-3
(ADSC EXTENDED BURST)
TIMING WAVEFORM OF WRTE CYCLE
D2-4
D3-1
A3
tDS
tADVS
tWS
tSS
D3-2
tDH
tADVH
tWH
tSH
D3-3
Undefined
Don′t Care
D3-4
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
Nov. 2003
Rev 2.0
- 13 -
Data Out
Data In
OE
ADV
CS
WRITE
ADDRESS
ADSP
CLOCK
tHZC
tSS
A1
tSH
tCD
tLZC
tAS
Q 1-1
A2
tCYC
tCL
tHZOE
tDS
tADVS
tWS
tAH
tCH
D2-1
tDH
tADVH
tWH
A3
tLZOE
Q3-1
Q3-2
tOH
Q3-3
TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED , ADSC=HIGH)
Unde fine d
Don′t Care
Q3-4
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
Nov. 2003
Rev 2.0
- 14 -
Data In
Data Out
OE
ADV
CS
WRITE
ADDRESS
ADSC
CLOCK
tCSS
tSS
A1
tCSH
tSH
tOE
tLZOE
A2
Q 1-1
A3
Q2-1
A4
Q3-1
Q4-1
tHZOE
D5-1
A5
tDS
tWS
D6-1
A6
tDH
tWH
D7-1
A7
tCL
tWS
tCYC
tCH
A8
tLZOE
tWH
A9
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED , ADSP=HIGH)
Q8-1
Undefined
Don′t Ca re
Q9-1
tOH
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
Nov. 2003
Rev 2.0
- 15 -
ZZ
Data Out
Data In
OE
ADV
CS
WRITE
ADDRESS
ADSC
ADSP
CLOCK
tCSS
tAS
tSS
A1
tCSH
tAH
tSH
tLZOE
tOE
Q1-1
ZZ Setup Cycle
tPDS
tHZC
Sleep State
ZZ Recovery Cycle
tPUS
tCL
tCYC
tCH
TIMING WAVEFORM OF POWER DOWN CYCLE
tWS
Normal Operation Mode
tHZOE
A2
D2-1
tWH
Undefined
Don′t Care
D2-2
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
Nov. 2003
Rev 2.0
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 512Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.
I/O [0:71]
Data
Address
A[0:19]
A[19]
A[0:18]
A[19]
A[0:18]
Address Data
CLK
Address Data
CS2
CS 2
CS2
CS 2
CLK
Microprocessor
Address
512Kx36
SPB
SRAM
ADSC
CLK
CLK
ADSC
WEx
WEx
(Bank 0)
OE
Cache
Controller
512Kx36
SPB
SRAM
(Bank 1)
OE
CS1
CS 1
ADV
ADSP
ADV
ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
ADDRESS
[0:n]
A1
tAH
A2
tWS
tWH
WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS 2
An+1
tADVS
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVH
ADV
OE
tOE
Data Out
(Bank 0)
Data Out
(Bank 1)
tHZC
tLZOE
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Q2-1
*Notes :
n = 14 32K depth ,
16 128K depth ,
18 512K depth ,
15 64K depth
17 256K depth
19 1M depth
- 16 -
Q2-2
Q2-3
Don′t Care
Q2-4
Undefined
Nov. 2003
Rev 2.0
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 1Mx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic.
I/O[0:71]
Data
Address
A[20]
A[0:20]
A[20]
A[0:19]
Address Data
CLK
Address Data
CS2
CS2
CS2
Microprocessor
CS2
CLK
Address
1Mx18
SPB
SRAM
ADSC
CLK
WEx
CLK
1Mx18
SPB
SRAM
ADSC
WEx
(Bank 0)
OE
Cache
Controller
A[0:19]
(Bank 1)
OE
CS1
CS1
ADV
ADV
ADSP
ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
ADDRESS
[0:n]
tAH
A1
A2
tWS
tWH
WRITE
tCSS
tCSH
CS 1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
A n+1
tADVS
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVH
ADV
OE
tOE
Data Out
(Bank 0)
Data Out
(Bank 1)
tLZOE
tHZC
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Q2-1
*Notes : n = 14
16
18
20
32K depth ,
128K depth ,
512K depth ,
2M depth
15 64K depth
17 256K depth
19 1M depth
Q2-2
Undefined
- 17 -
Q2-3
Q2-4
Don′t Care
Nov. 2003
Rev 2.0
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
PACKAGE DIMENSIONS
100-TQFP-1420A
Units ; millimeters/Inches
22.00
± 0.30
20.00
± 0.20
0~8°
0.127
16.00
14.00
+ 0.10
- 0.05
±0.30
± 0.20
0.10 MAX
(0.83)
0.50
#1
0.65
±0.10
(0.58)
0.30 ± 0.10
0.10 MAX
1.40 ± 0.10
0.50
±0.10
- 18 -
1.60 MAX
0.05 MIN
Nov. 2003
Rev 2.0