Advance CMOS SRAM KM68512B Family Document Title 64Kx8 bit Low Power CMOS Static RAM Revision History Revision No. 0.0 History Draft Data Remark Initial draft January 10th 1998 Advance The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you ha ve any questions, please contact the SAMSUNG branch office near you. 1 Revision 0.0 January 1998 Advance CMOS SRAM KM68512B Family 64Kx8 bit Low Power CMOS Static RAM FEATURES GENERAL DESCRIPTION • • • • • • The KM68512B family is fabricated by SAMSUNG ′s advanced CMOS process technology. The family support various operating temperature ranges and small package type for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current. Process Technology : 0.4 µm CMOS Organization : 64Kx8 Power Supply Voltage : Single 5V ±10% Low Data Retention Voltage : 2V(Min) Three state output and TTL Compatible Package Type : 32-TSOP I -0820F PRODUCT FAMILY Power Dissipation Product Family Operating Temperature KM68512BL-L Commercial(0~70 °C) KM68512BLI-L Industrial(-40~85 °C) PIN DESCRIPTION A11 A9 A8 A13 WE CS2 A15 VCC NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-TSOP Type1 - Forward VCC Range 5V±0.5V Speed(ns) Standby (ISB1 , Max) 55/70 10µA 70 15µA Operating (ICC2, Max) PKG Type 60mA 32-TSOP1-F FUNCTIONAL BLOCK DIAGRAM 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 Clk gen. Precharge circuit. A4 A5 A6 A7 A8 Memory array 512 rows 128×8 columns Row select A12 A13 A14 A15 Name Data cont I/O1 Function I/O8 A0~A15 I/O Circuit Column select Address Inputs WE Write Enable Input CS1, CS2 Chip Select Inputs OE Output Enable Input I/O1~I/O8 Data Inputs/Outputs Vcc Power Vss Ground N.C No Connection Data cont A0 A1 A2 A3 A9 A10 A11 CS CS2 WE Control logic OE SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 0.0 January 1998 Advance CMOS SRAM KM68512B Family PRODUCT LIST Industrial Temperature Products (-40~85°C) Commercial Temperature Product (0~70°C) Part Name Function Part Name KM68512BLT-5L 32-TSOP1-F, 55ns, LL-pwr KM68512BLT-7L 32-TSOP1-F, 70ns, LL-pwr Function KM68512BLTI-7L 32-TSOP1-F, 70ns, LL-pwr FUNCTIONAL DESCRIPTION CS1 CS2 OE WE 1) 1) I/O Pin Mode Power H X X X High-Z Deselected Standby X1) L X1) X1) High-Z Deselected Standby L H H H High-Z Output Disabled Active L H L H Dout Read Active L H X L Din Write Active 1) 1. X means don′t care.(Must be low or high state) ABSOLUTE MAXIMUM RATINGS Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time 1) Symbol Ratings Unit Remark VIN,VOUT -0.5 to 7.0 V - VCC -0.5 to 7.0 V - PD 1.0 W - TSTG -65 to 150 °C - 0 to 70 °C KM68512BL -40 to 85 °C KM68512BLI 260°C, 10sec(Lead Only) - - TA TSOLDER 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional oper ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect r eliability. 3 Revision 0.0 January 1998 Advance CMOS SRAM KM68512B Family RECOMMENDED DC OPERATING CONDITIONS Item 1) Symbol Min Typ Max Unit Supply voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input high voltage VIH 2.2 - Vcc+0.5V 2) V Input low voltage VIL - 0.8 V -0.5 3) Note 1. Commercial Product : TA=0 to 70°C, unless otherwise specified Industrial Product : TA=-40 to 85°C, unless otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width≤30ns 3. Undershoot : -3.0V in case of pulse width≤30ns 4. Overshoot and undershoot is sampled, not 100% tested CAPACITANCE 1)(f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 6 pF Input/Output capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA Operating power supply ICC IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH, Read - 7 10 mA ICC1 Cycle time=1 §Á , 100% duty, I IO=0mA CS1≤0.2V, CS 2≥VCC-0.2V, V IN≤0.2V or V IN≥Vcc -0.2V Read - - 5 mA Write - - 30 mA Average operating current ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH - - 60 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS1=VIH, CS2=VIL, Other inputs =V IL or V IH - - 3 mA Standby Current (CMOS) ISB1 CS1≥Vcc-0.2V, CS 2≥Vcc-0.2V or CS 2≤0.2V - 1 101) µA 1. Industrial product = 15µA 4 Revision 0.0 January 1998 Advance CMOS SRAM KM68512B Family AC OPERATING CONDITIONS TEST CONDITIONS ( Test Load and Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and faling time : 5ns Input and output reference voltage :1.5V Output load(see right) : C L=100pF+1TTL CL1) 1. Including scope and jig capacitance AC CHARACTERISTICS (Vcc=4.5~5.5V, KM68512B Family : TA=0 to 70°C, KM68512BI Family : TA=-40 to 85°C) Speed Bins Parameter List Symbol Min Max Min Max 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tCO - 55 - 70 ns Output enable to valid output tOE - 25 - 35 ns Chip select to low-Z output tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 25 ns tOHZ 0 20 0 25 ns Output disable to high-Z output Write Units 70ns tRC Read cycle time Read 55ns Output hold from address change tOH 10 - 10 - ns Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns Write pulse width tWP 40 - 55 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 20 - 30 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns Min Typ Max Unit V DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Symbol VDR IDR Data retention set-up time tSDR Recovery time tRDR Test Condition CS1 ≥Vcc-0.2V 2.0 - 5.5 KM68512BL-L - 0.5 10 KM68512BLI-L - - 15 0 - - 5 - - 1) Vcc=3.0V, CS1≥Vcc-0.2V See data retention waveform µA ms 1. CS1≥Vcc-0.2V, CS2≥Vcc-0.2V( CS1 controlled) or CS2≤0.2V(CS2 controlled). 5 Revision 0.0 January 1998 Advance CMOS SRAM KM68512B Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE OE Data out High-Z tOHZ tOLZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 0.0 January 1998 Advance CMOS SRAM KM68512B Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS1 tAW CS2 tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z 7 Revision 0.0 January 1998 Advance CMOS SRAM KM68512B Family TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS1 tAW CS2 tWP(2) tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. t WR(1) applied in case a write ends as CS1 or WE going high tWR(2) applied in case a write ends as CS 2 going to low. DATA RETENTION WAVE FORM CS1 controlled VCC tSDR Data Retention Mode tRDR 4.5V 2.2V VDR CS≥VCC - 0.2V CS1 GND CS2 controlled Data Retention Mode VCC 4.5V* CS2 tSDR tRDR VDR 0.4V CS2≤0.2V GND 8 Revision 0.0 January 1998 Advance CMOS SRAM KM68512B Family PACKAGE DIMENSIONS Units : Millimeters(Inches) 32-THIN SMALL OUTLINE PACKAGE TYPE I (0820F) +0.10 -0.05 0.008+0.004 -0.002 0.20 20.00±0.20 0.787±0.008 #1 #32 MAX 8.40 0.331 0.50 0.0197 #17 #16 0.25 0.010 TYP 0.25 ) 0.010 8.00 0.315 ( 1.00±0.10 0.039±0.004 1.20 0.047 MAX 0.05 0.002 MIN 18.40±0.10 0.724±0.004 +0.10 -0.05 0.006+0.004 -0.002 0~8° 0.45 ~0.75 0.018 ~0.030 ( 9 0.10 MAX 0.004 MAX 0.15 0.50 ) 0.020 Revision 0.0 January 1998