SAMSUNG M464S6554BTS-L7A

256MB, 512MB Unbuffered SODIMM
SDRAM
SDRAM Unbuffered SODIMM
144pin Unbuffered SODIMM based on 512Mb B-die
64-bit Non ECC
Revision 1.2
March 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
Revision History
Revision 1.0 (January, 2004)
- First release
Revision 1.1 (February, 2004)
- Corrected typo.
Revision 1.2 (March. 2004)
- Corrected package dimension.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
144Pin Unbuffered SODIMM based on 512Mb B-die(x8, x16)
Ordering Information
Part Number
Density
Organization
Component Composition
M464S3354BTS-C(L)7A
256MB
32M x 64
32Mx16(K4S511632B) * 4EA
M464S6554BTS-C(L)7A
512MB
64M x 64
32Mx16(K4S511632B) * 8EA
Component
Package
54-TSOP(II)
Height
1,000mil
1,250mil
Operating Frequencies
7A
@CL3
@CL2
Maximum Clock Frequency
133MHz(7.5ns)
100MHz(10ns)
CL-tRCD-tRP(clock)
3-3-3
2-2-2
Feature
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs Latency (Access from column address)
Burst length (1, 2, 4, 8)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Serial presence detect with EEPROM
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
PIN CONFIGURATIONS (Front side/back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
VSS
DQM0
DQM1
VDD
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ13
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
VSS
DQM4
DQM5
VDD
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VDD
DQ44
DQ45
51
53
55
57
59
DQ14
DQ15
VSS
NC
NC
52
54
56
58
60
DQ46
DQ47
VSS
NC
NC
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
DQ21
DQ22
DQ23
VDD
A6
A8
VSS
A9
A10/AP
VDD
DQM2
DQM3
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VDD
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
DQ53
DQ54
DQ55
VDD
A7
BA0
VSS
BA1
A11
VDD
DQM6
DQM7
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VDD
Voltage Key
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
**CLK0
VDD
RAS
WE
**CS0
**CS1
DU
VSS
NC
NC
VDD
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
**CKE0
VDD
CAS
**CKE1
A12
*A13
**CLK1
VSS
NC
NC
VDD
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Pin Description
Pin Name
Function
Pin Name
Function
A0 ~ A12
Address input (Multiplexed)
WE
Write enable
BA0 ~ BA1
Select bank
DQM0 ~ 7
DQM
DQ0 ~ DQ63
Data input/output
VDD
Power supply (3.3V)
CLK0 ~ CLK1
Clock input
VSS
Ground
CKE0 ~ CKE1
Clock enable input
SDA
Serial data I/O
CS0 ~ CS1
Chip select input
SCL
Serial clock
RAS
Row address strobe
DU
Don′t use
CAS
Column address strobe
NC
No connection
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
PIN CONFIGURATION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12
Column address : (x16 : CA0 ~ CA9)
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
VDD/VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
256MB, 32Mx64 Module (M464S3354BTS) (Populated as 1 bank of x16 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
DQM0
CS0
DQM4
LDQM CS
DQ0
DQ1
DQ2
U0
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
LDQM CS
DQ0
DQ1
DQ2
U2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM5
DQM6
DQM2
LDQM CS
LDQM CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM3
U1
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM7
A0 ~ A12, BA0 & 1
SDRAM U0 ~ U3
RAS
SDRAM U0 ~ U3
SCL
CAS
SDRAM U0 ~ U3
47KΩ
WE
SDRAM U0 ~ U3
CKE0
DQn
VDD
Vss
Serial PD
SDRAM U0 ~ U3
10Ω
WP
SA0 SA1 SA2
SDA
U0
Every DQ pin of SDRAM
Three 0.1uF X7R 0603Capacitors
per each SDRAM
U3
CLK0
U1
U2
U3
To all SDRAMs
CLK1
10Ω
10pF
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
512MB, 64Mx64 Module (M366S6554BTS) (Populated as 2 bank of x16 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
CS1
CS0
DQM0
DQM4
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
LDQM
U0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U4
LDQM
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U2
DQM1
UDQM
UDQM
DQM5
UDQM
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM2
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM3
UDQM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
LDQM
U1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM7
UDQM
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
SDRAM U0 ~ U7
U5
WE
SDRAM U0 ~ U7
CKE0
SDRAM U0 ~ U3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
CS
U7
Serial PD
SCL
SDRAM U0 ~ U7
CKE1
LDQM
UDQM
RAS
CAS
CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SDRAM U0 ~ U7
DQn
LDQM
CS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
A0 ~ A12, BA0 & 1
Vss
U6
DQM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
VDD
CS
47KΩ
WP
SA0 SA1 SA2
SDA
SDRAM U4 ~ U7
10Ω
Every DQ pin of SDRAM
Three 0.1 uF X7R 0603 Capacitors
per each SDRAM
U0/U4
To all SDRAMs
CLK0/1
U1/U5
U2/U6
U3/U7
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 4.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.0 * # of component
W
Short circuit current
IOS
50
mA
Storage temperature
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDDQ+0.3
V
1
Input low voltage
VIL
-0.3
0
0.8
V
2
Output high voltage
VOH
2.4
-
-
V
IOH = -2mA
Output low voltage
VOL
-
-
0.4
V
IOL = 2mA
ILI
-10
-
10
uA
3
Input leakage current
Note
Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Parameter
Symbol
M464S3354BTS
M464S6454BTS
Min
Max
Min
Max
Unit
Input capacitance (A0 ~ A12, BA0 ~ BA1)
CIN1
15
25
25
45
pF
Input capacitance (RAS, CAS, WE)
CIN2
15
25
25
45
pF
Input capacitance (CKE0 ~ CKE1)
CIN3
15
25
15
25
pF
Input capacitance (CLK0 ~ CLK1)
CIN4
15
21
15
21
pF
Input capacitance (CS0 ~ CS1)
CIN5
15
25
15
25
pF
Input capacitance (DQM0 ~ DQM7)
CIN6
10
12
10
12
pF
Data input/output capacitance (DQ0 ~ DQ63)
COUT
10
12
10
12
pF
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
DC CHARACTERISTICS
M464S3354BTS (32M x 64, 256MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
Parameter
Symbol
Test Condition
Unit
Note
mA
1
7A
Operating current
(One bank active)
Precharge standby current
in power-down mode
ICC1
ICC2P
ICC2PS
ICC2N
Precharge standby current
in non power-down mode
ICC2NS
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC3P
ICC3PS
ICC3N
ICC3NS
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
400
CKE ≤ VIL(max), tCC = 10ns
8
CKE & CLK ≤ VIL(max), tCC =∞
8
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
80
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
40
CKE ≤ VIL(max), tCC = 10ns
25
CKE & CLK ≤ VIL(max), tCC =∞
25
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
120
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
100
mA
mA
Operating current
(Burst mode)
ICC4
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
520
mA
1
Refresh current
ICC5
tRC ≥ tRC(min)
800
mA
2
12
mA
ICC6
CKE ≤ 0.2V
C
Self refresh current
L
6
mA
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
DC CHARACTERISTICS
M464S6554BTS (64M x 64, 512MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
Parameter
Symbol
Test Condition
Unit
Note
mA
1
7A
Operating current
(One bank active)
Precharge standby current
in power-down mode
ICC1
ICC2P
ICC2PS
ICC2N
Precharge standby current
in non power-down mode
ICC2NS
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC3P
ICC3PS
ICC3N
ICC3NS
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
520
CKE ≤ VIL(max), tCC = 10ns
16
CKE & CLK ≤ VIL(max), tCC =∞
16
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
160
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
80
CKE ≤ VIL(max), tCC = 10ns
50
CKE & CLK ≤ VIL(max), tCC =∞
50
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
240
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
200
mA
640
mA
1
920
mA
2
C
24
mA
L
12
mA
Operating current
(Burst mode)
ICC4
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
Refresh current
ICC5
tRC ≥ tRC(min)
Self refresh current
ICC6
CKE ≤ 0.2V
mA
mA
mA
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf = 1/1
ns
1.4
V
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
870Ω
Output
Z0 = 50Ω
50pF
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
7A
Unit
Note
Row active to row active delay
tRRD(min)
15
ns
1
RAS to CAS delay
tRCD(min)
20
ns
1
tRP(min)
20
ns
1
1
Row precharge time
tRAS(min)
45
ns
tRAS(max)
100
us
Row cycle time
tRC(min)
65
ns
1
Last data in to row precharge
tRDL(min)
2
CLK
2
Last data in to Active delay
tDAL(min)
2 CLK + tRP
-
Row active time
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
ea
4
Number of valid output data
CAS latency=3
2
CAS latency=2
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter
CLK cycle
time
CAS latency=3
CLK to valid
output delay
CAS latency=3
Output data
hold time
CAS latency=2
CAS latency=2
CAS latency=3
CAS latency=2
Symbol
tCC
7A
Min
7.5
10
1000
5.4
tSAC
tOH
Max
6
3
3
Unit
Note
ns
1
ns
1,2
ns
2
CLK high pulse width
tCH
2.5
ns
3
CLK low pulse width
tCL
2.5
ns
3
Input setup time
tSS
1.5
ns
3
Input hold time
tSH
0.8
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
tSHZ
5.4
6
ns
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
SIMPLIFIED TRUTH TABLE
Command
Register
Mode register set
Auto refresh
Refresh
Entry
Self
refresh
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
H
X
L
L
L
L
X
OP code
L
L
L
H
X
X
L
H
H
H
X
X
H
H
L
BA0,1
L
H
H
X
X
X
Bank active & row addr.
H
X
L
L
H
H
X
V
Read &
column address
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
V
H
X
L
H
H
L
X
Write &
column address
Exit
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
Burst stop
Precharge
Bank selection
H
X
Entry
H
L
Exit
L
H
Entry
H
L
All banks
Clock suspend or
active power down
Precharge power down mode
Exit
L
DQM
H
No operation command
H
H
L
L
H
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
X
H
X
X
X
L
H
H
H
X
X
A10/AP
A0 ~ A9,
A11, A12
Note
1,2
3
3
3
3
Row address
L
Column
address
H
L
Column
address
H
X
V
L
X
H
4
4,5
4
4,5
6
X
X
X
X
X
X
V
X
X
X
7
Notes : 1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
PACKAGE DIMENSIONS : 32Mx64 (M464S3354BTS)
Units : Inches (Millimeters)
2.66
(67.56)
2.50
(63.60)
1
59
61
0.91
(23.20)
0.13
(3.30)
143
2-φ 0.07
(1.80)
1.29
(32.80)
0.18
(4.60)
0.083
(2.10)
0.10
(2.50)
0.79
(20.00)
0.24
(6.0)
0.16 ± 0.039
(4.00 ± 0.10)
1.00
(25.40)
2-R 0.078 Min
(2.00 Min)
Y
Z
0.15
(3.70)
62
144
0.157 Min
(4.00 Min)
0.125 Min
(3.20 Min)
0.150 Max
(3.80 Max)
0.04 ± 0.0039
(1.00 ± 0.10)
0.16 ± 0.0039
(4.00 ± 0.10)
0.06 ± 0.0039
(1.50 ± 0.1)
Detail Z
0.100 Min
60
(2.540 Min)
2
0.024 ± 0.001
(0.600 ± 0.050)
0.008 ±0.006
(0.200 ±0.150)
0.03 TYP
(0.80 TYP)
Detail Y
Tolerances : ± 0.006(.15) unless otherwise specified
The used device is 32Mx16 SDRAM, TSOPII
SDRAM Part No. : K4S511632B
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
PACKAGE DIMENSIONS : 64Mx64 (M464S6554BTS)
Units : Inches (Millimeters)
2.66
(67.56)
2.50
(63.60)
1
59
61
0.91
(23.20)
0.13
(3.30)
143
2-φ 0.07
(1.80)
1.29
(32.80)
0.18
(4.60)
0.083
(2.10)
0.10
(2.50)
0.79
(20.00)
0.24
(6.0)
0.16 ± 0.039
(4.00 ± 0.10)
1.25
(31.75)
2-R 0.078 Min
(2.00 Min)
Y
Z
0.15
(3.70)
62
144
0.157 Min
(4.00 Min)
0.125 Min
(3.20 Min)
0.150 Max
(3.80 Max)
0.04 ± 0.0039
(1.00 ± 0.10)
0.16 ± 0.0039
(4.00 ± 0.10)
0.06 ± 0.0039
(1.50 ± 0.1)
Detail Z
0.100 Min
60
(2.540 Min)
2
0.024 ± 0.001
(0.600 ± 0.050)
0.008 ±0.006
(0.200 ±0.150)
0.03 TYP
(0.80 TYP)
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is 32Mx16 SDRAM, TSOPII
SDRAM Part No. : K4S511632B
Rev. 1.2 March 2004