SANYO LC78711

Ordering number : EN5476
CMOS LSI
LC78711E
Graphics Display Processor
Overview
Package Dimensions
The LC78711E is a CMOS LSI that provides graphics
display drawing functions. In addition to implementing
graphics display for NTSC and PAL signals, it provides
two 32 × 32-dot sprite display patterns and can easily
implement a wide range of displays.
unit: mm
3159-QFP64E
[LC78711E]
Features
• Two-chip structure consisting of this LSI, the
LC78711E, and an external 64-K × 4-bit RAM. (An
RGB encoder is built in.)
• Graphics drawing controlled by a microprocessor over a
serial interface.
• Includes two crystal oscillator systems, one for NTSC
and one for PAL, and these system can be easily
switched using the provided control pin.
The standard clocks and all necessary internal timings
can be generated by connecting two crystals, a
14.31818-MHz crystal for NTSC, and a 17.734476-MHz
crystal for PAL.
• Two 32 × 32-dot sprite patterns provided. Up to two
sprites can be displayed, either two different types or the
same pattern in two different locations.
• 16 colors from a palette of 4096 colors can be displayed
in graphics screens, and seven colors can be displayed in
sprite patterns.
• Y/C signal outputs (two 8-bit D/A converter outputs)
• Supports the superimpose function, and provides a
timing signal output.
• Provides a color bar signal output function.
• Adopts an 8-bit serial data input format for the external
control input.
SANYO: QFP64E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
63096HA (OT) No. 5476-1/43
LC78711E
Pin Assignment
Specifications
Absolute Maximum Ratings
Parameter
Maximum supply voltage
Maximum input voltage
Maximum output voltage
Allowable power dissipation
Ratings
Unit
VDD max
Symbol
AVDD1, DVDD1
VSS – 0.3 to VSS + 7.0
V
VIN max
TEST1, TEST2, TEST4, TEST5, TEST6, CE, DI, CL,
TEST7, DB0 to DB3, CB, LINE, FSCIN, TEST9, 4FSC2,
VSS – 0.3 to VDD + 0.3
TEST12, PALID, HRESET, VRESET, INIT, RESET, N/P1,
N/P2, SON, XIN1, XIN2
V
VOUT max
TEST3, DO, PSC1, PSC2, WAIT, INT, WE, RAS, A0 to A7,
DB0 to DB3, CAS, OE, TEST8, BFP, VSYNC, YS, CSYNC, VSS – 0.3 to VDD + 0.3
TEST10, TEST11, FSC0, XOUT1, XOUT2
V
Pd max
Conditions
Ta = 25°C
500
mW
Operating temperature
Topr
–30 to +85
°C
Storage temperature
Tstg
–40 to +125
°C
No. 5476-2/43
LC78711E
Allowable Operating Ranges at Ta = –30 to +85°C, VSS = 0 V
Parameter
Supply voltage
Symbol
VDD
AVDD1, DVDD1
VIH1
TEST1, TEST2, TEST4, TEST5, TEST6, CE, DI, TEST7,
CB, LINE, TEST9, TEST12, PALID, HRESET, VRESET,
N/P1, N/P2, SON
VIH2
CL, INIT, RESET
VIH3
DB0 to DB3
typ
4.5
Unit
max
V
0.7 VDD1
VDD1 + 0.3
V
0.8 VDD1
VDD1 + 0.3
V
2.2
VDD1 + 0.3
V
VIL1
TEST1, TEST2, TEST4, TEST5, TEST6, CE, DI, TEST7,
CB, LINE, TEST9, TEST12, PALID, HRESET, VRESET,
N/P1, N/P2, SON
VSS1 – 0.3
0.3 VDD1
V
VIL2
CL, INIT, RESET
VSS1 – 0.3
0.2 VDD1
V
VIL3
DB0 to DB3
VSS1 – 0.3
0.8
Input low-level voltage
5.0
V
FSCIN1
XIN1
14.31818
MHz
FSCIN2
XIN2
17.73447
MHz
4FSC2: NTSC mode
14.31818
MHz
4FSC2: PAL mode
17.73447
MHz
FSCIN: NTSC mode
3.57954
MHz
FSCIN: PAL mode
4.43361
FSCIN3
FSCIN4
Input amplitude
Ratings
min
5.5
Input high-level voltage
Input frequency
Conditions
MHz
VIN1
FSCIN, 4FCS2
0.5
VDD1
Vp-p
VIN2
XIN1, XIN2
0.5
VDD1
Vp-p
Electrical Characteristics at Ta = –30 to +85°C, DVDD1 = AVDD1 = 5 V unless otherwise specified.
Parameter
Input high-level current
Input low-level current
Conditions
IIH1
TEST1, TEST2, TEST4, TEST5, TEST6, CE, DI, CL,
TEST7, DB0 to DB3, LINE, PALID, HRESET, VRESET,
INIT, RESET, N/P1, N/P2, SON: VIN = DVDD1
IIH2
CB, TEST9, TEST12: VIN = DVDD1
30
IIL1
TEST1, TEST2, TEST4, TEST5, TEST6, CE, DI, CL,
TEST7, DB0 to DB3, CB, LINE, TEST9, TEST12,
HRESET, VRESET, INIT, RESET, N/P1, N/P2, SON:
VIN = DVSS1
–5
IIL2
PALID: VIN = DVSS1
Output high-level voltage
VOH
TEST3, DO, PSC1, PSC2, WAIT, INT, BFP, WE, RAS,
A0 to A7, CAS, OE, DB0 to DB3, TEST8, VSYNC, YS,
CSYNC, TEST10, TEST11, FSCO: IOH = –0.5 mA
Output low-level voltage
VOL
TEST3, DO, PSC1, PSC2, WAIT, INT, BFP, WE, RAS,
A0 to A7, CAS, OE, DB0 to DB3, TEST8, VSYNC, YS,
CSYNC, TEST10, TEST11, FSCO: IOL = 2.0 mA
Output off leakage current
IOFF
DB0 to DB3
Internal feedback resistance
Ratings
Symbol
RX
min
typ
–200
Unit
max
100
5
µA
200
µA
µA
–100
–30
µA
VDD1 – 1
VDD1
V
VSS
0.4
V
–5
XIN1, XIN2, FSCIN, 4FSC2
+5
1
µA
MΩ
Clock duty
fduty
FSCIN, 4FSC2
8-bit D/A converter reference
voltage
VREF
VIDEO1, VIDEO2
8-bit D/A converter output
resistance
RDA
VIDEO1, VIDEO2
IDD1
AVDD1
26
40
mA
IDD2
DVDD1
26
40
mA
Operating current drain
40
60
%
2.30
2.50
V
Ω
300
No. 5476-3/43
LC78711E
Electrical Characteristics at Ta = 25°C, VDD = 5.0 V, Fscp = 15.625 kHz
Parameter
Symbol
Conditions
Ratings
min
typ
max
Unit
tWH
CL, high-level pulse width
75
ns
tWL
CL, low-level pulse width
75
ns
Data setup time
tDS
DI, CL
20
ns
Data hold time
tDH
DI, CL
20
ns
CE setup time
tCS
CE, CL
0
ns
CE hold time
tCH
CE, CL
300
DO setup time
tDOS
DO, CL
Data acquisition time
tWT1
Serial data acquisition time
tWT2
tWORD
Minimum input pulse width
Data restart time
Single word write time
ns
30
ns
150
ns
Serial data restart time
1.0
µs
DI, CL (1 word = 8 bits)
1.35
µs
No. 5476-4/43
LC78711E
Basic Specifications
Pin no.
Pin
1
TEST1
Test input
Pin type
I/O
Polarity
I
Positive
Test input. Must be connected to ground during normal operation.
2
TEST2
Test input
3
TEST3
Test output
4
TEST4
Test input
5
TEST5
6
7
Pin function
I
Positive
Test input. Must be connected to ground during normal operation.
O
Positive
Test output
I
Positive
Test input. Must be connected to ground during normal operation.
Test input
I
Positive
Test input. Must be connected to ground during normal operation.
TEST6
Test input
I
Positive
DVDD1
Power supply (+5 V)
—
—
Test input. Must be connected to ground during normal operation.
Digital system power supply
8
CE
Enable input
I
Positive
Serial I/O data control input
9
DO
Data output
O
Positive
Serial data output
10
DI
Data input
I
Positive
Serial data input
11
CL
Clock input
I
Positive
Serial data I/O clock input
12
PSC1
Monitor 1 output
O
Positive
Serial input monitor signal output
13
PSC2
Monitor 2 output
O
Positive
Command monitor signal output
14
WAIT
Wait signal output
O
Negative
Serial input wait signal output (for use with bit maps)
15
INT
Wait signal output
O
Negative
Serial input wait signal output (for use with the sprite function)
16
TEST7
Test input
I
Positive
17
DVSS1
Ground
—
—
Test input. Must be connected to ground during normal operation.
Digital system ground
18
WE
DRAM output
O
Negative
19
RAS
DRAM output
O
Negative
DRAM write enable signal output
DRAM row address strobe signal output
20
A0
DRAM output
I/O
Positive
DRAM address (A0) output (Functions as an input in test mode.)
21
A1
DRAM output
I/O
Positive
DRAM address (A1) output (Functions as an input in test mode.)
22
A2
DRAM output
I/O
Positive
DRAM address (A2) output (Functions as an input in test mode.)
23
A3
DRAM output
I/O
Positive
DRAM address (A3) output (Functions as an input in test mode.)
24
A4
DRAM output
I/O
Positive
DRAM address (A4) output (Functions as an input in test mode.)
25
A5
DRAM output
I/O
Positive
DRAM address (A5) output (Functions as an input in test mode.)
26
A6
DRAM output
I/O
Positive
DRAM address (A6) output (Functions as an input in test mode.)
27
A7
DRAM output
I/O
Positive
DRAM address (A7) output (Functions as an input in test mode.)
28
DB0
DRAM input and output
I/O
Positive
DRAM data (D0) input and output
29
CAS
DRAM output
O
Negative
DRAM column address strobe signal output
30
DB1
DRAM input and output
I/O
Positive
DRAM data (D1) input and output
31
OE
DRAM output
O
Negative
DRAM read enable signal output
32
DB2
DRAM input and output
I/O
Positive
DRAM data (D2) input and output
33
DB3
DRAM input and output
I/O
Positive
DRAM data (D3) input and output
34
CB
Color bar selection
I
Positive
Low: normal mode, high: color bar output
(A pull-down resistor is built in.)
35
TEST8
Test output
O
Positive
Test output
36
AVSS1
Ground
—
—
Analog system ground
37
AVDD1
Power supply (+5 V)
—
—
Analog system power supply
38
VIDEO1
39
BIAS
Video signal (Y) output
O
—
Video (luminance) signal (analog) output (D/A converter output)
Capacitor connection
O
—
40
Connections for a ripple exclusion capacitor
VIDEO2
Video signal (C) output
O
—
Video (chrominance) signal (analog) output (D/A converter output)
41
BFP
Burst flag signal output
O
Positive
Burst signal output timing flag output
42
LINE
Line count selection
I
—
Line count selection
NTSC mode - Low: 263H, high: 262H
PAL mode - Low: 314H, high: 312H
43
FSCIN
Clock input
I
Positive
Superimpose subcarrier clock input (A feedback resistor is built in.)
44
VSYNC
Vertical synchronization output
O
Negative
Vertical synchronizing signal output
45
TEST9
Test input
I
Positive
Test input. Must be connected to ground during normal operation.
(A pull-down resistor is built in.)
46
YS
Superimpose output
O
Negative
Superimpose control output
47
CSYNC
Composite synchronization output
O
Negative
Composite synchronizing signal output
48
4FSC2
Clock input
I
Positive
External clock input for the superimpose function
(A feedback resistor is built in.)
49
TEST10
Test output
O
Positive
Test output
50
TEST11
Test output
O
Positive
Test output
Continued on next page.
No. 5476-5/43
LC78711E
Continued from preceding page.
Pin no.
Pin
51
TEST12
52
PALID
53
HRESET
54
FSCO
55
VRESET
I/O
Polarity
Test input
Pin type
I
Positive
Test input. Must be connected to ground during normal operation.
Pin function
PAL mode external control input
I
Positive
External superimpose function control input for PAL mode
(A pull-up resistor is built in.)
External horizontal
synchronization input
I
Negative
External horizontal synchronization timing control input
Clock output
O
Positive
Subcarrier clock output
NTSC mode: 3.579545 MHz
PAL mode: 4.433619 MHz
External vertical
synchronization input
I
Negative
External vertical synchronization timing control input
Initialization input
I
Negative
System initialization signal input
Reset input
I
Negative
System reset signal input
56
INIT
57
RESET
58
N/P1
NTSC/PAL selection
I
Positive
NTSC/PAL selection input (RGB encoder block)
High: NTSC, low: PAL
59
N/P2
NTSC/PAL selection
I
Positive
NTSC/PAL selection input (decoder block)
High: NTSC, low: PAL
60
SON
Superimpose control
I
Positive
Superimpose function on/off control input
High: superimpose on
61
XIN2
—
XOUT2
Crystal oscillator element
connections
I
62
O
—
Crystal oscillator element
connections
I
—
O
—
63
XIN1
64
XOUT1
Connections for the PAL crystal oscillator element
(4·fsc = 17.734476 MHz)
Connections for the NTSC crystal oscillator element
(4·fsc = 14.31818 MHz)
Timing Characteristics (DRAM access timing) at Ta = +25°C, DVDD1 = 5 V
Parameter
Symbol
Conditions
Ratings
min
typ
max
Unit
Random read/write cycle
tRC
250
Page mode cycle
tPC
130
RAS access time
tRAC
210
ns
CAS access time
tCAC
10
ns
Output turn off delay
tOFF
RAS precharge time
tRP
100
RAS pulse width
tRAS
120
RAS pulse width (page mode)
tRASP
ns
ns
20
ns
ns
ns
18000
ns
RAS hold time
tRSH
60
CAS hold time
tCSH
120
ns
CAS pulse width
tCAS
60
ns
CAS precharge time
tCPN
50
ns
CAS precharge time
tCP
50
ns
Row address setup time
tASR
100
ns
Row address hold time
tRAH
50
ns
Page mode
ns
Column address setup time
tASC
0
ns
Column address hold time
tCAH
50
ns
Read command setup time
tRCS
150
ns
Read command hold time
tRCH
Referenced to CAS
120
ns
Read command hold time
tRRH
Referenced to RAS
120
ns
Write command setup time
tWCS
100
ns
Write command hold time
tWCH
50
ns
Write command pulse width
tWP
150
ns
Write data setup time
tDS
100
ns
Write data setup time
tDH
100
ns
CAS setup time
tCSR
CAS before RAS
50
ns
CAS hold time
tCHR
CAS before RAS
50
ns
RAS precharge CAS active time
tRPC
50
ns
Refresh time
tREF
3.5
ms
No. 5476-6/43
LC78711E
1. DRAM read cycle
No. 5476-7/43
LC78711E
2. DRAM Early write cycle
No. 5476-8/43
LC78711E
3. DRAM page mode read cycle
No. 5476-9/43
LC78711E
4. DRAM page mode write cycle
5. DRAM CAS before RAS refresh cycle
No. 5476-10/43
LC78711E
Block Diagram
No. 5476-11/43
LC78711E
Function Overview
1. Crystal clock oscillator; XIN1, XOUT1, XIN2, XOUT2, N/P1, N/P2, FSCO
The XIN1 and XOUT1 pins are connections for an NTSC 14.31818-MHz crystal element, and the XIN2 and XOUT2
pins are connections for a PAL 17.734476-MHz crystal element. The N/P1 pin switches the LC78711E RGB encoder
block between NTSC and PAL modes, and the N/P2 pin switches the decoder block between NTSC and PAL modes.
The FSCO pin outputs a clock signal that is the crystal oscillator frequency divided by 4. The table below enumerates
the pin states vs. the LC78711E operating modes.
XIN1, XOUT1
14.31818 MHz
*
14.30244 MHz
XIN2, XOUT2
N/P1
N/P2
*
H
H
NTSC/M
3.579545 MHz
L
L
PAL/GBIDH
4.433619 MHz
L
H
PAL/M
3.575611 MHz
17.734476 MHz
*
TV format
FSCO
2. Display format; N/P1, N/P2, LINE, CSYNC, SON, 4FSC2, FSCIN, VRESET, HRESET, YS, PALID
• The LC78711E supports both NTSC and PAL modes, with the N/P1 and N/P2 pins being used to set the mode. See
item (1) above for the pin states in the NTSC and PAL modes. The LINE pin switches the number of scan lines in a
1-V period.
• The SON, 4FSC2, FSCIN, VRESET, HRESET, YS, and PALID pins are used with the superimpose function. The
4FSC2 pin inputs a 4 × fsc frequency, and the FSCIN pin inputs the fsc frequency. The VRESET and HRESET
pins input the external video signal VSYNC and HSYNC. The internal V and H counters are reset on the falling
edges of these signals, respectively. The image may be disrupted if the 4FSC2 signal is not locked with the
VRESET and HRESET signals. The YS pin is used to switch the video signal. The PALID pin is used for burst
waveform phase matching in PAL mode.
3. DRAM interface
Interface pins: A0 to A7, DB0 to DB3, RAS, CAS, WE, OE
An external 64k × 4-bit DRAM must be used.
4. Video outputs: VIDEO1, VIDEO2
The luminance signal can be acquired from the VIDEO1 pin.
The chrominance signal can be acquired from the VIDEO2 pin.
No. 5476-12/43
LC78711E
5. Color bar output; CB
If the CB input pin is set high, a color bar signal will be output from the VIDEO1 and VIDEO2 pins. The table below
lists the content of the color bar signal.
R
G
➀ White
F
F
B
F
➁ Gray
B
B
B
➂ Yellow
F
F
O
➃ Cyan
O
F
F
➄ Green
O
F
O
➅ Magenta
F
O
F
➆ Red
F
O
O
➇ Blue
O
O
F
Border (black)
O
O
O
6. Color bar signal output level
• Luminance signal output level (Y signal: VIDEO1, pin 38)
Data value
Output voltage (V)
Luminance level (IRE)
255
4.990
121.9
220
4.648
100
198
4.434
85.7
181
4.268
74.9
155
4.014
58.4
138
3.848
47.6
122
3.691
37.5
105
3.525
26.7
79
3.271
10.2
63
3.125
0
0
2.500
–40
Note: AVDD1 = 5.00 V
No. 5476-13/43
LC78711E
• Chrominance signal output level (C signal: VIDEO2, pin 40)
Data value
Output voltage (V)
Luminance level (IRE)
255
4.990
81.2
211
4.560
52.7
201
4.463
46.3
185
4.306
36.2
166
4.121
24.1
128
3.750
0
90
3.379
–24.1
71
3.193
–36.2
55
3.037
–46.3
45
2.939
–52.7
0
2.500
–81.2
Note: AVDD1 = 5.00 V
Drawing Display Functions
1. Operating mode (scan operation, display operation)
NTSC mode:
• Non-interlaced
60 Hz (262 or 263 lines)
• Dot clock
2fsc: 7.15909 MHz (T = 139.67 ns)
• System clock
4fsc: 14.31818 MHz
PAL mode:
• Non-interlaced
50 Hz (312 or 314 lines)
• Dot clock
4fsc × 2/5: 7.09379 MHz (T = 140.97 ns)
• System clock
4fsc: 17.734476 MHz
2. Display functions
• Display resolution
288 dots × 192 H
• Screen data area
300 dots × 216 H
• 16-color display
16 colors selected from a palette of 4096 colors
No. 5476-14/43
LC78711E
3. Sprite screen (cursor display)
• Sprite screen: Two types, 32 dots × 32 H
• Sprite color: Seven display colors plus transparent display (7 colors selected from 4096 colors)
This color setting selects colors that are independent of the bit-mapped screens.
4. Cross cursor display
• The X and Y coordinates are set.
A cross cursor is displayed at the point corresponding to the specified coordinates.
5. Display window area function
• A rectangular window is specified by specifying the X and Y coordinates for two points.
Either the area within the display window, or the area outside the display window can be specified to be transparent
(border color display).
6. Scrolling display function
• Scrolling in the vertical and horizontal directions
• The scroll amount can be set.
The scroll amount is set in units of 1 to 6 dots in the horizontal direction and 1 to 12 dots in the vertical direction.
Text with 50 characters in the horizontal direction and 18 characters in the vertical direction can be set up in single
character units.
7. Graphics display format
No. 5476-15/43
LC78711E
Writing graphics data
[A] Set up point (Xs, Ys): X is a 9-bit address.
[B] Set up point (Xe, Ye): Y is an 8-bit address.
1. Begin writing color codes from the origin coordinate address (Xs, Ys).
2. If the X direction address (Xs) matches the endpoint address (Xe), reset the X address to the origin address (Xs). At
the same time, increment the Y address by one count.
3. Terminate writing when the endpoint address (Xe, Ye) is reached.
• At termination, reset the address to the origin address (Xs, Ys) and exit.
• Terminate writing even if the CE pin has gone low. In this case, the address will be set to the endpoint address plus
one and the algorithm will exit.
• The address manipulations described above, are for the case where automatic address incrementing has been set up
by command.
1. When writing to the graphics display area, specify the address of the origin [A] to be 6 and the address of the
endpoint [B] to be 11.
2. When writing to a rectangular area, the origin [A] and the endpoint [B] can be set to arbitrary values.
When filling is specified by command, RAM data will be set to the first specified color code.
In this case, it suffices to write the color code that was specified at that point. However, add the condition that the
color code setting must not be changed during the fill operation.
3. When writing a straight line, set either the X (horizontal) values or Y (vertical) values of the origin [A] and endpoint
[B] to the same value.
For example, to draw a straight line in the vertical direction, set the origin [A] to (Xs, Ys) and set the endpoint [B] to
(Xs, Ye).
To draw a straight line in the horizontal direction, set the origin [A] to (Xs, Ys) and set the endpoint [B] to (Xe, Ys).
Filling must be specified by command to write straight lines.
4. Set up the addresses as follows to write scroll data.
For example,
To scroll down, specify 2 as the origin [A] and 7 as the endpoint [B].
To scroll right, specify 5 as the origin [A] and 9 as the endpoint [B].
To scroll left, specify 7 as the origin [A] and 12 as the endpoint [B].
To scroll up, specify 10 as the origin [A] and 15 as the endpoint [B].
Reading out color codes for specific bits
It is possible to read out (not write) the color code for a given dot by using a command to set the origin address (Xs, Ys).
Executing the read out command latches the data into the serial output shift register. The command manipulation
terminates when the data for a single dot has been read out. (The command register is reset.)
Graphics display priority order
1. Cross cursor
2. Sprite A pattern
3. Sprite B pattern
4. Graphics screen
5. Border screen
6. Background screen (not displayed during graphics display)
Note: There are cases where the same pattern is displayed for sprite patterns A and B. Thus the LC78711E may be in a
state of accessing the same sprite RAM. Therefore, a time difference must be set up for the sprite pattern accesses
(reads) for the A and B patterns.
No. 5476-16/43
LC78711E
Microprocessor Interface
1. Data transfer format (for command transfers)
• A command identification code (control item) must be transferred before the data is transferred when setting up
commands, positions (coordinates), or color codes (color table).
• If continuous data transfer mode is not set up, then data transfers of bit map data and sprite (cursor) data also
require that a command identifier code (control item) be transferred before the data is transferred.
• Transfer format (example)
①, ➂, ➄:
➁, ➃, ➅:
➆:
Command identification code (control item)
Command register setup data
Serial transfer completes
2. Transfer format (when continuous data transfer mode has been set up)
• Continuous data transfer mode must be set up by the data (1 byte) that follows a command identification code
(control item). When a RAM data transfer command is set up and the data transfer started, the data that follows (in
byte units) is all acquired as RAM data.
Note: If continuous data transfer mode is set up, the RAM write address must be set (by command) to automatic
increment mode.
• Transfer format (example)
①, ➂:
➁:
➃, ➄, ➅:
➆:
Command identification code (control item)
Command register setup data
RAM data
Serial transfer completes and continuous data transfer mode is cleared.
Note: When continuous data transfer mode is cleared, the command register setting is not reset. If the control
microprocessor immediately issues a RAM data transfer command and starts the data transfer, the
LC78711E will switch to continuous data transfer mode once again.
No. 5476-17/43
LC78711E
3. Transfer format (when a check command is issued)
• Transfer format (example)
➀: Control item (address = first byte: 11hex)
➁: Data (check flags)
Control Commands
First byte
Command
MSB
Second byte
Control item code
LSB MSB
Data
LSB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Register 00hex
(Mode setup)
0
0
0
0
0
0
0
0
INIT
SCP2
SCP1
SCP0
CB
1
0
VRAM/
BG
Register 01hex
(Screen position fine adjustment)
0
0
0
0
0
0
0
1
VP3
VP2
VP1
VP0
HP3
HP2
HP1
HP0
Register 04hex
(Color: RG settings)
0
0
0
0
0
1
0
0
CRG3
CRG2
CRG1
CRG0
CRR3
CRR2
CRR1
CRR0
Register 05hex
(Color: B settings)
0
0
0
0
0
1
0
1
CROS
CRKY
BGCL
0
CRB3
CRB2
CRB1
CRB0
Register 06hex
(Burst phase setting; when SON = 1)
0
0
0
0
0
1
1
0
R/F
0
0
0
0
BST
ON
PH1
PH0
Register 07hex
(YS output phase adjustment)
0
0
0
0
0
1
1
1
0
0
0
0
YT3
YT2
YT1
YT0
Register 08hex
(External synchronization on/off)
0
0
0
0
1
0
0
0
MVMD
EXSN
0
0
TST3
TST2
TST1
TST0
Register 09hex
(Subtitle scrolling: up/down)
0
0
0
0
1
0
0
1
0
0
0
SCV4
SCV3
SCV2
SCV1
SCV0
Register 0Ahex
(Subtitle scrolling: left/right)
0
0
0
0
1
0
1
0
0
0
SCH5
SCH4
SCH3
SCH2
SCH1
SCH0
Register 8Bhex
(Scrolling control: vertical direction)
1
0
0
0
1
0
1
1
SCRV
1
SCRV
0
0
0
SRFV
3
SRFV
2
SRFV
1
SRFV
0
Register 8Chex
(Scrolling control: horizontal direction)
1
0
0
0
1
1
0
0
SCRH
1
SCRH
0
0
0
0
SRFH
2
SRFH
1
SRFH
0
Register 0Dhex
(Graphics mode setup)
0
0
0
0
1
1
0
1
0
0
0
0
0
DCRS
DSPB
DSPA
Register 0Ehex
(Pin PSC1 output control)
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
SRO
ENM
Register 0Fhex
(Pin PSC2 output control)
0
0
0
0
1
1
1
1
0
0
0
0
CRSM
SPBM
SPAM
GPHM
Register 11hex
0
0
0
1
0
0
0
1
0
0
0
0
0
VBLK
EXEC
1
Continued on next page.
No. 5476-18/43
LC78711E
Continued from preceding page.
First byte
Command
MSB
Second byte
Control item code
LSB MSB
Data
LSB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Register 20hex
(Color data settings: R, G)
0
0
1
0
0
0
0
0
SGCG
3
SGCG
2
SGCG
1
SGCG
0
SGCR
3
SGCR
2
SGCR
1
SGCR
0
Register 21hex
(Color data settings: B)
0
0
1
0
0
0
0
1
0
0
0
0
SGCB
3
SGCB
2
SGCB
1
SGCB
0
Register A2hex
(Color data settings)
1
0
1
0
0
0
1
0
0
0
0
0
SCPC
3
SCPC
2
SCPC
1
SCPC
0
Register A3hex
(Border color setting)
1
0
1
0
0
0
1
1
0
0
0
0
SBDC
3
SBDC
2
SBDC
1
SBDC
0
Register 24hex
(Bit map address setting)
0
0
1
0
0
1
0
0
BMAY
7
BMAY
6
BMAY
5
BMAY
4
BMAY
3
BMAY
2
BMAY
1
BMAY
0
Register 25hex
(Bit map address setting)
0
0
1
0
0
1
0
1
BMAX
7
BMAX
6
BMAX
5
BMAX
4
BMAX
3
BMAX
2
BMAX
1
BMAX
0
Register 26hex
(Write control setting)
0
0
1
0
0
1
1
0
0
R/W
0
STRP/
ENDP
FILL
COLR
BMAI
BMDF
BMAX
8
Register A7hex
(Bit map data setting)
1
0
1
0
0
1
1
1
BMD7
BMD6
BMD5
BMD4
BMD3
BMD2
BMD1
BMD0
Register 28hex
(Color data settings: R, G)
0
0
1
0
1
0
0
0
SSPG
3
SSPG
2
SSPG
1
SSPG
0
SSPR
3
SSPR
2
SSPR
1
SSPR
0
Register 29hex
(Color data settings: B)
0
0
1
0
1
0
0
1
0
0
0
0
SSPB
3
SSPB
2
SSPB
1
SSPB
0
Register AAhex
(Sprite settings)
1
0
1
0
1
0
1
0
0
0
0
0
0
SSPC
2
SSPC
1
SSPC
0
Register 2Bhex
(Sprite address Y setting)
0
0
1
0
1
0
1
1
0
0
0
SPAR
Y4
SPAR
Y3
SPAR
Y2
SPAR
Y1
SPAR
Y0
Register 2Chex
(Sprite address X setting)
0
0
1
0
1
1
0
0
0
0
0
SPAR
X4
SPAR
X3
SPAR
X2
SPAR
X1
SPAR
X0
Register 2Dhex
(Write control settings)
0
0
1
0
1
1
0
1
0
0
0
0
WSP2
WSP1
SPAI
SPDF
Register AEhex
(Sprite data setting)
1
0
1
0
1
1
1
0
0
SPD6
SPD5
SPD4
0
SPD2
SPD1
SPD0
Register 2Fhex
(Sprite A and B settings)
0
0
1
0
1
1
1
1
0
0
0
0
0
SPRT
ARA
SPSB
SPSA
Register 30hex
(Sprite display address Y setting)
0
0
1
1
0
0
0
0
SPDA
Y7
SPDA
Y6
SPDA
Y5
SPDA
Y4
SPDA
Y3
SPDA
Y2
SPDA
Y1
SPDA
Y0
Register 31hex
(Sprite display address X setting)
0
0
1
1
0
0
0
1
SPDA
X7
SPDA
X6
SPDA
X5
SPDA
X4
SPDA
X3
SPDA
X2
SPDA
X1
SPDA
X0
Register 32hex
(Sprite display address setting control)
0
0
1
1
0
0
1
0
0
0
0
0
WSPB
WSPA
0
SPDA
X8
Register 33hex
(Display window setting: Y)
0
0
1
1
0
0
1
1
WDYS
7
WDYS
6
WDYS
5
WDYS
4
WDYS
3
WDYS
2
WDYS
1
WDYS
0
Register 34hex
(Display window setting: X)
0
0
1
1
0
1
0
0
WDXS
7
WDXS
6
WDXS
5
WDXS
4
WDXS
3
WDXS
2
WDXS
1
WDXS
0
Register 35hex
(Display window: X; display area settings)
0
0
1
1
0
1
0
1
0
0
WDEN
WDAR
PAL
60
SADR/
EADR
0
WDXS
8
Register 36hex
(Cross cursor display position setting: X)
0
0
1
1
0
1
1
0
CRAX
7
CRAX
6
CRAX
5
CRAX
4
CRAX
3
CRAX
2
CRAX
1
CRAX
0
Register 37hex
(Cross cursor display position setting: Y)
0
0
1
1
0
1
1
1
CRAY
7
CRAY
6
CRAY
5
CRAY
4
CRAY
3
CRAY
2
CRAY
1
CRAY
0
No. 5476-19/43
LC78711E
Command Descriptions
Note: 1. After a hardware reset, always first send register 00 command, and only then issue the various commands. The
LC78711E may operate incorrectly if a register 00 command is not issued.
Note: 2. All data transfers must be performed LSB first.
Note: 3. The (0) and (1) notations in the second byte indicate the default values.
1. Register 00hex
• Data7: INIT
— Function: System reset
— Operation: INIT = 0: The LC78711E internal state is not reset (normal operation continues)
INIT = 1: The internal state is reset (The display is set to a blue background screen.)
• Data6: SCP2
Data5: SCP1
Data4: SCP0
— Function: YS output (pin 46) control
— Operation: SCP2 = 0: When (SCP0, SCP1) is (0,0) or (0,1), the whole screen is set to low (transparent) if the
comparison condition did not hold.
SCP2 = 1: When (SCP0, SCP1) is (0,0) or (0,1), the whole screen is set to high (display) if the
comparison condition did not hold.
The superimpose mode comparison condition is determined by the SCP1 and SCP2 setting.
(Only valid when pin 60, SON, is 1)
SCP1
SCP0
0
0
No comparison performed
Comparison condition (YS pin output operation setting)
1
0
If the border color was not black, YS is set to high (display) for sections that do not match
the border color, and set to low (transparent) for all other sections.
1
1
Sets YS high for sections that do not match the chroma key color, and low for all other
sections.
• Data3: CB
— Function: Color bar screen output setting
— Operation: CB = 0: The graphics signal is output.
CB = 1: A color bar signal is output.
• Data2: 1
— Operation: This bit must always be set to 1. The LC78711E may not operate correctly if this bit is not set to 1.
• Data1: 0
— Operation: This bit must always be set to 0. The LC78711E may not operate correctly if this bit is not set to 0.
• Data0: VRAM/BG
— Function: Switches the displayed screen
— Operation: VRAM/BG = 0: Displays the contents of VRAM
VRAM/BG = 1: Displays the background color
No. 5476-20/43
LC78711E
2. Register 01hex
• Data7: VP3
Data6: VP2
Data5: VP1
Data4: VP0
— Function: These bits set the vertical direction display start position.
— Operation: Sets the display position as a two’s complement value with positive indicating up in the vertical
direction. The position is set in two dot units, supporting a range of from –16 to +14 dots from the
center position.
• Data3: HP3
Data2: HP2
Data1: HP1
Data0: HP0
— Function: These bits set the horizontal direction display start position.
— Operation: Sets the display position as a two’s complement value with positive indicating left in the horizontal
direction. The position is set in two dot units, supporting a range of from –16 to +14 dots from the
center position.
3. Register 04hex
• Data7: CRG3
Data6: CRG2
Data5: CRG1
Data4: CRG0
— Function:
— Operation:
• Data3: CRR3
Data2: CRR2
Data1: CRR1
Data0: CRR0
— Function:
— Operation:
The green color data setting
Specifies the green color data. There are 16 values in the range 0 to F (hexadecimal).
The red color data setting
Specifies the red color data. There are 16 values in the range 0 to F (hexadecimal).
No. 5476-21/43
LC78711E
4. Register 05hex
• Data7: CROS
— Function: Cross cursor display color setting
— Operation: Acquires the color set in bits CRR3:0, CRG3:0, and CRB3:0 as the cross cursor display color.
• Data6: CRKY
— Function: Chroma key color setting
— Operation: Acquires the color set in bits CRR3:0, CRG3:0, and CRB3:0 as the chroma key color.
• Data5: BGCL
— Function: Background color setting
— Operation: Acquires the color set in bits CRR3:0, CRG3:0, and CRB3:0 as the background color.
• Data4: Unused (Must be set to 0.)
• Data3: CRB3
Data2: CRB2
Data1: CRB1
Data0: CRB0
— Function: The blue color data setting
— Operation: Specifies the blue color data. There are 16 values in the range 0 to F (hexadecimal).
5. Register 06hex
• Data7: R/F
— Function: Color burst phase timing setting during superimpose operation
— Operation: R/F = 0: Set to the rising edge of the 4fsc clock
R/F = 1: Set to the falling edge of the 4fsc clock
• Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
Data3: Unused (Must be set to 0.)
• Data2: BSTON
— Function: Color burst signal output control setting during superimpose operation
— Operation: BSTON = 0: Burst signal output is turned off
BSTON = 1: Burst signal output is turned on
No. 5476-22/43
LC78711E
• Data1: PH1
Data0: PH0
— Function: Color burst signal phase setting during superimpose operation
— Operation:
PH1
PH0
0
0
Phase
0°
0
1
90°
1
0
180°
1
1
270°
6. Register 07hex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
• Data3: YT3
Data2: YT2
Data1: YT1
Data0: YT0
— Function: YS (pin 46) output phase adjustment setting
— Operation: Sets the YS output timing in single 4fsc clock units. The default is a phase setting identical to that of
the video output.
7. Register 08hex
• Data7: MVMD
— Function: Moving display area setting during superimpose operation
— Operation: MVMD = 0: Only the display area moves
MVMD = 1: The area including the border area moves (only left and right motion is possible with
this setting.)
No. 5476-23/43
LC78711E
• Data6: EXSN
— Function: Synchronizing signal reset control setting for external synchronization mode, i.e., when SON = 1.
— Operation: EXSN = 0: Reset is executed on the falling edge of the HRESET (pin 54) and VRESET (pin 56)
signals.
EXSN = 1: Reset is executed on the falling edge of the VRESET (pin 56) signal. (The HRESET
signal is not required.)
• Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
• Data3: TST3
Data2: TST2
Data1: TST1
Data0: TST0
— Function: Test mode settings
— Operation: These bits must be set to 0 during normal operation.
8. Register 09hex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
• Data4: SCV4
Data3: SCV3
Data2: SCV2
Data1: SCV1
Data0: SCV0
— Function: Subtitle scrolling amount (vertical direction setting in character units)
— Operation: Scrolls the screen display position up in character units. The scrolling amount can be set to a value
in the range 0 to 17 characters, where a single character is 12 vertical dots (12 H).
9. Register 0Ahex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
No. 5476-24/43
LC78711E
• Data5: SCH5
Data4: SCH4
Data3: SCH3
Data2: SCH2
Data1: SCH1
Data0: SCH0
— Function: Subtitle scrolling horizontal direction setting
— Operation: Scrolls the screen display position to the left in character units. The scrolling amount can be set to a
value in the range 0 to 49 characters, where a single character is 6 horizontal dots.
10. Register 8Bhex
• Data7: SCRV1
Data6: SCRV0
— Function: Scrolling function vertical direction setting
— Operation:
SCRV0
SCRV1
0
0
Scroll direction
Do not scroll
0
1
Scroll down
1
0
Scroll up
1
1
Illegal value
• Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
• Data3: SRFV3
Data2: SRFV2
Data1: SRFV1
Data0: SRFV0
— Function: Scrolling adjustment setting in dot units
— Operation: Scrolls the screen display position up or down in dot units. The amount of the scrolling is 0 to 12
dots.
No. 5476-25/43
LC78711E
11. Register 8Chex
• Data7: SCRH1
Data6: SCRH0
— Function: Scrolling left/right motion in dot units
— Operation:
SCRH0
SCRH1
0
0
Scroll direction
Do not scroll
0
1
Scroll right
1
0
Scroll left
1
1
Illegal value
• Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
Data3: Unused (Must be set to 0.)
• Data2: SRFH2
Data1: SRFH1
Data0: SRFH0
— Function: Scroll adjustment setting (in dot units)
— Operation: Scrolls the screen display position to the left or right in dot units. The amount of the scrolling is 0 to
6 dots.
12. Register 0Dhex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
Data3: Unused (Must be set to 0.)
• Data2: DCRS
— Function: Cross cursor display control setting
— Operation: DCRS = 0: Cursor display off
DCRS = 1: Cursor display on
No. 5476-26/43
LC78711E
• Data1: DSPB
— Function: Sprite pattern B display control setting
— Operation: DSPB = 0: Sprite B display off
DSPB = 1: Sprite B display on
• Data0: DSPA
— Function: Sprite pattern A display control setting
— Operation: DSPA = 0: Sprite A display off
DSPA = 1: Sprite A display on
13. Register 0Ehex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
Data3: Unused (Must be set to 0.)
Data2: Unused (Must be set to 0.)
Data1: Unused (Must be set to 0.)
• Data0: SROENM
— Function: Output signal setting for the PSC1 pin (pin 12)
— Operation: Controls whether or not the serial output data setup complete flag is output from the PCS1 pin.
SROENM = 0: The flag is not output.
SROENM = 1: The flag is output.
14. Register 0Fhex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
• Data3: CRSM
— Function: Output signal setting for the PSC2 pin (pin 13)
— Operation: Controls whether or not the PSC2 pin output monitors the cross cursor display state.
CRSM = 0: The cursor state is not monitored.
CRSM = 1: The cross cursor display state is monitored.
A high level is output when the cross cursor is displayed.
No. 5476-27/43
LC78711E
• Data2: SPBM
— Function: Output signal setting for the PSC2 pin (pin 13)
— Operation: Controls whether or not the PSC2 pin output monitors the sprite pattern B display state.
SPBM = 0: The sprite state is not monitored.
SPBM = 1: The sprite B display state is monitored.
A high level is output when the sprite B pattern is displayed.
• Data1: SPAM
— Function: Output signal setting for the PSC2 pin (pin 13)
— Operation: Controls whether or not the PSC2 pin output monitors the sprite pattern A display state.
SPAM = 0: The sprite state is not monitored.
SPAM = 1: The sprite A display state is monitored.
A high level is output when the sprite A pattern is displayed.
• Data0: GPHM
— Function: Output signal setting for the PSC2 pin (pin 13)
— Operation: Controls whether or not the PSC2 pin output monitors the state of the graphics display mode setting.
GPHM = 0: The display state is not monitored.
GPHM = 1: The graphics display mode setting state is monitored.
A high level is output when the LC78711E is operating in graphics display mode.
15. Register 11hex
• Data7: 0
Data6: 0
Data5: 0
Data4: 0
Data3: 0
• Data2: VBLK
— Function: Vertical blanking (vertical return) period indicator
— Operation: Outputs a 1 during the vertical blanking period.
VBLK = 0: Not a vertical blanking period.
VBLK = 1: Display is in a vertical blanking period.
NTSC mode: A 19H period
PAL mode: A 25H period
• Data1: EXEC
— Function: Command execution state
— Operation: Outputs the LC78711E command execution state.
EXEC = 0: Command execution in progress
EXEC = 1: Command wait state
• Data0: 1
No. 5476-28/43
LC78711E
16. Register 20hex
• Data7: SGCG3
Data6: SGCG2
Data5: SGCG1
Data4: SGCG0
— Function: Drawing color setting (Green level setting for the color palette specified color)
— Operation: These 4 bits specify the green level. (0hex to Fhex)
• Data3: SGCR3
Data2: SGCR2
Data1: SGCR1
Data0: SGCR0
— Function: Drawing color setting (Red level setting for the color palette specified color)
— Operation: These 4 bits specify the red level. (0hex to Fhex)
17. Register 21hex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
• Data3: SGCB3
Data2: SGCB2
Data1: SGCB1
Data0: SGCB0
— Function: Drawing color setting (Blue level setting for the color palette specified color)
— Operation: These 4 bits specify the blue level. (0hex to Fhex)
No. 5476-29/43
LC78711E
18. Register A2hex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
• Data3: SCPC3
Data2: SCPC2
Data1: SCPC1
Data0: SCPC0
— Function: Color palette color setting
— Operation: Sets up the color specified in registers 20 and 21 at the color palette address specified by these 4 bits.
19. Register A3hex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
• Data3: SBDC3
Data2: SBDC2
Data1: SBDC1
Data0: SBDC0
— Function: Border color specification
— Operation: Selects the border color from the 16 colors in the color palette.
No. 5476-30/43
LC78711E
20. Register 24hex
• Data7: BMAY7
Data6: BMAY6
Data5: BMAY5
Data4: BMAY4
Data3: BMAY3
Data2: BMAY2
Data1: BMAY1
Data0: BMAY0
— Function: Bit map address specification
— Operation: Specifies the bit map vertical direction (Y coordinate). The range of valid settings is from 00hex to
B7hex (00oct to 215oct). Values of B8hex or larger are illegal.
21. Register 25hex
• Data7: BMAX7
Data6: BMAX6
Data5: BMAX5
Data4: BMAX4
Data3: BMAX3
Data2: BMAX2
Data1: BMAX1
Data0: BMAX0
— Function: Bit map address specification
— Operation: These 8 bits plus the Data0 bit (BMAX8) of register 26hex (for a total of 9 bits), specify the bit map
horizontal direction (X coordinate). The range of valid settings is from 000hex to 12Bhex (000oct to
299oct). Values of 12Chex or larger are illegal.
No. 5476-31/43
LC78711E
22. Register 26hex
• Data7: Unused (Must be set to 0.)
• Data6: R/W
— Function: Bit map data area read/write mode setting
— Operation: Sets the bit map data to read or write mode.
R/W = 0: Bit map data area set to write mode
R/W = 1: Bit map data area set to read mode
• Data5: Unused (Must be set to 0.)
• Data4: STRP/ENDP
— Function: Bit map data setup area start or stop coordinate selection
— Operation: Loads the coordinates set up by registers 24hex, 25hex, and the Data0 bit (BMAX8) of this register
into the bit map data setup area start or stop address.
STRP/ENDP = 0: Sets the start coordinates.
STRP/ENDP = 1: Sets the stop coordinates.
• Data3: FILLCOLR
— Function: Bit map area color palette color fill operation setup
— Operation: Fills the bit map area specified with STRP/ENDP with the color palette color specified by the 4 bits
Data3 to Data0 (BMD3 to BMD0) in register A7hex.
The execution of the fill operation starts after the color palette is set with register A7hex.
FILLCOLR = 0: Fill operation not set up.
FILLCOLR = 1: Sets up a fill operation.
• Data2: BMAI
— Function: Automatic bit map address increment during bit map data write setting
— Operation: Specifies whether or not the bit map address is automatically incremented during bit map data write
operations.
If automatic incrementing is not specified, the application must specify the address in registers
24hex, 25hex, and 26hex after every data transfer.
BMAI = 0: The address is not automatically incremented.
BMAI = 1: The address is automatically incremented.
• Data1: BMDF
— Function: Bit map data transfer item count setting
— Operation: Specifies whether data is transferred in dot units or in two-dot units during bit map data transfers.
This is a setting that determines whether only the lower 4 bits or all 8 bits are transferred in register
A7hex data transfers.
BMDF = 0: Takes only the lower 4 bits as data.
BMDF = 1: Takes all 8 bits as data.
Here, the lower 4 bits of data are taken as the first data item, and the upper 4 bits are
taken as the next data item.
Note: BMDF must be set to 0 when BMAI is set to 0, i.e. when automatic address incrementing is not used.
No. 5476-32/43
LC78711E
• Data0: BMAX8
— Function: Bit map address specification
— Operation: This bit plus the Data0 to Data7 bits (BMAX0 to BMAX7) of register 25hex (for a total of 9 bits),
specify the bit map horizontal direction (X coordinate). The range of valid settings is from 000hex
to 12Bhex (000oct to 299oct). Values of 12Chex or larger are illegal.
23. Register A7hex
• Data7: BMD7
Data6: BMD6
Data5: BMD5
Data4: BMD4
— Function: Bit map data setting
— Operation: The color palette color specified by these 4 bits is loaded into the specified bit map coordinate, i.e.,
is written to VRAM.
This data is valid when BMAI is 1 and BMDF is 1.
• Data3: BMD3
Data2: BMD2
Data1: BMD1
Data0: BMD0
— Function: Bit map data setting
— Operation: The color palette color specified by these 4 bits is loaded into the specified bit map coordinates, i.e.,
is written to VRAM.
24. Register 28hex
• Data7: SSPG3
Data6: SSPG2
Data5: SSPG1
Data4: SSPG0
— Function: Sprite color setting (Sets the green level for the specified color in the sprite color palette.)
— Operation: These 4 bits specify the green level. (0hex to Fhex)
No. 5476-33/43
LC78711E
• Data3: SSPR3
Data2: SSPR2
Data1: SSPR1
Data0: SSPR0
— Function: Sprite color setting (Sets the red level for the specified color in the sprite color palette.)
— Operation: These 4 bits specify the red level. (0hex to Fhex)
25. Register 29hex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
• Data3: SSPB3
Data2: SSPB2
Data1: SSPB1
Data0: SSPB0
— Function: Sprite color setting (Sets the blue level for the specified color in the sprite color palette.)
— Operation: These 4 bits specify the blue level. (0hex to Fhex)
26. Register AAhex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
Data3: Unused (Must be set to 0.)
• Data2: SSPC2
Data1: SSPC1
Data0: SSPC0
— Function: Sprite color palette color setting
— Operation: The color specified by registers 28 and 29 is stored at the color palette address specified by these
3 bits.
No. 5476-34/43
LC78711E
27. Register 2Bhex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
• Data4: SPARY4
Data3: SPARY3
Data2: SPARY2
Data1: SPARY1
Data0: SPARY0
— Function: Sprite pattern address specification
— Operation: Specifies the sprite pattern vertical direction (Y coordinate). The range of valid settings is from
00hex to 1Fhex (00oct to 31oct).
28. Register 2Chex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
• Data4: SPARX4
Data3: SPARX3
Data2: SPARX2
Data1: SPARX1
Data0: SPARX0
— Function: Sprite pattern address specification
— Operation: Specifies the sprite pattern horizontal direction (X coordinate). The range of valid settings is from
00hex to 1Fhex (00oct to 31oct).
No. 5476-35/43
LC78711E
29. Register 2Dhex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
• Data3: WSP2
— Function: Data write to sprite pattern 2 setup.
— Operation: Sets up data writes to sprite pattern 2.
WSP2 = 0: Does not set up data writes to sprite pattern 2.
WSP2 = 1: Sets up data writes to sprite pattern 2.
• Data2: WSP1
— Function: Data write to sprite pattern 1 setup
— Operation: Sets up data writes to sprite pattern 1.
WSP1 = 0: Does not set up data writes to sprite pattern 1.
WSP1 = 1: Sets up data writes to sprite pattern 1.
• Data1: SPAI
— Function: Automatic increment setting for the sprite address during sprite data writes
— Operation: Specifies whether or not the sprite address is automatically incremented during sprite data writes.
If automatic incrementing is not specified, the application must specify the address in registers
2Bhex and 2Chex after every data transfer.
SPAI = 0: The address is not automatically incremented.
SPAI = 1: The address is automatically incremented.
• Data0: SPDF
— Function: Setting for the number of data items transferred during sprite data transfers
— Operation: Specifies whether data is transferred in dot units or in two dot units during sprite data transfers.
This is a setting that determines whether only the lower 3 bits or the lower 3 bits and the upper 3 bits
are transferred in register AEhex data transfers.
SPDF = 0: Takes only the lower 3 bits as data.
SPDF = 1: Also process the 3 bits Data6 to Data4 as data.
Here, the lower 3 bits of data are processed as the first data item, and the upper 3 bits
become the data for the next bit map address.
Note: SPDF must be set to 0 when SPAI is set to 0, i.e. when automatic address incrementing is not used.
No. 5476-36/43
LC78711E
30. Register AEhex
• Data7: Unused (Must be set to 0.)
• Data6: SPD6
Data5: SPD5
Data4: SPD4
— Function: Bit map data settings
— Operation: The color palette color specified by these 3 bits is loaded at the specified sprite coordinate.
This data is valid when SPAI is 1 and SPDF is 1.
• Data3: Unused (Must be set to 0.)
• Data2: SPD2
Data1: SPD1
Data0: SPD0
— Function: Bit map data settings
— Operation: The color palette color specified by these 3 bits is loaded at the specified sprite coordinate.
31. Register 2Fhex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
Data3: Unused (Must be set to 0.)
• Data2: SPRTARA
— Function: Sprite pattern display area setting
— Operation: Sets whether the sprite pattern display area is limited to the drawing area or is set to the whole
image area, i.e., the sprite pattern can also be displayed outside the drawing area.
SPRTARA = 0: Display only in the drawing area.
SPRTARA = 1: Display outside the drawing area also allowed.
• Data1: SPSB
— Function: Selection of sprite pattern 1 or 2 as the sprite B display pattern
— Operation: Selects whether sprite pattern 1 or 2 is displayed as the sprite B display pattern. This is selection of
the pattern whose display is turned on by the Data1 (DSPB) bit in register 0Dhex.
SPSB = 0: Sprite pattern 1 is displayed.
SPSB = 1: Sprite pattern 2 is displayed.
No. 5476-37/43
LC78711E
• Data0: SPSA
— Function: Selection of sprite pattern 1 or 2 as the sprite A display pattern
— Operation: Selects whether sprite pattern 1 or 2 is displayed as the sprite A display pattern. This is selection of
the pattern whose display is turned on by the Data0 (DSPA) bit in register 0Dhex.
SPSA = 0: Sprite pattern 1 is displayed.
SPSA = 1: Sprite pattern 2 is displayed.
Note: When the same pattern is selected for both sprites A and B, two instances of the same pattern are displayed.
32. Register 30hex
• Data7: SPDAY7
Data6: SPDAY6
Data5: SPDAY5
Data4: SPDAY4
Data3: SPDAY3
Data2: SPDAY2
Data1: SPDAY1
Data0: SPDAY0
— Function: Sprite display address setting
— Operation: Specifies the sprite display vertical direction (Y coordinate). The range of valid settings is from
00hex to B7hex (00oct to 215oct). Values of B8hex or larger are illegal.
33. Register 31hex
• Data7: SPDAX7
Data6: SPDAX6
Data5: SPDAX5
Data4: SPDAX4
Data3: SPDAX3
Data2: SPDAX2
Data1: SPDAX1
Data0: SPDAX0
— Function: Sprite display address setting
— Operation: These 8 bits plus the Data0 bit (SPDAX8) of register 32hex (for a total of 9 bits), specify the sprite
display horizontal direction (X coordinate). The range of valid settings is from 000hex to 12Bhex
(000oct to 299oct). Values of 12Chex or larger are illegal.
No. 5476-38/43
LC78711E
34. Register 32hex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
Data5: Unused (Must be set to 0.)
Data4: Unused (Must be set to 0.)
• Data3: WSPB
— Function: Sprite B display start address write control
— Operation: Sets the address specified as the sprite display address as the sprite B display start address.
WSPB = 0: No setting performed.
WSPB = 1: Sets the address.
• Data2: WSPA
— Function: Sprite A display start address write control
— Operation: Sets the address specified as the sprite display address as the sprite A display start address.
WSPA = 0: No setting performed.
WSPA = 1: Sets the address.
• Data1: Unused (Must be set to 0.)
• Data0: SPDAX8
— Function: Sprite address specification
— Operation: The Data0 to Data7 bits (SPDAX0 to SPDAX7) in register 31 and this bit of this register (for a total
of 9 bits) specify the sprite horizontal direction (X coordinate). The range of valid settings is from
000hex to 12Bhex (000oct to 299oct). Values of 12Chex or larger are illegal.
35. Register 33hex
• Data7: WDYS7
Data6: WDYS6
Data5: WDYS5
Data4: WDYS4
Data3: WDYS3
Data2: WDYS2
Data1: WDYS1
Data0: WDYS0
— Function: Display window address specification
— Operation: Specifies the display window vertical direction (Y coordinate). The range of valid settings is from
00hex to B7hex (00oct to 215oct). Values of B8hex or larger are illegal.
No. 5476-39/43
LC78711E
36. Register 34hex
• Data7: WDXS7
Data6: WDXS6
Data5: WDXS5
Data4: WDXS4
Data3: WDXS3
Data2: WDXS2
Data1: WDXS1
Data0: WDXS0
— Function: Sprite display address specification
— Operation: These 8 bits plus the Data0 bit (WDXS8) of register 35hex (for a total of 9 bits), specify the bit map
horizontal direction (X coordinate). The range of valid settings is from 000hex to 12Bhex (000oct to
299oct). Values of 12Chex or larger are illegal.
37. Register 35hex
• Data7: Unused (Must be set to 0.)
Data6: Unused (Must be set to 0.)
• Data5: WDEN
— Function: Display window display setting
— Operation: Sets display window display.
WDEN = 0: The display window is not displayed.
WDEN = 1: The display window is displayed.
• Data4: WDAR
— Function: Display window display area setting
— Operation: Sets the display window display area.
WDAR = 0: Displays the inside of the display window
WDAR = 1: Displays the outside of the display window
• Data3: PAL60
— Function: PAL60 mode setting (Valid only when N/P1 and N/P2 are 0.)
— Operation: PAL60 = 0: PAL mode
PAL60 = 1: PAL60 mode
No. 5476-40/43
LC78711E
• Data2: SADR/EADR
— Function: Display window display coordinates setting
— Operation: Sets the display window display area.
SADR/EADR = 0: Sets the display window start address.
SADR/EADR = 1: Sets the display window end address.
• Data1: Unused (Must be set to 0.)
• Data0: WDXS8
— Function: Display window address setting
— Operation: The Data0 to Data7 bits (WDXS0 to WDXS7) in register 34 and this bit of this register (for a total
of 9 bits) specify the sprite horizontal direction (X coordinate). The range of valid settings is from
000hex to 12Bhex (000oct to 299oct). Values of 12Chex or larger are illegal.
38. Register 36hex
• Data7: CRAX7
Data6: CRAX6
Data5: CRAX5
Data4: CRAX4
Data3: CRAX3
Data2: CRAX2
Data1: CRAX1
Data0: CRAX0
— Function: Cross cursor position setting
— Operation: Specifies the horizontal direction (X coordinate) for the cross cursor intersection point. This setting
sets the position in 2-dot units.
No. 5476-41/43
LC78711E
39. Register 37hex
• Data7: CRAY7
Data6: CRAY6
Data5: CRAY5
Data4: CRAY4
Data3: CRAY3
Data2: CRAY2
Data1: CRAY1
Data0: CRAY0
— Function: Cross cursor position setting
— Operation: Specifies the vertical direction (Y coordinate) for the cross cursor intersection point. This setting
sets the position in 2-dot units.
Note: The register 0Dhex Data 3 bit (DCRS) setting is required for execution of the cross cursor display function.
No. 5476-42/43
LC78711E
NTSC Sample Application Circuit
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of December, 1997. Specifications and information herein are subject to
change without notice.
No. 5476-43/43