INTEGRATED CIRCUITS 74F164 8-bit serial-in parallel-out shift register Product specification IC15 Data Handbook 1995 Sep 22 Philips Semiconductors Product specification 8-bit serial-in parallel-out shift register FEATURES 74F164 PIN CONFIGURATION • Gated serial data inputs • Typical shift frequency of 100MHz • Asynchronous Master Reset • Buffered clock and data inputs • Fully synchronous data transfer • Industrial temperature range available (–40°C to +85°C) DESCRIPTION Dsa 1 14 VCC Dsb 2 13 Q7 Q0 3 12 Q6 Q1 4 11 Q5 Q2 5 10 Q4 Q3 6 9 MR GND 7 8 CP The 74F164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered through one of two inputs (Dsa, Dsb); either input can be used as an active High enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied High. SF00717 TYPE Data shifts one place to the right on each Low-to-High transition of the clock (CP) input, and enters into Q0 the logical AND of the two data inputs (Dsa, Dsb) that existed one setup time before the rising edge. A Low level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs Low. TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL) 100MHz 33mA 74F164 ORDERING INFORMATION ORDER CODE DRAWING NUMBER DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C 14-pin plastic DIP 74F164N I74F164N SOT27-1 14-pin plastic SO 74F164D I74F164D SOT108-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Data inputs 1.0/1.0 20µA/0.6mA CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.6mA MR Master reset input (active-Low) 1.0/1.0 20µA/0.6mA Data outputs 50/33 1.0mA/20mA PINS DESCRIPTION Dsa, Dsb Q0 – Q7 One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL SRG8 8 9 1 2 1 8 CP 9 MR Dsa 2 Dsb C1/→ R & 1D 3 4 5 Q0 Q1 Q3 Q4 Q0 Q1 Q3 Q4 6 10 3 4 5 6 10 11 12 13 11 12 13 VCC = Pin 14 GND = Pin 7 1995 Sep 22 SF00714 SF00713 2 853-0348 15794 Philips Semiconductors Product specification 8-bit serial-in parallel-out shift register 74F164 LOGIC DIAGRAM Dsa Dsb CP 1 D 2 Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q CP RD 8 MR 9 3 VCC = Pin 14 GND = Pin 7 4 Q0 5 Q1 6 Q2 10 Q4 Q3 11 Q5 12 Q6 13 Q7 SF00715 FUNCTION TABLE INPUTS OUTPUTS MR CP Dsa Dsb H h L l qn X ↑ Q0 Q1 Q2 Q3 Q4 OPERATING MODE Q5 Q6 Q7 L X X X L L L L L L L L H ↑ l l L q0 q1 q2 q3 q4 q5 q6 H ↑ l h L q0 q1 q2 q3 q4 q5 q6 H ↑ h l L q0 q1 q2 q3 q4 q5 q6 H ↑ h h H q0 q1 q2 q3 q4 q5 q6 = = = = = = = Reset (Clear) Shift High voltage level High voltage level one setup time prior to the Low-to-High clock transition. Low voltage level Low voltage level one setup time prior to the Low-to-High clock transition. Lower case letter indicate the state of the referenced output one setup time prior to the Low-to-High clock transition. Don’t care Low-to-High clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 40 mA Tambb Operating temperature O erating free-air tem erature range Tstg Storage temperature range Commercial Range 0 to +70 Industrial Range –40 to +85 –65 to +150 °C °C RECOMMENDED OPERATING CONDITIONS LIMIT SYMBOL PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 V VIH High-level iput voltage 2.0 VIL Low-level input voltage 0.8 V V IIk Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tambb 1995 Sep 22 Operating O erating free-air tem temperature erature range Commercial Range 0 +70 Industrial Range –40 +85 3 °C Philips Semiconductors Product specification 8-bit serial-in parallel-out shift register 74F164 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) TEST SYMBOL PARAMETER VOH High-level out output ut voltage VOL Low-level output voltage VIK LIMITS CONDITIONS1 VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOL= MAX Input clamp voltage VCC = MIN, II = IIK MIN ±10%VCC 2.5 ±5%VCC 2.7 TYP2 UNIT MAX V 3.4 V ±10%VCC 0.30 0.50 V ±5%VCC 0.30 0.50 V –0.73 –1.2 V II Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IILL Low-level input current VCC = MAX, VI = 0.5V IOS Short-circuit output current3 VCC = MAX ICC Supply current (total)4 VCC = MAX -60 33 –0.6 mA –150 mA 55 mA Notes to DC electrical characteristics 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter test, IOS tests should be performed last. 4. Measure ICC with the serial inputs grounded, the clock input at 2.4V, and a momentary ground, then applied to Master Reset, and all outputs open. APPLICATION RESET CLOCK CP DATA CP MR 74F164 ENABLE 74F164 Dsb H Dsb Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 The 74F164 can be cascaded to form synchronous shift registers of longer length. Here, two devices are combined to form a 16-bit shift register. 1995 Sep 22 MR Dsa Dsa Q2 Q3 Q4 Q5 Q6 Q7 SF00716 4 Philips Semiconductors Product specification 8-bit serial-in parallel-out shift register 74F164 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C +25 C VCC = 5V CL = 50pF RL = 500Ω Tamb = 0°C 0 C to +70°C +70 C VCC = +5V±10% CL = 50pF RL = 500Ω MIN TYP 80 100 Propagation delay CP to Qn Waveform 1 3.0 5.0 5.0 7.0 8.0 10.0 2.5 5.0 9.0 11.0 2.5 5.0 9.0 11.0 ns Propagation delay MR to Qn Waveform 3 5.5 7.5 10.5 5.5 11.5 5.5 11.5 ns Maximum clock frequency tPLH tPHL tPHL MIN MAX 80 MIN UNIT Waveform 1 fmax MAX Tamb = –40°C 40 C to +85°C +85 C VCC = +5V±10% CL = 50pF RL = 500Ω MAX 80 MHz AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C +25 C VCC = 5V CL = 50pF RL = 500Ω MIN TYP Tamb = 0°C 0 C to +70°C +70 C VCC = +5V±10% CL = 50pF RL = 500Ω MAX MIN MAX Tamb = –40°C 40 C to +85°C +85 C VCC = +5V±10% CL = 50pF RL = 500Ω MIN UNIT MAX ts(H) tS(L) Setup time, High or Low Dn to CP Waveform 2 7.0 7.0 7.0 7.0 7.0 7.0 ns th(H) th(L) Hold time, High or Low Dn to CP Waveform 2 1.0 1.0 2.0 2.0 2.0 2.0 ns tw(H) tw(L) CP Pulse width High or Low Waveform 1 4.0 7.0 4.0 7.0 4.0 7.0 ns tw(L) MR Pulse wicth Low Waveform 3 7.0 7.0 7.0 ns tREC Recovery time MR to CP Waveform 3 7.0 7.0 7.0 ns AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fmax MR CP VM VM VM tw(H) tw(L) tPHL tw(L) VM Qn VM VM tPLH VM tREC VM CP tPHL SF00294 Qn Waveform 1. Propagation delay for Clock input to output, Clock Pulse width, and maximum Clock frequency VM SF00158 Waveform 3. Master Reset pulse width, Master Reset to output delay and Master Reset to Clock recovery time Dn CP VM VM VM VM ts(H) th(H) ts(L) th(L) VM VM SF00191 Waveform 2. Data setup and hold times 1995 Sep 22 5 Philips Semiconductors Product specification 8-bit serial-in parallel-out shift register 74F164 TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN tw 90% VM D.U.T. RT CL RL AMP (V) VM 10% VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% Test Circuit for Totem-Pole Outputs 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 1995 Sep 22 6 Philips Semiconductors Product specification 8-bit serial-in parallel-out shift register DIP14: plastic dual in-line package; 14 leads (300 mil) 1995 Sep 22 7 74F164 SOT27-1 Philips Semiconductors Product specification 8-bit serial-in parallel-out shift register 74F164 SO14: plastic small outline package; 14 leads; body width 3.9 mm 1995 Sep 22 8 SOT108-1 Philips Semiconductors Product specification 8-bit serial-in parallel-out shift register 74F164 NOTES 1995 Sep 22 9 Philips Semiconductors Product specification 8-bit serial-in parallel-out shift register 74F164 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. 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