SEMTECH UR5HCSPI-06-FB

SPICoderTM 06 UR5HCSPI-06
Zero-PowerTM Keyboard Encoder &
Power Management IC for H/PCs
HID & SYSTEM MANAGEMENT PRODUCTS, H/PC IC FAMILY
DESCRIPTION
The UR5HCSPI-06 keyboard
encoder and power management
IC is designed specifically for
handheld PCs (H/PCs). The off-theshelf UR5HCSPI-06 will readily work
with CPUs designed for Windows
CE®, saving OEMs significant
development time and money as
well as minimizing time-to-market
for the new generations of handheld
products.
Three main design features of the
UR5HCSPI-06 make it the ideal
companion for the new generation
of Windows CE® -compatible,
single-chip computers: low-power
consumption; real estate-saving
size; and special keyboard modes.
FEATURES
• SPI-compatible keyboard encoder
and power management IC with
other interfaces available
• Compatible with Windows CE®
keyboard specification
• Zero-PowerTM — typically
consuming less than 2µA,
between 3-5V
• Offers overall system power
management capabilities
• Compatible with “system-on
silicon” CPUs for H/PCs
• Special keyboard and power
management modes for H/PCs,
including programmable “wakeup” keys
• Scans, debounces, and encodes
an 8 x 14 matrix and controls
discrete switches and LED
indicators
• Available in a small 44-pin QFP
package
• Custom versions available
APPLICATIONS
• Personal Digital Assistants (PDAs)
• Wearable Computers
• Internet Appliance
• StrongARMTM Handheld PCs
• Windows CE® Platforms
• Web Phones
_ATN
_SS
SCK
MOSI
MISO
WUKO
SW0
C8
C9
C10
C11/_LID
C6
C7
Vx
NC
_WKU
_RESET
Vcc
OSCI
OSCO
NC0
NC
PIN ASSIGNMENTS
Finally, special keyboard modes
and built-in power management
features allow the SPICoderTM 06 to
operate in harmony with the power
management modes of Windows
CE®, resulting in more user flexibility
and longer battery life.
PWR_OK
NC0
OSCO
OSCI
Vcc
NC
NC
_RESET
_WKU
Vx
C7
33
34
QFP
1
12
11
C6
C5
C4
C3
C2
C1
C0
R0
R1
R2
R3
44
The UR5HCSPI-06 also offers
programmable features for wake-up
keys and general purpose I/O pins.
6
23
22
NC
C12
C13
GIO0
_IOTEST
Vss
NC
R7
R6
R5
R4
C5
C4
C3
C2
C1
C0
R0
R1
R2
R3
R4
7
12
17
18
1
40
39
PLCC
34
23
SPICoder is a trademark of Semtech Corp. All
other trademarks belong to their respective
companies.
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
1
29
28
NC
R5
R6
R7
Vss
NC
_IOTEST
GIO0
C13
C12
C11/_LID
“Quasi” Zero-PowerTM consumption
(less than 2µA @ 3V), a must for
H/PCs, provides the host system
with both power management and
I/O flexibility, with almost no battery
drainage.
www.semtech.com
_PWR_OK
_ATN
_SS
SCK
MOSI
MISO
XSW
SW0
C8
C9
C10/WUKO
ORDERING CODE
Package Options
44-pin, Plastic PLCC
44-pin, Plastic QFP
Pitch in mm’s
1.27 mm
0.8 mm
TA=-20° C to +85° C
UR5HCSPI-06-XX-FN
UR5HCSPI-06-XX-FB
Note 1: XX=Optional Customization, XXX= Denotes Revision number
BLOCK DIAGRAM
MISO
R0-R8
MOSI
SCK
SS
SPI
Communication
Channel
Keyboard
Scanner
ATN
GIO0
Keyboard
Matrix
&
Keyboard
State
Control
C0-C13
Programmable
I/O
PWR_OK
WKUP
IOTEST
WKU
System
Monitor
Input
Signals
Power
Management
Unit
LID
WUKO
XSW
SWO
LID Latch Monitor
Wake-Up Keys Only Signal
Switch External to Case
Switch
UR5HCSPI-06
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
2
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FUNCTIONAL DESCRIPTION
The UR5HCSPI-06 consists
functionally of five major sections
(see the Functional Diagram on
page 2). These are the Keyboard
Scanner and State control, the
Programmable I/O, the SPI
Communication Channel, the
System Monitor and the Power
Management unit. All sections
communicate with each other and
operate concurrently.
PIN DEFINITIONS
Mnemonic
VCC
VSS
VX
OSCI
OSCO
_RESET
PLCC
44
22
4
43
42
1
QFP
38
17
43
37
36
41
Type
I
I
I
I
O
I
MISO
MOSI
SCK
_SS
_IOTEST
_WKU
R0-R4
34
35
36
37
24
2
13-17
29
30
31
32
18
42
8-12
O
I
I
I
O
I
I
R5-R7
C0-C5
19-21
12-7
13-15
7-2
I
O
C6-C7
C8-C9
6-5
31-30
1,44
26-25
O
O
Name and Function
Power Supply: 3-5V
Ground
Tie to VCC
Oscillator input
Oscillator output
Reset: apply 0V to provide orderly
start-up
SPI Interface Signals
Slave Select: If not used tie to VSS
Wake-Up Control Signals
Row Data Inputs
Port provides internal pull-up resistors
Column Select Outputs:
Multi-function pins
C10
C11/_LID
29
28
24
23
C12
C13
GIO0
WUKO
SWO
27
26
25
33
32
21
20
19
28
27
_ATN
38
33
39
3,18
23,40
41
34
39-40
16,22
35
_PWR_OK
NC
NC0
I/O C10 & “Wake-Up Keys Only” imput
I/O C11 & Lid latch detect input
Miscellaneous functions
I/O C12
I/O C13
I/O Programmable I/O
I
External discrete switch
I
Discrete switch
Power Management Pins
O CPU Attention Output
I
Power OK Input
No Connects: these pins are unused
NC0 should be tied to VSS or GND
Note 1: An underscore before a pin mnemonic denotes an active low signal.
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
3
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PIN DESCRIPTIONS
VCC and VSS
_IOTEST and _WKU
C10/WUKO
VCC and VSS are the power
supply and ground pins. The
UR5HCSPI-06 will operate from a
3-5 Volt power supply. To prevent
noise problems, provide bypass
capacitors and place them as
close as possible to the IC with the
power supply. VX, where available,
should be tied to Vcc.
“Input Output Test” and “Wake Up”
pins control the stop mode exit of
the device. The designer can
connect any number of active low
signals to these two pins through a
17K resistor, in order to force the
device to exit the stop mode. A
sample circuit is shown on page 15
of this document.
OSCI and OSCO
All the signals are “wire-anded.”
When any one of these signals is
not active, it should be floating
(i.e., these signals should be
driven from “open-collector” or
“open-drain” outputs). Other
configurations are possible;
contact Semtech.
The C10/WUKO pin acts
alternatively as column scan output
and as an input. As an input, the
pin detects the “Wake-Up Keys
Only” signal, typically provided by
the host CPU to indicate that the
user has turned the unit off. When
the device detects an active high
state on this pin, it feeds this
information into the “Keyboard
State Control” unit, in order to
disable the keyboard and enable
the programmed wake-up keys.
OSCI and OSCO provide the input
and output connections for the onchip oscillator. The oscillator can
be driven by any of the following
circuits:
- Crystal
- Ceramic Resonator
- External Clock Signal
The frequency of the on-chip
oscillator is 2 MHz.
_RESET
A logic zero on the _RESET pin will
force the UR5HCSPI-06 into a
known start-up state. The reset
signal can be supplied by any of
the following circuits:
- RC
- Voltage monitor
- Master system reset
MOSI, MISO, SCK, _SS, _ATN
R0-R 7
The R0-R7 pins are connected to
the rows of the scanned matrix.
Each pin provides an internal pullup resistor, eliminating the need for
external components.
C0-C9
C11/_LID
The C11/_LID pin acts in a similar
manner to the C10/WUKO. This pin
is typically connected to the LID
latch through a 150K resistor, in
order to detect physical closing of
the device cover. When the pin
detects an active low state in this
input, it feeds this information into
the “Keyboard State Control” unit,
in order to disable keys inside the
case and enable only switches
located physically on the outer
body of the H/PC unit.
C0 to C9 are bi-directional pins
connected to the columns of the
scanned matrix. When a column is
selected, the pin outputs an active
low signal. When the column is
de-selected, the pin turns into
high-impedance.
These five signals implement the
SPI interface. The device acts as a
slave on the SPI bus. The _SS
(Slave Select) pin should be tied to
ground if not used by the SPI
master. The _ATN pin is asserted
low each time the UR5HCSPI-06
has a packet ready for delivery.
For a more detailed description,
refer to the SPI Communication
Channel section on page 9.
Copyright Semtech 1997-2000
DOC5-SPI-06-DS-103
4
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PIN DESCRIPTIONS, (CON’T)
WINDOWS CE® KEYBOARD
C12, C13 and GIO0
The following illustration shows a typical implementation of a Windows CE®
keyboard.
The SPICoderTM 06 offers pins C12,
C13 and GIO0. C12 and C13 are
used as additional column pins in
order to accommodate larger-size
keyboards, such as the Fujitsu
FKB1406 palmtop keyboard. GIO0
is a programmable input/output
switch; it can also be used as a
wake-up signal. The programming
of the GIO0 is explained on page 8
of this document.
Windows CE® does not support the following keyboard keys typically found
on desktop and laptop keyboards:
power
[email protected]
3#
4$
5%
6^
7&
8*
9(
0)
-
~
`
Q
W
E
R
T
Y
U
I
O
P
=+
A
shift
The XSW pin is dedicated to an
external switch. This pin is handled
differently than the rest of the switch
matrix and is intended to be
connected to a switch physically
located on the outside of the unit.
S
Z
F
D
X
C
G
V
alt
ctrl
J
H
B
N
K
M
; :
L
, <
. >
[{
]}
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
' "
/ ?
If the keyboard implements the Windows key, the following key
combinations are supported in the Windows CE® environment:
PWR_OK
The PWR_OK is an active low pin
that monitors the battery status of
the unit. When the UR5HCSPI-06
detects a transition from high to low
on this pin, it will immediately enter
the STOP mode, turn the LED off
and remain in this state until the
batteries of the unit are replaced
and the signal is deasserted.
\ |
INSERT
SCROLL LOCK
PAUSE
NUM LOCK
Function Keys (F1-F12)
PRINT SCREEN
SW0
The SW0 pin is a dedicated input
pin for a switch.
1!
tab
XSW
_
esc
Key Combination
Result
Windows
Windows+K
Windows+I
Windows+C
Windows+E
Windows+R
Windows+H
Ctrl+Windows+A
Open Start Menu
Open Keyboard Tool
Open Stylus Tool
Open Control Panel
Explore the H/PC
Display the Run Dialog Box
Open Windows CE® Help
Select all on desktop
5
www.semtech.com
enter
shift
“GHOST” KEYS
KEYBOARD SCANNER
In any scanned contact switch matrix,
whenever three keys defining a
rectangle on the switch matrix are
pressed at the same time, a fourth
key positioned on the fourth corner of
the rectangle is sensed as being
pressed. This is known as the “ghost”
or “phantom” key problem.
The encoder scans a keyboard organized as an 8 row by 14 column matrix
for a maximum of 112 keys. Smaller size matrixes can also be
accommodated by simply leaving unused pins open. The UR5HCSPI-06
provides internal pull-ups for the Row input pins. When active, the encoder
selects one of the column lines (C0-C13) every 512 µS and then reads the
row data lines (R0-R7). A key closure is detected as a zero in the
corresponding position of the matrix.
Figure 1: “Ghost” or “Phantom” Key Problem
A complete scan cycle for the entire keyboard takes approximately 9.2 mS.
Each key found pressed is debounced for a period of 20 mS. Once the key
is verified, the corresponding key code(s) are loaded into the transmit buffer
of the SPI communication channel.
Actual key presses
N-Key Rollover
“Ghost”
Key
Although the problem cannot be
totally eliminated without using
external hardware, there are methods
to neutralize its negative effects for
most practical applications. Keys that
are intended to be used in
combinations should be placed in the
same row or column of the matrix,
whenever possible. Shift Keys (Shift,
Alt, Ctrl, Window) should not reside in
the same row (or column) as any
other keys. The UR5HCSPI-06 has
built-in mechanisms to detect the
presence of “ghost” keys.
In this mode, the code(s) corresponding to each key press are transmitted
to the host system as soon as that key is debounced, independent of the
release of other keys.
When a key is released, the corresponding break code is transmitted to the
host system. There is no limitation to the number of keys that can be held
pressed at the same time. However, two or more key closures, occurring
within a time interval of less than 5mS, will set an error flag and will not be
processed. This feature is to protect against the effects of accidental key
presses.
Data Command Buffer
The UR5HCSPI-06 implements a data buffer, which contains the key
code/command bytes waiting to be transmitted to the host. If the data
buffer is full, the whole buffer will be cleared and an "Initialize" command will
be sent to the host. At the same time, the keyboard will be disabled until
the "Initialize" or "Initialize Complete" command from the host is received.
Power Management Unit
In most keyboard subsystems, the power consumption is determined by the
use of the LEDs. In these situations, USAR has implemeneted two modes
of operation to minimize power drain. (For more information, see page 10
on the UR5HCSPI datasheet - doc5-spi-ds-100.pdf.) However, since the
SPICoderTM 06 does not provide LED ouput/input, this is not a concern.
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
6
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KEYBOARD STATES
These states of operation refer only
to the keyboard functionality and,
although they are related to power
states, they are also independent of
them.
WUKO=1
AND Key Press
Entry Conditions: Power on reset,
soft reset, PWR_OK =1,
{(LID=1) AND (WUKO=0)}
Description: This is the UR5HCSPI06’s normal state of operation,
accepting and transmitting every
key press to the system. This state
is entered after the power-on and is
sustained while the unit is being
used.
“Send Wake-Up Keys Only”
Entry Conditions: (WUKO=1) AND
(Key or Switch press)
Exit Conditions: Soft Reset -> “Send
All Keys”PWR_OK = 0 -> “Send No
Keys”
Description: This state is entered
when the user turns the unit off. A
signal line driven by the host will
notify the UR5HCSPI-06 about this
state transition. While in this state,
the UR5HCSPI-06 will transmit only
keys programmed to be wake-up
keys to the system. It is not
necessary for the UR5HCSPI-06 to
detect this transition in real time,
since it does not affect any
operation besides buffering
keystrokes.
Copyright Semtech 1997-2000
DOC5-SPI-06-DS-103
Send All
Keys
(LID = 1) AND (WUKO=0)
AND Key Press
"Send All Keys"
Exit Conditions: PWR_OK = 0 ->
"Send No Keys"(WUKO=1) AND
(Key Press) -> "Send Wake-Up
Keys Only"(LID = 0) AND
(WUKO=0) AND (Key Press) ->
"Send XSW Key Only"
(LID = 0) AND (WUK0=0)
AND Key Press
Send
XSW Key
Only
WUKO =1
AND Key
Press
(PWR_OK =1)
AND (LID = 0)
AND (WUKO=0)
AND Key Press
Soft Reset
PWR_OK ↓
Send Wake
Up Keys
Only
PWR_OK ↓
(PWR_OK =1)
AND (WUKO=0)
AND (LID=1)
AND Key Press
PWR_OK = 0
PWR_OK ↓
(PWR_OK =1) AND Key Press
AND (WUKO = 1)
Send
No Keys
Figure 2: The UR5HCSPI-06 implements four modes of keyboard and switch operation.
“Send No Keys"
Entry Conditions: PWR_OK
transition from high to low
Exit Conditions: (PWR_OK = 1)
AND (Matrix key pressed OR
Switch OR _WKUP)
Description: This state is entered
when a PWR_OK signal is asserted
(transition high to low), indicating a
critically low level of battery
voltage. The PWR_OK signal will
cause an interrupt to the
UR5HCSPI-06, which guarantees
that the transition is performed in
real time. While in this state, the
UR5HCSPI-06 will perform as
follows:
1. The UR5HCSPI-06 will enter the
STOP mode for maximum energy
conservation.
2. Stop mode time-out entry will be
shortened to further conserve
energy.
7
3. While in this state all interrupts
are disabled. The UR5HCSPI-06
will exit this state on the next
interrupt event that detects the
PWR_OK line has been deasserted.e
“Send XSW Key Only"
Entry Condition: (LID=0) AND
(WUKO=0) AND (Key Press)
Exit Condition: (LID=1) AND
(WUKO=0) AND (Key Press) ->
“Send All Keys”PWR_OK = 0 ->
“Send No Keys”
(WUKO = 1) AND (Key Press) ->
“Send Wake Up Keys Only”
Description: This state is entered
upon closing the lid of the device.
While in this state, the encoder will
transmit only the XSW key, which is
located outside the unit. This
feature is designed to
accommodate buttons on the
outside of the box, such as a
microphone button, that need to be
used while the lid is closed.
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KEY CODES
GIO0 PIN
Key codes range from 01H to 73H
and are arranged as follows:
Make code = column_number * 8 +
row_number + 1
The UR5HCSPI-06 a general purpose pin that can be programmed as Input,
Output, Debounced or Switch Input. The programmable I/O pin can be
configured to the desired mode through a command from the system. After
the I/O pin is configured, the host system can read or write data to it. If the
pin is configured as a Debounced Switch, it will return scan codes.
Break code = Make code OR 80H
Input Mode
Discrete Switches transmit the
following codes:
While in the Input Mode, the GIO0 pin will detect input signals and report
the input status to the system as required.
XSW = 71H
Output Mode
SW0 = 72H
In the Output Mode, the UR5HCSPI-06 will control the output signal level
according to the system command. When the pin is set at Output Mode,
the default output is low.
GIO0 = 73H
Switch Input Mode
Pin Configurations
When prototyping, caution should
be taken to ensure that
programming of the GIO0 pin does
not conflict with the circuit
implemented. A series protection
resistor is recommended to be used
for protection over improper
programming of the pin.
In Switch Input Mode, the UR5HCSPI-06 will generate an individual make
key code when the switch closes (pin goes low), and a break key code
when the switch returns to open (pin goes to high). The switches generate
key codes outside of those generated by the key matrix, from 71H - 73H.
When the switch closes, the SPICoderTM will not fall asleep.
Input
Output
GIX
GIX
Circuit
determined by
the specific
application
After a power-on or soft reset, GIO0
defaults to the Input state.
Series
protection
resistor
The drawing to the right illustrates
the suggested interface to the
general purpose input/output pin.
Circuit
determined by
the specific
application
Switch
150K
_WKU
LED
GIX
_IOTEST
15K
GIX
Wake-up
interrupt
i
Figure 3: The suggested interface to the general purpose
input/output pin
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
8
www.semtech.com
SPI COMMUNICATION CHANNEL
SPI data transfers can be performed at a maximum clock rate of 500 KHz. When the UR5HCSPI asserts the _ATN
signal to the host Master, the data will have already been loaded into the data register waiting for the clocks from
the master. The Slave Select (SS) line can be tied permanently to Ground if the UR5HCSPI is the only slave device
in the SPI network. One _ATN signal is used per each byte transfer. If the host fails to provide clock signals for
successive bytes in the data packet within 120 mS, the transmission will be aborted and a new session will be
initiated by asserting a new ATN signal. In this case, the whole packet will be re-transmitted.
If the SPI transmission fails 20 times consecutively, the synchronization between the master and slave may be lost.
In this case, the UR5HCSPI will enter the reset state.
The UR5HCSPI implements the SPI communication protocol according to the following diagram:
CPOL = 0 ---------- SCK line idles in low state
CPHA = 1 ---------- SS line is an output enable control
_ATN SIGNAL
SCK (CPOL=0)
_SS
SAMPLE INPUT
DATA OUTPUT
(CPHA=1)
?
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
When the host sends commands to the keyboard, the UR5HCSPI-06 requires that the minimum and maximum
intervals between two successive bytes be 200 µS and 5 mS respectively.
Figure 5: SPI Communication Protocol
Figure 6: Transmitting Data Waveforms:
Figure 7: Receiving Data Waveforms
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
9
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DATA/COMMAND BUFFER
POWER MANAGEMENT UNIT
The UR5HCSPI-06 implements a
data buffer that contains the key
code/command bytes waiting to be
transmitted to the host. If the data
buffer is full, the whole buffer will be
cleared and an "Initialize" command
will be sent to the host. At the
same time, the keyboard will be
disabled until the "Initialize" or
"Initialize Complete" command from
the host is received.
The UR5HCSPI-06 supports two modes of operation. The following table
lists the typical and maximum supply current (no DC loads) for each mode
at 3.3 Volts (+/- 10%).
Current
RUN
Typical
1.5 1
Max
3.0
Unit
mA
STOP
2.0
20
µA
Description
Entered only while data/commands
are in process and if the LEDs
are blinking
Entered after 125 mS of inactivity if
LEDs islow
Power consumption of the keyboard sub-system will be determined
primarily by the use of the LEDs. While the UR5HCSPI-06 is in the STOP
mode, an active low Wake-Up Output from the Master must be connected
to the edge-sensitive _WKU pin of the UR5HCSPI-06. This signal will be
used to wake up the UR5HCSPI-06 in order to receive data from the Master
host. The Master host will have to wait a minimum of 5 mS prior to
providing clocks to the UR5HCSPI-06. The UR5HCSPI-06 will enter the
STOP mode after a 125 mS period of keypad and/or host communications
inactivity, or anytime the PWR_OK line is asserted low by the host. Note
that while one or more keys are held pressed, the UR5HCSPI-06 will not
enter the STOP mode until every key is released.
Figure 6: The Power States of the UR5HCSPI-06
-
Keyboard
Switch
Input transaction
System wake-up
Stop
After Reset
or 125 mS of
inactivity
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
10
Run
While processing
current task
and/or LED(s)
are active
- After 125 mS of
inactivity and LEDs
are off
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LRC CALCULATION, (CON’T)
COMMANDS FROM THE UR5HCSPI-06 TO THE HOST, (CON’T)
The following C language function
is an example of an LRC
calculation program. It accepts two
arguments: a pointer to a buffer
and a buffer length. Its return value
is the LRC value for the specified
buffer.
Resend Request
<CONTROL>
80H
<RESEND>
A5H
<LRC>
25H
The UR5HCSPI-06 will send this Resend Request Command to the host
when its command buffer is full, or if it detects either a parity error or an
unknown command during a system command transmission.
char Calculate LRC (char buffer,
size buffer)
{
char LRC;
size_t index;
/*
* Init the LRC using the first two
message bytes.
*/
LRC = buffer [0] ^ buffer [1];
/*
* Update the LRC using the
remainder of the buffer.
*/
for (index = 2; index < buffer; index
++)
LRC ^ = buffer[index];
/*
* If the MSB is set then clear the
MSB and change the next most
significant bit
*/
if (LRC & 0x80)
LRC ^ = 0xC0;
/* * Return the LRC value for the
buffer.*/}
Input/Output Mode Status Report
<CONTROL>
80H
<MODIO>
A7H
<IO NUMBER>
xxH
IO number, 0
<IO MODE>
xxH
IO mode: (0=input; 1=output;
2=switch; 3=LED )
<LRC>
xxH
The UR5HCSPI-06 will send the I/O Mode Status Report to the host when it
receives the I/O Mode Status Request Command from the host, in order to
report the status of the GIO0 pin.
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
Input/Output Data Report
<CONTROL>
80H
<MODIO>
A8H
<IO NUMBER>
xxH
IO number, 0
<IO DATA>
xxH
IO data: ( 0=low, 1=high )
<LRC>
xxH
The UR5HCSPI-06 will send the I/O Data Report to the host when it receives
the I/O Data Request Command from the host.
11
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COMMANDS FROM THE HOST TO THE UR5HCSPI-06
Commands from the Host - Summary
Command Name
Code
Initialize
AOH
Initialization Complete
A1H
Heartbeat Request
A2H
Identification Request
F2H
Resend Request
A5H
Input/Output Mode Modify
A7H
Output Data to I/O pin
A8H
Set Wake-Up Keys
A9H
Description
Causes the UR5HCSPI-06 to enter the power-on state
Issued as a response to the “Initialize Request”
The UR5HCSPI-06 will respond with “Heartbeat Response”
The UR5HCSPI-06 will respond with “Identification Response”
Issued upon error during the reception of a packet
The UR5HCSPI-06 will modify or report the status of the GIO0 pin
The UR5HCSPI-06 will output a signal to the GIO0 pin
Defines which keys are “wake-up” keys
Each command to UR5HCSPI-06 is composed of a sequence of codes. All commands start with <ESC> code
(1BH) and end with the LRC code (bitwise exclusive OR of all bytes).
COMMANDS FROM THE HOST TO THE UR5HCSPI-06 ANALYTICALLY
Initialize
<ESC>
1BH
<INIT>
A0H
<LRC>
7BH
When the UR5HCSPI-06 receives this command, it will clear all buffers and return to the power-on state.
Initialization Complete
<ESC>
1BH
<INIT COMPLETE>
A1H
<LRC>
7AH
When the UR5HCSPI-06 receives this command, it will enable transmission of keyboard data. Keyboard data
transmission is disabled if the TX output buffer is full (32 bytes). Note that if the transmit data buffer gets full the
encoder will issue an "Initialize Request" to the host.
Heartbeat Request
<ESC>
1BH
<ONLINE>
A2H
<LRC>
79H
When the UR5HCSPI-06 receives this command, it will reply with the Heartbeat Response Report.
Identification Request
<ESC>
<ID>
<LRC>
The UR5HCSPI-06 will reply to
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
1BH
F2H
29H
this command with the Identification Response Report.
12
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COMMANDS FROM THE HOST TO THE UR5HCSPI-06, (CON’T)
Set Wake-Up Keys
<ESC>
1BH
<SETMATRIX>
A9H
<COL0>
xxH
(R7
R6 R5 R4 R3 R2 R1 R0 Bitmap: 0enabled, 1-disabled)
<COL1>
xxH
<COL2>
xxH
<COL3>
xxH
<COL4>
xxH
<COL5>
xxH
<COL6>
xxH
<COL7>
xxH
<COL8>
xxH
<COL9>
xxH
<COL10>
xxH
<COL11>
xxH
<COL12>*
xxH
(*UR5HCSPI-06-06-XX only)
<COL13>*
xxH
(*UR5HCSPI-06-06-XX only)
<SWITCHES>
xxH
(where SWITCHES bit assignments
are = x x x x x GIO0 SW0 XSW)
<LRC>
xxH
I/O Mode Modify
<ESC>
1BH
<MODIO>
A7H
<IO NUMBER>
xxH
IO number: 0
<IO MODE>
xxH
IO mode: ( 0=input, 1=output,
2=switch, 3=LED, 4=current mode state
request)
<LRC>
xxH
When UR5HCSPI-06 receives this command, it will change the I/O pin's
mode accordingly. If the <IO MODE> =4, the UR5HCSPI-06 will send the
I/O Mode Status Report to the host.
Output Data to I/O Pin:
<ESC>
1BH
<MODIO>
A8H
<IO NUMBER>
xxH
IO number: 0
<IO DATA>
xxH
IO data: ( 0=low, 1=high, 2=current
I/O data request)
<LRC>
xxH
When UR5HCSPI-06 receives this command, it will change the value of the
output pin accordingly. If the addressed pin is not configured as an output
pin, the command will be ignored. If <IO DATA> =2, the UR5HCSPI-06 will
respond by issuing the I/O Data Status Report to the host.
The "Set Wake-Up Keys" command
is used to disable specific keys
from waking up the host. Using this
command, the host can set only a
group of keys. For this IC, data in
bytes <COL12> and <COL 13> is
not relevant, but these two bytes
must be present in the packet in
order to preserve the packet
structure.
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
13
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KEY MAP FOR THE FUJITSU FKB1406
0
1
LAlt
`
0
2
\
Columns (C0–C13)
6
7
8
3
4
5
LCtrl
FN
Esc
LSft
1
F1
2
F2
T
Del
9
F9
Y
9
10
11
12
0
F10
U
Pad 4
NmLk
I
Pad 5
+
Bk
Enter
13
BkSp
RShift
PgDn
Rows (R0–R6)
1
TAB
Q
W
Z
CapLk
E
R
O
Pad 6
P
Ins
[
Pause
]
ScrLk
K
Pad 2
L
Pad 3
;
PrtScr
‘
SysReq
PgUp
G
H
J
Pad 1
/
/
Home
Spc
2
3
A
S
D
F
4
X
C
V
B
N
Pad 0
M
,
.
3
F3
4
F4
5
F5
6
F6
7
F7
8
F8
Prog
5
6
End
KEYBOARD LAYOUT FOR FUJITSU FKB1406
Esc
@
#
$
%
^
&
1 F2
2 F2
3 F3
4 F4
5 F5
6 F6
7 F7
Q
Del
7
!
Cap
Lock
Fn
Shift
Ctrl
Alt
W
A
E
S
D
Z
X
~
`
:
;
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
R
T
F
C
V
Y
G
B
*
8
8 F8
U4
H
N
J
9
(
9 F9
I
1
M0
)
0 F10
O6
5
_
+
- Num = Bk
Lk
*
P
Ins
K2 L3
<
,
..
>
:
;
{
}
[ Pause
] Scr
Lk
_
+
"
Prt
Scr
'
?
/
/
Sys
Req
Enter
Shift
Home PgUp PgDn
14
www.semtech.com
Prog
End
_WKUP
PWR_OK
_ATN
SCK
MOSI
15K
Wake Up
Signal
150K
NC0
VSS
PWR_OK
ATN
SS
SCK
MOSI
1MOhm
UR5HCSPI-06-FB
Ceramic resonator circuit
with built in capacitors,
like AVX PBRC-2.00BR
35
17
34
Vin
Alternatively a 2MHz CMOS
signal can be tied directly
to OSC1
Power OK Signal
Attention Signal 33
Tied to Gnd
if not used
Slave Select 32
31
30
Vout
41
GND
MISO
2MHz
R7
R6
R5
R4
R3
R2
R1
R0
XSW
SW0
GIO0
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10/WUKO
C11/LID
COL12
COL13
36
29
OSCO
MISO
OSCI
37
TC54C4302ECB
IOTEST
18
Alternatively an RC circuit
or Master Reset Signal
can be used
Power OK
Signal
43
38
Vpp
VDD
WKU
15
42
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
RESET
VCC
28
27
19
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1.5M
1.5M
©2000, USAR, A Semtech Company
15K
15K
Tie to Vcc or GND if
not used
7
6
5
4
3
2
1
44
26
25
24
23
21
20.
15
14
13
12
11
10
9
8
DISCRETE
SWITCHES
COLUMN
OUTPUTS
WUKO
_LID
TO SWITCH
MATRIX
ROW
INPUTS
SAMPLE CONFIGURATION UR5HCSPI-06-FB
IMPLEMENTATION NOTES FOR THE UR5HCSPI-06
The following notes pertain to the suggested schematic found on the
previous page.
The Built-in Oscillator on the UR5HCSPI-06 requires the attachment of the
2.00 MHz Ceramic Resonators with built-in Load Capacitors.. You can use
either an AVX, part number PBRC-2.00 BR; or a Murata part number
CSTCC2.00MG ceramic resonator.
It may also be possible to operate with the 2.00 MHz Crystal, albeit with
reduced performance. Due to their high Q, the Crystal oscillator circuits
start-up slowly. Since the SPICoderTM constantly switches the clock on and
off, it is important that the Ceramic Resonator is used (it starts up much
quicker than the Crystal). Resonators are also less expensive than Crystals.
Also, if Crystal is attached, two Load Capacitors (33pF to 47pF) should be
added, a Capacitor between each side of the Crystal and ground.
In both cases, using Ceramic Resonator with built-in Load Capacitors, or
Crystal with external Load Capacitors, a feedback Resistor of 1 Meg should
be connected between OSCIN and OSCOUT.
Troubleshoot the circuit by looking at the Output pin of the Oscillator. If the
voltage is half-way between Supply and Ground (while the Oscillator should
be running) --- the problem is with the Load Caps / Crystal. If the voltage is
all the way at Supply or Ground (while the Oscillator should be running) --there are shorts on the PCB.
Note: When the Oscillator is intentionally turned OFF, the voltage on the
Output pin of the Oscillator is High (at the Supply rail).
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
16
www.semtech.com
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Ratings
Supply Voltage
Input Voltage
Current Drain per Pin
(not including Vss or Vdd)
Operating Temperature
UR5HCSPI-06
Storage Temperature Range
Thermal Characteristics
Characteristic
Thermal Resistance
Plastic
PLCC
Symbol
Vdd
Vin
I
Value
-0.3 to +7.0
Vss -0.3 to Vdd +0.3
25
Unit
V
V
mA
Ta
T low to T high
-40 to +85
-65 to +150
°C
Value
Unit
°C per W
Tstg -
Symbol
Tja
°C
60
70
DC Electrical Characteristics (Vdd=3.3 Vdc +/-10%, Vss=0 Vdc, Temperature range=T low to T high unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage (I load<10µA)
Vol
0.1
V
Voh
Vdd–0.1
Output High Voltage (I load=0.8mA)
Voh
Vdd–0.8
V
Output Low Voltage (I load=1.6mA)
Vol:
0.4
V
Input High Voltage
Vih
0.7xVdd
Vdd
V
Input Low Voltage
Vil
Vss
0.2xVdd
V
User Mode Current
Ipp
5
10
mA
Data Retention Mode (0 to 70°C)
Vrm
2.0
V
Supply Current (Run)
Idd
1.53
3.0
mA
(Wait)
0.711
1.0
mA
(Stop)
2.0
20
µA
I/O Ports Hi-Z Leakage Current
Iil
+/-10
µA
Input Current
Iin
+/- 1
µA
I/O Port Capacitance
Cio
8
12
pF
Control Timing (Vdd=3.3 Vdc +/-10%, Vss=0 Vdc, Temperature range=T low to T high unless otherwise noted)
Characteristic
Symbol
Min
Max
Frequency of Operation
fosc
Crystal Option
2.0
External Clock Option
dc
2.0
Cycle Time
tcyc
1000
Crystal Oscillator Startup Time
toxov
100
Stop Recovery Startup Time
tilch
100
RESET Pulse Width
trl
8
Interrupt Pulse Width Low
tlih
250
Interrupt Pulse Period
tilil
*
OSC1 Pulse Width
toh, tol
200
Unit
MHz
ns
ms
ms
tcyc
ns
tcyc
ns
*The minimum period tlil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tcyc.
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
17
www.semtech.com
SPICODERTM BILL OF MATERIALS
UR5HCSPI-06-FB
Quantity
3
1
1
2
1
1
Generic
Generic
Generic
Generic
TELCOM
AVX
Manufacture
Part#
15K
150K
1M
1.5K
TC54VC4302ECB713
TC54VC2702ECB713
PBRC-2.00BR
Description
15K Resistor
150K Resistor
1M Resistor
1.5 Resistors
IC Volt Detector CMOS 4.3V SOT23, for 5V Operation
IC Volt Detector CMOS 2.7V SOT23, for 3.3V Operation
2.00MHZCeramic Resonator with Built in Capacitors, SMT
Revised 7/14/99
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
18
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This Page Left Intentionally Blank
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
19
www.semtech.com
For sales information
and product literature,
contact:
HID & System Mgmt Division
Semtech Corporation
568 Broadway
New York, NY 10012
[email protected]
http://www.semtech.com
212 226 2042 Telephone
212 226 3215 Telefax
Semtech Western Regional Sales
805-498-2111 Telephone
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Copyright 2000-2001 Semtech Corporation. All rights reserved.
Zero-Power, SPICoder and Self-Power Management are trademarks
of Semtech Corporation. Semtech is a registered trademark of
Semtech Company. All other trademarks belong to their respective
companies.
INTELLECTUAL PROPERTY DISCLAIMER
This specification is provided "as is" with no warranties whatsoever
including any warranty of merchantability, fitness for any particular
purpose, or any warranty otherwise arising out of any proposal,
specification or sample. A license is hereby granted to reproduce
and distribute this specification for internal use only. No other
license, expressed or implied to any other intellectual property
rights is granted or intended hereby. Authors of this specification
disclaim any liability, including liability for infringement of proprietary
rights, relating to the implementation of information in this
specification. Authors of this specification also do not warrant or
represent that such implementation(s) will not infringe such rights.
Copyright Semtech 1997-2001
DOC5-SPI-06-DS-103
20
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