74VCXH16374 LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE) WITH 3.6V TOLERANT INPUTS AND OUTPUTS ■ ■ ■ ■ ■ ■ ■ ■ ■ 3.6V TOLERANT INPUTS AND OUTPUTS HIGH SPEED : tPD = 3.0 ns (MAX.) at VCC = 3.0 to 3.6V tPD = 3.9 ns (MAX.) at VCC = 2.3 to 2.7V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3.0V |IOH| = IOL = 18mA (MIN) at VCC = 2.3V OPERATING VOLTAGE RANGE: VCC(OPR) = 2.3V to 3.6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES H16374 BUS HOLD PROVIDED ON DATA INPUTS LATCH-UP PERFORMANCE EXCEEDS 300mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V TSSOP ORDER CODES PACKAGE TSSOP TUBE T&R 74VCXH16374TTR PIN CONNECTION DESCRIPTION The 74VCXH16374 is a low voltage CMOS 16 BIT D-TYPE FLIP-FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and five-layer metal wiring C2MOS technology. It is ideal for low power and very high speed 2.3 to 3.6V applications; it can be interfaced to 3.6V signal environment for both inputs and outputs. These 16 bit D-TYPE flip-flops are controlled by two clock inputs (nCK) and two output enable inputs (nOE). On the positive transition of the (nCK), the nQ outputs will be set to the logic state that were setup at the nD inputs. While the (nOE) input is low, the 8 outputs (nQ) will be in a normal state (HIGH or LOW logic level) and while high level the outputs will be in a high impedance state. Any output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Bus hold on data inputs is provided in order to eliminate the need for external pull-up or pull-down resistor. February 2003 1/12 74VCXH16374 All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT IEC LOGIC SYMBOLS PIN DESCRIPTION PIN No SYMBOL 1 1OE NAME AND FUNCTION 3 State Output Enable Input (Active LOW) 2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs 11, 12 13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs 19, 20, 22, 23 3 State Output Enable 24 2OE Input (Active LOW) 25 2CK Clock Input 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1CK Clock Input 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 VCC Positive Supply Voltage TRUTH TABLE INPUTS OE CK D H X Q X Z L X NO CHANGE* L L L L H H X : Don‘t Care Z : High Impedance 2/12 OUTPUT 74VCXH16374 LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Supply Voltage -0.5 to +4.6 V VI DC Input Voltage -0.5 to +4.6 V VO DC Output Voltage (OFF State) VO DC Output Voltage (High or Low State) (note 1) IIK DC Input Diode Current IOK DC Output Diode Current (note 2) IO DC Output Current VCC Parameter ICC or IGND DC VCC or Ground Current per Supply Pin PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) -0.5 to +4.6 V -0.5 to VCC + 0.5 - 50 V mA - 50 mA ± 50 mA ± 100 mA 400 mW -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND, VO > VCC RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Value Unit V Supply Voltage 2.3 to 3.6 VI Input Voltage -0.3 to 3.6 V VO Output Voltage (OFF State) 0 to 3.6 V VO Output Voltage (High or Low State) 0 to VCC V ± 24 mA IOH, IOL High or Low Level Output Current (VCC = 3.0 to 3.6V) IOH, IOL High or Low Level Output Current (VCC = 2.3 to 2.7V) Top dt/dv Operating Temperature Input Rise and Fall Time (note 1) ± 18 mA -55 to 125 °C 0 to 10 ns/V 1) VIN from 0.8V to 2V at VCC = 3.0V 3/12 74VCXH16374 DC SPECIFICATIONS (2.7V < VCC < 3.6V unless otherwise specified) Test Condition Symbol VIH VIL VOH Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage II(HOLD) Ioff IOZ ICC ∆ICC 4/12 Input Leakage Current Input Hold Current Min. Max. 2.0 -55 to 125 °C Min. 2.0 V 0.8 0.8 2.7 to 3.6 IO=-100 µA VCC-0.2 VCC-0.2 2.7 IO=-12 mA 2.2 2.2 IO=-18 mA 2.4 2.4 IO=-24 mA 2.2 2.2 V 2.7 to 3.6 IO=100 µA 0.2 0.2 2.7 IO=12 mA 0.4 0.4 IO=18 mA 0.4 0.4 IO=24 mA 0.55 0.55 VI = 0 to 3.6V ±5 ±5 2.7 to 3.6 3.0 Unit Max. 2.7 to 3.6 3.0 II -40 to 85 °C VCC (V) 3.0 VOL Value VI = 0.8V 75 75 VI = 2V -75 -75 V µA µA 3.6 VI = 0 to 3.6V ± 500 ± 500 0 VI or VO = 0 to 3.6V 10 10 µA 2.7 to 3.6 VI = VIH or VIL VO = 0 to 3.6V ± 10 ± 10 µA VI = VCC or GND 20 20 VI or VO = VCC to 3.6V VIH = VCC - 0.6V ± 20 ± 20 750 750 Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ICC incr. per Input 2.7 to 3.6 2.7 to 3.6 µA µA 74VCXH16374 DC SPECIFICATIONS (2.3V < VCC < 2.7V unless otherwise specified) Test Condition Symbol VIH VIL VOH Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage II(HOLD) Ioff IOZ ICC Input Leakage Current Input Hold Current Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Min. Max. 1.6 -55 to 125 °C Min. 1.6 V 0.7 2.3 to 2.7 2.3 to 2.7 2.3 to 2.7 2.3 Unit Max. 2.3 to 2.7 2.3 II -40 to 85 °C VCC (V) 2.3 VOL Value 0.7 IO=-100 µA VCC-0.2 VCC-0.2 IO=-6 mA 2.0 2.0 IO=-12 mA 1.8 1.8 IO=-18 mA 1.7 1.7 V IO=100 µA 0.2 0.2 IO=12 mA 0.4 0.4 IO=18 mA 0.6 0.6 VI = 0 to 3.6V ±5 ±5 VI = 0.7V 45 45 VI = 1.7V -45 -45 V µA µA 0 VI or VO = 0 to 3.6V 10 10 µA 2.3 to 2.7 VI = VIH or VIL VO = 0 to 3.6V ± 10 ± 10 µA VI = VCC or GND 20 20 VI or VO = VCC to 3.6V ± 20 ± 20 2.3 to 2.7 µA DYNAMIC SWITCHING CHARACTERISTICS (Ta = 25°C, Input tr = tf = 2.0ns, CL = 30pF, RL = 500Ω) Test Condition Symbol Parameter VOLP Dynamic Low Voltage Quiet Output (note 1, 3) VOLV Dynamic Low Voltage Quiet Output (note 1, 3) VOHV Dynamic High Voltage Quiet Output (note 2, 3) TA = 25 °C VCC (V) 2.5 3.3 2.5 3.3 2.5 3.3 Value Min. VIL = 0V VIH = VCC VIL = 0V VIH = VCC VIL = 0V VIH = VCC Typ. 0.6 0.8 -0.6 -0.8 1.9 2.2 Unit Max. V V V 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. 2) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the HIGH state. 3) Parameters guaranteed by design. 5/12 74VCXH16374 AC ELECTRICAL CHARACTERISTICS (CL = 30pF, RL = 500Ω, Input tr = tf = 2.0ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time CK to Qn tPZL tPZH Output Enable Time tPLZ tPHZ Output Disable Time ts Setup TIme, HIGH or LOW level Dn to CK th Hold Time High or LOW level Dn to CK tw CK Pulse Width, HIGH fMAX Clock Pulse Frequency tOSLH tOSHL Output To Output Skew Time (note1, 2) Value -40 to 85 °C VCC (V) 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 2.3 to 2.7 3.0 to 3.6 -55 to 125 °C Min. Max. Min. Max. 1.0 0.8 1.0 0.8 1.0 0.8 1.5 1.5 1.0 1.0 1.5 1.5 200 250 3.9 3.0 4.6 3.5 3.8 3.5 1.0 0.8 1.0 0.8 1.0 0.8 1.5 1.5 1.0 1.0 1.5 1.5 180 235 4.7 3.5 5.1 4.3 4.6 4.3 0.5 0.5 Unit ns ns ns ns ns ns MHz 0.5 0.5 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|) 2) Parameter guaranteed by design CAPACITIVE CHARACTERISTICS Test Condition Symbol CIN Parameter Value TA = 25 °C VCC (V) Min. Typ. Unit Max. Input Capacitance 2.5 or 3.3 VIN = 0 or VCC 6 pF COUT Output Capacitance 2.5 or 3.3 VIN = 0 or VCC 7 pF CPD Power Dissipation Capacitance (note 1) 2.5 or 3.3 fIN = 10MHz VIN = 0 or VCC 20 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per circuit) 6/12 74VCXH16374 TEST CIRCUIT TEST SWITCH tPLH, tPHL Open tPZL, tPLZ (VCC = 3.0 to 3.6V) 6V tPZL, tPLZ (VCC = 2.3 to 2.7V) tPZH, tPHZ 2VCC GND CL = 30 pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM SYMBOL VALUES VCC Symbol VIH 3.0 to3.6V 2.3 to 2.7V 2.7V VCC VM 1.5V VCC/2 VX VOL + 0.3V VOL + 0.15V VY VOH - 0.3V VOH - 0.15V 7/12 74VCXH16374 WAVEFORM 1 : nCK TO Qn PROPAGATION DELAYS, nCK MAXIMUM FREQUENCY, Dn TO nCK SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 8/12 74VCXH16374 WAVEFORM 3 : nCK MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle) 9/12 74VCXH16374 TSSOP48 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. 1.2 A1 0.05 0.047 0.15 A2 MAX. 0.002 0.006 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 D 12.4 12.6 0.488 0.496 E 8.1 BSC E1 6.0 0.318 BSC 6.2 e 0.236 0.5 BSC 0.244 0.0197 BSC K 0˚ 8˚ 0˚ 8˚ L 0.50 0.75 0.020 0.030 A A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 7065588C 10/12 74VCXH16374 Tape & Reel TSSOP48 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 30.4 0.519 1.197 Ao 8.7 8.9 0.343 0.350 Bo 13.1 13.3 0.516 0.524 Ko 1.5 1.7 0.059 0.067 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 11/12 74VCXH16374 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 12/12