74VHC139 DUAL 2 TO 4 DECODER/DEMULTIPLEXER ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD =5.0 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 139 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74VHC139 is an advanced high-speed CMOS DUAL 2 TO 4 LINE DECODER/ DEMULTIPLEXER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The active low enable input can be used for M1 (Micro Package) T (TSSOP Package) ORDER CODES : 74VHC139M 74VHC139T gating or as a data input for demultiplexing applications. While the enable input is held high, all four outputs are high independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS June 1999 1/8 74VHC139 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 15 1G, 2G Enable Inputs 1A, 1B Address Inputs 2, 3 NAME AND FUNCT ION 4, 5, 6, 7 1Y0 to 1Y3 Outputs 12, 11, 10, 9 2Y0 to 2Y3 Outputs 14, 13 2A, 2B 8 GND Ground (0V) Address Inputs 16 VCC Positive Supply Voltage TRUTH TABLE ENABLE G H L L L L INPUT S SELECT B X L L H H OUTPUTS A X L H L H X:Don’t Care LOGIC DIAGRAM Thislogic diagram has notbe used to estimate propagation delays 2/8 Y0 H L H H H Y1 H H L H H Y2 H H H L H Y3 H H H H L 74VHC139 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Unit -0.5 to +7.0 V -0.5 to +7.0 V -0.5 to VCC + 0.5 V Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 75 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Valu e Unit 2.0 to 5.5 V V VI Input Voltage 0 to 5.5 VO Output Voltage 0 to VCC Top dt/dv Operating Temperature V o -40 to +85 Input Rise and Fall Time (see note 1) (VCC = 3.3 ± 0.3V) (V CC = 5.0 ± 0.5V) C 0 to 100 0 to 20 ns/V ns/V 1) VIN from 30% to70%of VCC DC SPECIFICATIONS Symb ol VIH VIL VOH VOL II ICC Parameter T est Cond ition s Value o Min. Typ . Un it o T A = 25 C V CC (V) -40 to 85 C Max. Min . Max. High Level Input Voltage 2.0 1.5 1.5 3.0 to 5.5 0.7VCC 0.7VCC Low Level Input Voltage 2.0 0.5 0.5 3.0 to 5.5 0.3VCC 0.3VCC High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current V 2.0 IO=-50 µA 1.9 2.0 1.9 3.0 IO=-50 µA 2.9 3.0 2.9 4.5 IO=-50 µA 4.4 4.5 4.4 3.0 IO=-4 mA 2.58 4.5 IO=-8 mA 3.94 2.0 IO=50 µA 0.0 0.1 0.1 3.0 IO=50 µA 0.0 0.1 0.1 4.5 0.0 0.1 0.1 0.36 0.44 V V 2.48 3.8 V 3.0 IO=50 µA IO=4 mA 4.5 IO=8 mA 0.36 0.44 0 to 5.5 VI = 5.5V or GND ±0.1 ±1.0 µA 5.5 VI = VCC or GND 4 40 µA 3/8 74VHC139 AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns) Symb ol Parameter 3.3(*) 15 Value T A = 25 o C Min. Typ . Max. 7.2 11.0 3.3(*) 5.0(**) 5.0(**) 3.3(*) 3.3(*) 50 15 50 15 50 9.7 5.0 6.5 6.4 8.9 14.5 7.2 9.2 9.2 12.7 1.0 1.0 1.0 1.0 1.0 16.5 8.5 10.5 11.0 14.5 (**) 15 50 4.4 5.9 6.3 8.3 1.0 1.0 7.5 9.5 V CC (V) tPLH tPHL Propagation Delay Time A, B, to Y tPLH tPHL Propagation Delay Time G to Y Test Co ndition CL (pF ) 5.0 5.0(**) Un it -40 to 85 o C Min . Max. 1.0 13.0 ns ns (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5V ± 0.5V CAPACITIVE CHARACTERISTICS Symb ol Parameter T est Cond ition s Value o Min. Un it o T A = 25 C -40 to 85 C Typ . Max. C IN Input Capacitance 4 10 CPD Power Dissipation Capacitance (note 1) 26 Min . Max. 10 pF pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/2 (per Decoder) TEST CIRCUIT CL = 15/50 pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) 4/8 74VHC139 WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle) WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty cycle) 5/8 74VHC139 SO-16 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.004 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8 (max.) P013H 6/8 74VHC139 TSSOP16 MECHANICAL DATA mm DIM. MIN. inch TYP. A MAX. MIN. TYP. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 7/8 74VHC139 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com . 8/8