ST93C56, 56C ST93C57C 2K (128 x 16 or 256 x 8) SERIAL MICROWIRE EEPROM NOT FOR NEW DESIGN 1 MILLION ERASE/WRITE CYCLES, with 40 YEARS DATA RETENTION DUAL ORGANIZATION: 128 x 16 or 256 x 8 BYTE/WORD and ENTIRE MEMORY PROGRAMMING INSTRUCTIONS SELF-TIMED PROGRAMMING CYCLE with AUTO-ERASE READY/BUSY SIGNAL DURING PROGRAMMING SINGLE SUPPLY VOLTAGE: – 4.5V to 5.5V for ST93C56 version – 3V to 5.5V for ST93C57 version SEQUENTIAL READ OPERATION 5ms TYPICAL PROGRAMMING TIME ST93C56, ST93C56C, ST93C57C are replaced by the M93C56 PSDIP8 (B) 0.4mm Frame D Serial Data Input Q Serial Data Output C Serial Clock ORG Organisation Select VCC Supply Voltage VSS Ground SO8 (M) 150mil Width Figure 1. Logic Diagram Table 1. Signal Names Chip Select Input 1 1 DESCRIPTION This specification covers a range of 2K bit serial EEPROM products, the ST93C56, 56C specified at 5V ± 10% and the ST93C57C specified at 3V to 5.5V. In the text, products are referred to as ST93C56. The ST93C56 is a 2K bit Electrically Erasable Programmable Memory (EEPROM) fabricated with SGS-THOMSON’s High EnduranceSingle Polysilicon CMOS technology. The memory is accessed through a serial input (D) and output (Q). The 2K bit memory is divided into either 256 x 8 bit bytes or 128 x 16 bit words. The organization may be selected by a signal applied on the ORG input. S 8 8 VCC D C S Q ST93C56 ST93C57 ORG VSS AI00881C June 1997 This is information on a product still in production bu t not recommended for new de signs. 1/13 ST93C56/56C, ST93C57C Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections ST93C56 ST93C57 S C D Q 1 2 3 4 8 7 6 5 ST93C56 ST93C57 VCC DU ORG VSS S C D Q 1 2 3 4 AI00882C 8 7 6 5 VCC DU ORG VSS AI00883D Warning: DU = Don’t Use Warning: DU = Don’t Use Table 2. Absolute Maximum Ratings (1) Symbol Parameter Value Unit Ambient Operating Temperature –40 to 125 °C TSTG Storage Temperature –65 to 150 °C TLEAD Lead Temperature, Soldering 215 260 °C TA (SO8 package) (PSDIP8 package) VIO Input or Output Voltages (Q = VOH or Hi-Z) VCC Supply Voltage VESD Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model) (3) (2) 40 sec 10 sec –0.3 to VCC +0.5 V –0.3 to 6.5 V 4000 V 500 V Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω). 3. EIAJ IC-121 (Condition C) (200pF, 0 Ω). DESCRIPTION (cont’d) The memory is accessed by a set of instructions which includes Read a byte/word, Write a byte/word, Erase a byte/word, Erase All and Write All. A Read instruction loads the address of the first byte/word to be read into an internal address pointer. The data contained at this address is then clocked out serially. The address pointer is automatically incremented after the data is output and, if the Chip Select input (S) is held High, the ST93C56 can output a sequential stream of data bytes/words. In this way, the memory can be read as a data stream from 8 to 2048 bits long, or continuously as the address counter automatically rolls over to ’00’ when the highest address is reached. Programming is internally self-timed (the external clock signal on C input may be discon2/13 nected or left running after the start of a Write cycle) and does not require an erase cycle prior to the Write instruction. The Write instruction writes 8 or 16 bits at one time into one of the 256 bytes or 128 words. After the start of the programming cycle, a Busy/Ready signal is available on the Data output (Q) when Chip Select (S) is driven High. The design of the ST93C56 and the High Endurance CMOS technologyused for its fabrication give an Erase/Write cycle Endurance of 1,000,000 cycles and a data retention of 40 years. The DU (Don’t Use) pin does not affect the function of the memory and it is reserved for use by SGSTHOMSON during test sequences.The pin may be left unconnected or may be connected to VCC or VSS. Direct connection of DU to VSS is recommended for the lowest standby power consumption. ST93C56/56C, ST93C57C AC MEASUREMENT CONDITIONS Input Rise and Fall Times ≤ 20ns Input Pulse Voltages 0.4V to 2.4V Input Timing Reference Voltages 1V to 2.0V Output Timing Reference Voltages 0.8V to 2.0V Figure 3. AC Testing Input Output Waveforms 2.4V 2V 2.0V 1V 0.8V 0.4V Note that Output Hi-Z is defined as the point where data is no longer driven. INPUT OUTPUT AI00815 Table 3. Capacitance (1) (TA = 25 °C, f = 1 MHz ) Symbol C IN COUT Parameter Input Capacitance Output Capacitance Test Condition Min Max Unit VIN = 0V 5 pF VOUT = 0V 5 pF Max Unit 0V ≤ VIN ≤ VCC ±2.5 µA Note: 1. Sampled only, not 100% tested. Table 4. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V or 3V to 5.5V) Symbol Parameter Test Condition Min ILI Input Leakage Current ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA Supply Current (TTL Inputs) S = VIH, f = 1 MHz 3 mA Supply Current (CMOS Inputs) S = VIH, f = 1 MHz 2 mA ICC1 Supply Current (Standby) S = VSS, C = VSS, ORG = VSS or VCC 50 µA VIL Input Low Voltage (D, C, S) ICC VIH VOL VOH Input High Voltage (D, C, S) Output Low Voltage Output High Voltage VCC = 5V ± 10% –0.3 0.8 V 3V ≤ VCC ≤ 4.5V –0.3 0.2 VCC V VCC = 5V ± 10% 2 VCC + 1 V 3V ≤ VCC ≤ 4.5V 0.8 VCC VCC + 1 V IOL = 2.1mA 0.4 V IOL = 10 µA 0.2 V IOH = –400µA 2.4 V IOH = –10µA VCC – 0.2 V 3/13 ST93C56/56C, ST93C57C Table 5. AC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V or 3V to 5.5V) Symbol Alt Parameter Test Condition Min Max Unit tSHCH tCSS Chip Select High to Clock High 50 ns tCLSH tSKS Clock Low to Chip Select High 100 ns tDVCH tDIS Input Valid to Clock High 100 ns Temp. Range: grade 1 100 ns tCHDX tDIH Clock High to Input Transition Temp. Range: grades 3, 6 200 ns tCHQL tPD0 Clock High to Output Low 500 ns tCHQV tPD1 Clock High to Output Valid 500 ns tCLSL tCSH Clock Low to Chip Select Low 0 ns Chip Select Low to Clock High 250 ns 250 ns tSLCH tSLSH tCS Chip Select Low to Chip Select High tSHQV tSV Chip Select High to Output Valid tSLQZ tDF Chip Select Low to Output Hi-Z Note 1 500 ns ST93C56 300 ns ST93C56C, 57C 200 ns tCHCL tSKH Clock High to Clock Low Note 2 250 ns tCLCH tSKL Clock Low to Clock High Note 2 250 ns tW tWP Erase/Write Cycle time fC fSK Clock Frequency 10 ms 1 MHz 0 Notes: 1. Chip Select must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles. 2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings tCHCL + tCLCH must be greater or equal to 1 µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns. Figure 4. Synchronous Timing, Start and Op-Code Input tCLSH tCHCL C tSHCH tCLCH S tDVCH D START START tCHDX OP CODE OP CODE OP CODE INPUT AI01428 4/13 ST93C56/56C, ST93C57C Figure 5. Synchronous Timing, Read or Write C tCLSL S tDVCH tCHDX tSLSH A0 An D tCHQV tSLQZ tCHQL Hi-Z Q15/Q7 Q ADDRESS INPUT Q0 DATA OUTPUT AI00820C tSLCH C tCLSL S tDVCH D An tCHDX tSLSH A0/D0 tSHQV tSLQZ Hi-Z Q BUSY READY tW ADDRESS/DATA INPUT WRITE CYCLE AI01429 MEMORY ORGANIZATION The ST93C56 is organized as 256 bytes x 8 bits or 128 words x 16 bits. If the ORG input is left unconnected (or connected to VCC) the x16 organization is selected, when ORG is connected to Ground (VSS) the x8 organization is selected. When the ST93C56 is in standby mode, the ORG input should be unconnected or set to either VSS or VCC in order to achieve the minimum power consumption. Any voltage between VSS and VCC applied to ORG may increase the standby current value. POWER-ON DATA PROTECTION In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit resets all internal programming circuitry and sets the device in the Write Disable mode. When VCC reaches its functional value, the device is properly reset (in the Write Disable mode) and is ready to decode and execute an incoming instruction. A stable VCC must be applied, before applying any logic signal. 5/13 ST93C56/56C, ST93C57C be executed, the Erase/Write Disable instruction (EWDS) disables the execution of the following Erase/Write instructions. When power is first applied, the ST93C56 enters the Disable mode. When the EWEN instruction is executed, Write instructions remain enabled until an Erase/Write Disable instruction (EWDS) is executed or VCC falls below the power-on reset threshold. To protect the memory contents from accidental corruption, it is advisable to issue the EWDS instruction after every write cycle. The READ instruction is not affected by the EWEN or EWDS instructions. Erase The Erase instruction (ERASE) programs the addressed memory byte or word bits to ’1’. Once the address is correctly decoded, the fallingedge of the Chip Select input (S) triggers a self-timed erase cycle. If the ST93C56 is still performing the erase cycle, the Busy signal (Q = 0) will be returned if S is driven high, and the ST93C56 will ignore any data on the bus. When the erase cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93C56 is ready to receive a new instruction. Write The Write instruction (WRITE) is followed by the address and the 8 or 16 data bits to be written. Data input is sampled on the Low to High transition of the clock. After the last data bit has been sampled, Chip Select (S) must be brought Low before the next rising edge of the clock (C) in order to start the self-timed programming cycle. If the ST93C56 is still performing the write cycle, the Busy signal INSTRUCTIONS The ST93C56 has seven instructions, as shown in Table 6. The op-codes of the instructions are made up of 2 bits. The op-code is followed by an address for the byte/word which is eight bits long for the x16 organization or nine bits long for the x8 organization. Each instruction is preceded by the rising edge of the signal applied on the Chip Select (S) input (assuming that the clock C is low). The data input D is then sampled upon the following rising edges of the clock C untill a ’1’ is sampled and decoded by the ST93C56 as a Start bit. The ST93C56 is fabricated in CMOS technology and is therefore able to run from zero Hz (static input signals) up to the maximum ratings (specified in Table 5). Read The Read instruction (READ) outputs serial data on the Data Output (Q). When a READ instruction is received, the instruction and address are decoded and the data from the memory is transferred into an output shift register. A dummy ’0’ bit is output first, followed by the 8 bit byte or the 16 bit word with the MSB first. Output data changes are triggered by the Low to High transition of the Clock (C). The ST93C56 will automatically increment the address and will clock out the next byte/word as long as the Chip Select input (S) is held High. In this case the dummy ’0’ bit is NOT output between bytes/words and a continuous stream of data can be read. Erase/Write Enable and Disable The Erase/Write Enable instruction (EWEN) authorizes the following Erase/Write instructions to Table 6. Instruction Set Description Op-Code x8 Org Address (ORG = 0) (1, 2) Data x16 Org Address (ORG = 1) (1, 3) Data READ Read Data from Memory 10 A8-A0 Q7-Q0 A7-A0 Q15-Q0 WRITE Write Data to Memory 01 A8-A0 D7-D0 A7-A0 D15-D0 EWEN Erase/Write Enable 00 11XXX XXXX 11XX XXXX EWDS Erase/Write Disable 00 00XXX XXXX 00XX XXXX ERASE Erase Byte or Word 11 A8-A0 A7-A0 ERAL Erase All Memory 00 10XXX XXXX 10XX XXXX WRAL Write All Memory with same Data 00 01XXX XXXX Instruction Notes: 1. X = don’t care bit. 2. Address bit A8 is not decoded by the ST93C56, ST93C56C. 3. Address bit A7 is not decoded by the ST93C56, ST93C56C. 6/13 D7-D0 01XX XXXX D15-D0 ST93C56/56C, ST93C57C Figure 6. READ, WRITE, EWEN, EWDS Sequences READ S D 1 1 0 An A0 Q Qn ADDR Q0 DATA OUT OP CODE WRITE S CHECK STATUS D 1 0 1 An A0 Dn D0 Q ADDR DATA IN BUSY READY OP CODE ERASE WRITE ENABLE ERASE WRITE DISABLE S D 1 0 0 1 1 Xn X0 OP CODE S D 1 0 0 0 0 Xn X0 OP CODE AI00878C Notes: 1. An: n = 7 for x16 org. and 8 for x8 org. 2. Xn: n = 5 for x16 org. and 6 for x8 org. (Q = 0) will be returned if S is driven high, and the ST93C56 will ignore any data on the bus. When the write cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93C56 is ready to receive a new instruction. Programming is internally self-timed (the external clock signal on C input may be disconnected or left running after the start of a programming cycle) and does not require an Erase instruction prior to the Write instruction (The Write instruction includes an automatic erase cycle before programing data). 7/13 ST93C56/56C, ST93C57C Figure 7. ERASE, ERAL Sequences ERASE S CHECK STATUS D 1 1 1 An A0 Q ADDR BUSY READY OP CODE ERASE ALL S CHECK STATUS 1 0 0 1 0 Xn X0 D Q ADDR BUSY READY OP CODE AI00879B Notes: 1. An: n = 7 for x16 org. and 8 for x8 org. 2. Xn: n = 5 for x16 org. and 6 for x8 org. Figure 8. WRAL Sequence WRITE ALL S CHECK STATUS D 1 0 0 0 1 Xn X0 Dn D0 Q ADDR DATA IN BUSY READY OP CODE AI00880C Note: 1. Xn: n = 5 for x16 org. and 6 for x8 org. 8/13 ST93C56/56C, ST93C57C Erase All The Erase All instruction (ERAL) erases the whole memory (all memory bits are set to ’1’). A dummy address is input during the instruction transfer and the erase is made in the same way as the ERASE instruction. If the ST93C56 is still performing the erase cycle, the Busy signal (Q = 0) will be returned if S is driven high, and the ST93C56 will ignore any data on the bus. When the erase cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93C56 is ready to receive a new instruction. Write All The Write All instruction (WRAL) writes the Data Input byte or word to all the addresses of the memory. If the ST93C56 is still performing the write cycle, the Busy signal (Q = 0) will be returned if S is driven high, and the ST93C56 will ignore any data on the bus. When the write cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93C56 is ready to receive a new instruction. READY/BUSY Status During every programming cycle (after a WRITE, ERASE, WRAL or ERAL instruction) the Data Output (Q) indicates the Ready/Busy status of the memory when the Chip Select (S) is driven High. Once the ST93C56 is Ready, the Ready/Busy status is available on the Data Output (Q) until a new start bit is decoded or the Chip Select (S) is brought Low. COMMON I/O OPERATION The Data Output (Q) and Data Input (D) signals can be connected together, through a current limiting resistor, to form a common, one wire data bus. Some precautions must be taken when operating the memory with this connection, mostly to prevent a short circuit between the last entered address bit (A0) and the first data bit output by Q. The reader may also refer to the SGS-THOMSON application note ”MICROWIRE EEPROM Common I/O Operation”. DIFF ERENCES BETWEEN ST93C56 AND ST93C56C The ST93C56C is an enhanced version of the ST93C56 and offers a functional security filtering glitches on the clock input (C). The following description will detail the Clock pulse counter (available only on the ST93C56C). In a normal environment, the ST93C56 expects to receive the exact amount of data on the D input, that is, the exact amount of clock pulses on the C input. In a noisy environment, the number of pulses received (on the clock input C) may be greater than the clock pulsesdelivered by the Master (Microcontroller) driving the ST93C56C. In such a case, a part of the instruction is delayed by one bit (see Figure 9), and it may induce an erroneous write of data at a wrong address. The ST93C56C has an on-chip counter which counts the clock pulses from the Start bit until the falling edge of the Chip Select signal. For the WRITE instructions, the number of clock pulses incoming to the counter must be exactly 20 (with the Organisation by 8) from the Start bit to the falling edge of Chip Select signal (1 Start bit + 2 bits of Op-code + 9 bits of Address + 8 bits of Data = 20): if so, the ST93C56C executes the WRITE instruction; if the number of clock pulses is not equal to 20, the instruction will not be executed (and data will not be corrupted). In the same way, when the Organisation by 16 is selected, the number of clock pulses incoming to the counter must be exactly 27 (1 Start bit + 2 bits of Op-code + 8 bits of Address + 16 bits of Data = 27) from the Start bit to the falling edge of Chip Select signal: if so, the ST93C56C executes the WRITE instruction; if the number of clock pulses is not equal to 27, the instruction will not be executed (and data will not be corrupted). The clock pulse counter is active only on ERASE and WRITE instructions (WRITE, ERASE, ERAL, WRALL). 9/13 ST93C56/56C, ST93C57C Figure 9. WRITE Sequence with One Clock Glitch S C D An START ”0” ”1” An-2 An-1 Glitch D0 ADDRESS AND DATA ARE SHIFTED BY ONE BIT WRITE AI01395 ORDERING INFORMATION SCHEME Example: Revision Operating Voltage 56 4.5V to 5.5V 57 3V to 5.5V ST93C56C blank CMOS F3 C CMOS F4 M 1 013TR Package B PSDIP8 0.4 mm Frame M SO8 150mil Width Temperature Range 1 0 to 70 °C 6 –40 to 85 °C 3 (1) –40 to 125 °C Option 013TR Tape & Reel Packing (A, T ver.) TR Tape & Reel Packing (C version) Note: 1. Temperature range on special request only. Devices are shipped from the factory with the memory content set at all ”1’s” (FFFFh for x16, FFh for x8). For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. 10/13 ST93C56/56C, ST93C57C PSDIP8 - 8 pin Plastic Skinny DIP, 0.4mm lead frame mm Symb Typ inches Min Max A Typ Min 4.80 Max 0.189 A1 0.70 – 0.028 – A2 3.10 3.60 0.122 0.142 B 0.38 0.58 0.015 0.023 B1 1.15 1.65 0.045 0.065 C 0.38 0.52 0.015 0.020 D 9.20 9.90 0.362 0.390 – – – – 6.30 7.10 0.248 0.280 – – – – 8.40 – 0.331 – E 7.62 E1 e1 2.54 eA eB 0.300 0.100 9.20 L 3.00 N 8 0.362 3.80 0.118 0.150 8 CP 0.10 0.004 PSDIP8 A2 A1 B A L e1 eA eB B1 D C N E1 E 1 PSDIP-a Drawing is not to scale 11/13 ST93C56/56C, ST93C57C SO8 - 8 lead Plastic Small Outline, 150 mils body width mm Symb Typ inches Min Max A 1.35 A1 Min Max 1.75 0.053 0.069 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 – – – – H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 0.90 0.016 0.035 α 0° 8° 0° 8° N 8 e 1.27 CP Typ 0.050 8 0.10 0.004 SO8 h x 45° A C B CP e D N E H 1 A1 SO-a Drawing is not to scale 12/13 α L ST93C56/56C, ST93C57C Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1997 SGS-THOMSON Microelectronics - All Rights Reserved MICROWIRE is a registered trademark of National Semiconductor Corp. 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