ST93C06 ST93C06C 256 bit (16 x 16 or 32 x 8) SERIAL MICROWIRE EEPROM NOT FOR NEW DESIGN 1 MILLION ERASE/WRITE CYCLES, with 40 YEARS DATA RETENTION DUAL ORGANIZATION: 16 x 16 or 32 x 8 BYTE/WORD and ENTIRE MEMORY PROGRAMMING INSTRUCTIONS SELF-TIMED PROGRAMMING CYCLE with AUTO-ERASE READY/BUSY SIGNAL DURING PROGRAMMING SINGLE 5V ±10% SUPPLY VOLTAGE SEQUENTIAL READ OPERATION 5ms TYPICAL PROGRAMMING TIME ENHANCED ESD/LATCH UP PERFORMANCES for ”C” VERSION ST93C06 and ST93C06C are replaced by the M93C06 PSDIP8 (B) 0.4mm Frame D Serial Data Input Q Serial Data Output C Serial Clock ORG Organisation Select VCC Supply Voltage VSS Ground SO8 (M) 150mil Width Figure 1. Logic Diagram Table 1. Signal Names Chip Select Input 1 1 DESCRIPTION The ST93C06 and ST93C06C are 256 bit Electrically Erasable Programmable Memory (EEPROM) fabricated with SGS-THOMSON’s High Endurance Single Polysilicon CMOS technology. In the text the two products are referred to as ST93C06. The memory is divided into either 32 x 8 bit bytes or 16 x 16 bit words. The organization may be selected by a signal applied on the ORG input. The memory is accessed through a serial input (D) and by a set of instructions which includes Read a byte/word, Write a byte/word, Erase a byte/word, Erase All and Write All. ARead instruction loads the address of the first byte/word to be read into an internal address pointer. S 8 8 June 1997 This is information on a product still in production bu t not recommended for new de signs. VCC D C S Q ST93C06 ST93C06C ORG VSS AI00816B 1/15 ST93C06, ST93C06C Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections ST93C06 ST93C06C ST93C06 ST93C06C S C D Q 1 2 3 4 8 7 6 5 VCC DU ORG VSS S C D Q 1 2 3 4 AI00817B 8 7 6 5 VCC DU ORG VSS AI00818C Warning: DU = Don’t Use Warning: DU = Don’t Use Table 2. Absolute Maximum Ratings (1) Symbol Value Unit Ambient Operating Temperature –40 to 125 °C TSTG Storage Temperature –65 to 150 °C TLEAD Lead Temperature, Soldering 215 260 °C TA Parameter (SO8 package) (PSDIP8 package) VIO Input or Output Voltages (Q = VOH or Hi-Z) VCC Supply Voltage Electrostatic Discharge Voltage (Human Body model) VESD Electrostatic Discharge Voltage (Machine model) (3) (2) 40 sec 10 sec –0.3 to VCC +0.5 V –0.3 to 6.5 V ST93C06 ST93C06C 2000 4000 V ST93C06 ST93C06C 500 500 V Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω). 3. EIAJ IC-121 (Condition C) (200pF, 0 Ω). DESCRIPTION (cont’d) The data contained at this address is then clocked out serially. The address pointer is automatically incremented after the data is output and, if the Chip Select input (S) is held High, the ST93C06 can output a sequential stream of data bytes/words. In this way, the memory can be read as a data stream from 8 to 256 bits long, or continuously as the address counter automatically rolls over to ’00’ when the highest address is reached. Programming is internally self-timed (the external clock 2/15 signal on C input may be disconnected or left running after the start of a Write cycle) and does not require an erase cycle prior to the Write instruction. The Write instruction writes 8 or 16 bits at one time into one of the 32 bytes or 16 words. After the start of the programming cycle aBusy/Ready signal is available on the Data output (Q) when Chip Select (S) is driven High. The design of the ST93C06 and the High Endurance CMOS technologyused for its fabrication give an Erase/Write cycle Endurance of 1,000,000 cycles and a data retention of 40 years. ST93C06, ST93C06C AC MEASUREMENT CONDITIONS Input Rise and Fall Times ≤ 20ns Input Pulse Voltages 0.4V to 2.4V Input Timing Reference Voltages 1V to 2.0V Output Timing Reference Voltages 0.8V to 2.0V Figure 3. AC Testing Input Output Waveforms 2.4V 2V 2.0V 1V 0.8V 0.4V Note that Output Hi-Z is defined as the point where data is no longer driven. INPUT OUTPUT AI00815 Table 3. Capacitance (1) (TA = 25 °C, f = 1 MHz ) Symbol C IN COUT Parameter Input Capacitance Output Capacitance Test Condition Min Max Unit VIN = 0V 5 pF VOUT = 0V 5 pF Max Unit 0V ≤ VIN ≤ VCC ±2.5 µA Note: 1. Sampled only, not 100% tested. Table 4. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 5V ± 10%) Symbol Parameter Test Condition Min ILI Input Leakage Current ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA Supply Current (TTL Inputs) S = VIH, f = 1 MHz 3 mA Supply Current (CMOS Inputs) S = VIH, f = 1 MHz 2 mA ICC1 Supply Current (Standby) S = VSS, C = VSS, ORG = VSS or VCC 50 µA VIL Input Low Voltage (D, C, S) –0.3 0.8 V VIH Input High Voltage (D, C, S) 2 VCC + 1 V VOL Output Low Voltage IOL = 2.1mA 0.4 V IOL = 10 µA 0.2 V ICC VOH Output High Voltage IOH = –400µA 2.4 V IOH = –10µA VCC – 0.2 V 3/15 ST93C06, ST93C06C Table 5. AC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 5V ± 10%) Symbol Alt Parameter Test Condition Min Max Unit tSHCH tCSS Chip Select High to Clock High 50 ns tCLSH tSKS Clock Low to Chip Select High 100 ns tDVCH tDIS Input Valid to Clock High 100 ns Temp. Range: grade 1 100 ns tCHDX tDIH Clock High to Input Transition Temp. Range: grades 3, 6 200 ns tCHQL tPD0 Clock High to Output Low 500 ns tCHQV tPD1 Clock High to Output Valid 500 ns tCLSL tCSH Clock Low to Chip Select Low 0 ns Chip Select Low to Clock High 250 ns 250 ns tSLCH tSLSH tCS Chip Select Low to Chip Select High tSHQV tSV Chip Select High to Output Valid tSLQZ tDF Chip Select Low to Output Hi-Z Note 1 500 ns ST93C06 300 ns ST93C06C 200 ns tCHCL tSKH Clock High to Clock Low Note 2 250 ns tCLCH tSKL Clock Low to Clock High Note 2 250 ns tW tWP Erase/Write Cycle time fC fSK Clock Frequency 0 10 ms 1 MHz Notes: 1. Chip Select must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles. 2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings tCHCL + tCLCH must be greater or equal to 1 µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns. Figure 4. Synchronous Timing, Start and Op-Code Input tCLCH tCLSH C tSHCH tCHCL S tCHDX tDVCH D START START OP CODE OP CODE OP CODE OP CODE OP CODE INPUT AI00819C 4/15 ST93C06, ST93C06C Figure 5. Synchronous Timing, Read or Write C tCLSL S tDVCH D tCHDX tCHQV tSLSH A0 An tSLQZ tCHQL Hi-Z Q Q15/Q7 ADDRESS INPUT Q0 DATA OUTPUT AI00820C tSLCH C tCLSL S tDVCH D An tCHDX tSLSH A0/D0 tSHQV tSLQZ Hi-Z Q BUSY READY tW ADDRESS/DATA INPUT WRITE CYCLE AI01429 DESCRIPTION (cont’d) The DU (Don’t Use) pin does not affect the function of the memory and it is reserved for use by SGSTHOMSON during test sequences.The pin may be left unconnected or may be connected to VCC or VSS. Direct connection of DU to VSS is recommended for the lowest standby power consumption. MEMORY ORGANIZATION The ST93C06 is organized as 32 bytes x 8 bits or 16 words x 16 bits. If the ORG input is left unconnected (or connected to VCC) the x16 organization is selected, when ORG is connected to Ground (VSS) the x8 organization is selected. When the ST93C06 is in standby mode, the ORG input should be unconnected or set to either VSS or VCC in order to achieve the minimum power consumption. Any voltage between VSS and VCC applied to ORG may increase the standby current value. 5/15 ST93C06, ST93C06C POWER-ON DATA PROTECTION In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit resets all internal programming circuitry and sets the device in the Write Disable mode. When VCC reaches its functional value, the device is properlyreset (in the Write Disable mode) and is ready to decode and execute an incoming instruction. A stable VCC must be applied before any logic signal. INSTRUCTIONS The ST93C06 has seven instructions, as shown in Table 6. The op-codes of the instructions are made up of 4 bits: some instructions use only the first two bits, others use all four bits to define the op-code. The op-code is followed by an address for the byte/word which is four bits long for the x16 organization or five bits long for the x8 organization. Each instruction is preceded by the rising edge of the signal applied on the S input (assuming that clock C and data input D are low), followed by a first clock pulse which is ignored by the ST93C06 (optional clock pulse for the ST93C06C). The data input D is then sampled upon the following rising edges of the clock C untill a ’1’ is sampled and decoded by the ST93C06 as a Start bit. Even though the first clock pulse is ignored, it recommended to pull low the data input D during this first clock pulse in order to keep the timing upwardly compatible with other ST93Cxx devices. The ST93C06 is fabricated in CMOS technology and is therefore able to run from zero Hz (static input signals) up to the maximum ratings (specified in Table 5). Read The Read instruction (READ) outputs serial data on the Data Output (Q). When a READ instruction is received, the instruction and address are decoded and the data from the memory is transferred into an output shiftregister. A dummy ’0’ bit is output first followed by the 8 bit byte or the 16 bit word with the MSB first. Output data changes are triggered by the Low to High transition of the Clock (C). The ST93C06 will automatically increment the address and will clock out the next byte/word as long as the Chip Select input (S) is held High. In this case the dummy ’0’ bit is NOT output between bytes/words and a continuous stream of data can be read. Erase/Write Enable and Disable The Erase/Write Enable instruction (EWEN) authorizesthe following Erase/Write instructions to be executed, the Erase/Write Disable instruction (EWDS) disables the execution of the following Erase/Write instructions. When power is first applied, the ST93C06 enters the Disable mode. When the Erase/Write Enable instruction (EWEN) is executed, Write instructions remain enabled until an Erase/Write Disable instruction (EWDS) is executed or if the Power-on reset circuit becomes active due to a reduced VCC. To protect the memory contents from accidental corruption, it is advisable to issue the EWDS instruction after every write cycle. The READ instruction is not affected by the EWEN or EWDS instructions. Erase The Erase instruction (ERASE) programs the addressed memory byte or word bits to ’1’. Once the address is correctly decoded, the falling edge of the Chip Select input (S) triggers a self-timed erase cycle. Table 6. Instruction Set Instruction Description Op-Code x8 Org Address (ORG = 0) Data x16 Org Address (ORG = 1) Data READ Read Data from Memory 10XX A4-A0 Q7-Q0 A3-A0 Q15-Q0 WRITE Write Data to Memory 01XX A4-A0 D7-D0 A3-A0 D15-D0 EWEN Erase/Write Enable 0011 XXXXX XXXX EWDS Erase/Write Disable 0000 XXXXX XXXX ERASE Erase Byte or Word 11XX A4-A0 A3-A0 ERAL Erase All Memory 0010 XXXXX XXXX WRAL Write All Memory with same Data 0001 XXXXX Note: X = don’t care bit. 6/15 D7-D0 XXXX D15-D0 ST93C06, ST93C06C Figure 6. READ, WRITE, EWEN, EWDS Sequences READ S D 1 1 0 X X An A0 Q Qn OP CODE ADDR WRITE Q0 DATA OUT S CHECK STATUS D 1 0 1 X X An A0 Dn D0 Q OP CODE ADDR ERASE WRITE ENABLE S D DATA IN ERASE WRITE DISABLE 1 0 0 1 1 Xn X0 OP CODE BUSY READY S D 1 0 0 0 0 Xn X0 OP CODE AI00822D Notes: 1. An: n = 3 for x16 org. and 4 for x8 org. 2. Xn: n = 3 for x16 org. and 4 for x8 org. If the ST93C06 is still performing the erase cycle, the Busy signal (Q = 0) will be returned if S is driven high, and the ST93C06 will ignore any data on the bus. When the erase cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93C06 is ready to receive a new instruction. Write The Write instruction (WRITE) is followed by the address and the 8 or 16 data bits to be written. Data input is sampled on the Low to High transition of the clock. After the last data bit has been sampled, Chip Select (S) must be brought Low before the next rising edge of the clock (C) in order to start the self-timed programming cycle. If the ST93C06 is still performing the write cycle, the Busy signal (Q = 0) will be returned if S is driven high, and the ST93C06 will ignore any data on the bus. When the write cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93C06 is ready to receive a new instruction. Programming is internally self-timed (the external clock signal on C input may be disconnected or left running after the start of a programming cycle) and does not require an Erase instruction prior to the Write instruction (The Write instruction includes an automatic erase cycle before programing data). 7/15 ST93C06, ST93C06C Figure 7. ERASE, ERAL Sequences ERASE S CHECK STATUS D 1 1 1 X X An A0 Q OP CODE ADDR ERASE ALL BUSY READY S CHECK STATUS D 1 0 0 1 0 Xn X0 Q OP CODE ADDR DUMMY BUSY READY AI00823B Notes: 1. An: n = 3 for x16 org. and 4 for x8 org. 2. Xn: n = 3 for x16 org. and 4 for x8 org. Figure 8. WRAL Sequence WRITE ALL S CHECK STATUS D 1 0 0 0 1 Xn X0 Dn D0 Q OP CODE ADDR DUMMY DATA IN BUSY READY AI00824B Note: 1 Xn: n = 3 for x16 org. and 4 for x8 org. 8/15 ST93C06, ST93C06C Erase All The Erase All instruction (ERAL) erases the whole memory (all memory bits are set to ’1’). A dummy address is input during the instruction transfer and the erase is made in the same way as the ERASE instruction. If the ST93C06 is still performing the erase cycle, the Busy signal (Q = 0) will be returned if S is driven high, and the ST93C06 will ignore any data on the bus. When the erase cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93C06 is ready to receive a new instruction. Write All For correct operation, an ERAL instruction should be executed before the WRAL instruction: the WRAL instruction DOES NOT perform an automatic erase before writing. The Write All instruction (WRAL) writes the Data Input byte or word to all the addresses of the memory. If the ST93C06 is still performing the write cycle, the Busy signal (Q = 0) will be returned if S is driven high, and the ST93C06 will ignore any data on the bus. When the write cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93C06 is ready to receive a new instruction. memory when the Chip Select (S) is driven High. Once the ST93C06 is Ready, the Ready/Busy status is available on the Data Output (Q) until a new start bit is decoded or the Chip Select (S) is brought Low. COMMON I/O OPERATION The Data Output (Q) and Data Input (D) signals can be connected together, through a current limiting resistor, to form a common, one wire data bus. Some precautions must be taken when operating the memory with this connection, mostly to prevent a short circuit between the last entered address bit (A0) and the first data bit output by Q. The reader may also refer to the SGS-THOMSON application note ”MICROWIRE EEPROM Common I/O Operation”. DIFF ERENCES BETWEEN ST93C06 AND ST93C06C Each instruction of the ST93C06 requires an Additional Dummy clock pulse after the rising edge of the Chip Select input (S) and before the START bit, see Figure 9. When replacing the ST93C06 with the ST93C06C in an application, it must be checked that this Dummy Clock cycle DOES NOT HAPPEN when D = 1: if it is so, this clock pulse will latch an information which is decoded by the ST93C06C as a START bit (see Figure 10) and the following bits will be decoded with a shift of one bit. READY/BUSY Status During every programming cycle (after a WRITE, ERASE, WRAL or ERAL instruction) the Data Output (Q) indicates the Ready/Busy status of the Figure 9. ST93C06 Timing S D C 0 1 Dummy Clock pulse START Bit AI01334 9/15 ST93C06, ST93C06C Figure 10. Comparative Timings WRONG TIMING S D C For ST93C06: For ST93C06C: GOOD TIMING 1 1 Dummy Clock pulse START Bit START Bit Bit = 1 0 1 S D C For ST93C06: For ST93C06C: Dummy Clock pulse START Bit Nothing happens (waits for D = 1) Bit = 1 AI01335 10/15 ST93C06, ST93C06C Figure 11. WRITE Swquence with One Clock Glitch S C D An START ”0” ”1” WRITE An-1 An-2 Glitch D0 ADDRESS AND DATA ARE SHIFTED BY ONE BIT AI01395 DIFFERENCES BETWEEN ST93C06 AND ST93C06C (cont’d) The ST93C06C is an enhanced version of the ST93C06A and offers the following extra features: – Enhanced ESD voltage – Functional security filtering glitches on the clock input (C). Refer to Table 2 (Absolute Maximum Ratings) for more about ESD limits. The following description will detail the Clock pulses counter (available only on the ST93C06C). In a normal environment, the ST93C06 is expected to receive the exact amount of data on the D input, that is the exact amount of clock pulses on the C input. In a noisy environment, the amount of pulses received (on the clock input C) may be greater than the clock pulses delivered by the Master (Microcontroller) driving the ST93C06C. In such a case, a part of the instruction is delayed by one bit (see Figure 11), and it may induce an erroneous write of data at a wrong address. The ST93C46C has an on-board counter which counts the clock pulses from the Start bit until the falling edge of the Chip Select signal. For the WRITE instructions, the number of clock pulses incoming to the counter must be exactly 18 (with the Organisation by 8) from the Start bit to the falling edge of Chip Select signal (1 Start bit + 2 bits of Op-code + 7 bits of Address + 8 bits of Data = 18): if so, the ST93C06C executes the WRITE instruction; if the number of clock pulses is not equal to 18, the instruction will not be executed (and data will not be corrupted). In the same way, when the Organisation by 16 is selected, the number of clock pulses incoming to the counter must be exactly 25 (1 Start bit + 2 bits of Op-code + 6 bits of Address + 16 bits of Data = 25) from the Start bit to the falling edge of Chip Select signal: if so, the ST93C06C executes the WRITE instruction; if the number of clock pulses is not equal to 25, the instruction will not be executed (and data will not be corrupted). The clock pulse counter is active only on ERASE and WRITE instructions (WRITE, ERASE, ERAL, WRALL). 11/15 ST93C06, ST93C06C ORDERING INFORMATION SCHEME Example: ST93C06C Package Revision blank CMOS F3 Tech. C CMOS F4 Tech. M B (1) PSDIP8 0.4mm Frame M SO8 150mil Width 1 013TR Temperature Range 1 0 to 70 °C 6 –40 to 85 °C 3 (2) Option 013TR Tape & Reel Packing –40 to 125 °C Notes: 1. ST93C06CB1 is available with 0.25mm lead Frame only. 2. Temperature range on special request only. Devices are shipped from the factory with the memory content set at all ”1’s” (FFFFh for x16, FFh for x8). For a list of available options (Package, etc...) or for further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. 12/15 ST93C06, ST93C06C PSDIP8 - 8 pin Plastic Skinny DIP, 0.4mm lead frame mm Symb Typ inches Min Max A Typ Min 4.80 Max 0.189 A1 0.70 – 0.028 – A2 3.10 3.60 0.122 0.142 B 0.38 0.58 0.015 0.023 B1 1.15 1.65 0.045 0.065 C 0.38 0.52 0.015 0.020 D 9.20 9.90 0.362 0.390 – – – – 6.30 7.10 0.248 0.280 – – – – 8.40 – 0.331 – E 7.62 E1 e1 2.54 eA eB 0.300 0.100 9.20 L 3.00 N 8 0.362 3.80 0.118 0.150 8 PSDIP8 A2 A1 B A L e1 eA eB B1 D C N E1 E 1 PSDIP-a Drawing is not to scale 13/15 ST93C06, ST93C06C SO8 - 8 lead Plastic Small Outline, 150 mils body width mm Symb Typ inches Min Max A 1.35 A1 Min Max 1.75 0.053 0.069 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 – – – – H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 0.90 0.016 0.035 α 0° 8° 0° 8° N 8 e 1.27 CP Typ 0.050 8 0.10 0.004 SO8 h x 45° A C B CP e D N E H 1 A1 SO-a Drawing is not to scale 14/15 α L ST93C06, ST93C06C Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1997 SGS-THOMSON Microelectronics - All Rights Reserved MICROWIRE is a registered trademark of National Semiconductor Corp. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 15/15