FXMA2104 Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / Isolator for Open-Drain Applications Features Description Bi-Directional Interface between Any Two Levels: 1.65V to 5.5V Direction Control not Needed The FXMA2104 is a 4-bit high-performance, configurable dual-voltage supply, open-drain translator for bi-directional voltage translation over a wide range of input and output voltages levels. I2C 400pF Buffer / Repeater System GPIO Resources Not Required when OE Tied to VCCA I2C-Bus® Isolation A/B Port VOL = 175mV (Typical), VIL = 150mV, IOL = 6mA Open-Drain Inputs / Outputs Supports I2C Clock Stretching & Multi-Master Outputs Switch to 3-State if Either VCC is at GND ESD Protection Exceeds: - 5kV HBM ESD (per JESD22-A114) - 2kV CDM (per JESD22-C101) Accommodates Standard-Mode and Fast-Mode I2C-Bus Devices Fully Configurable: Inputs and Outputs Track VCC Non-Preferential Power-Up; Either VCC May Be Powered-Up First Intended for use as a voltage translator in applications 2 ® using the I C-Bus interface, the input and output voltage levels are compatible with I2C device specification voltage levels. External pull-up resistors are required. The device is designed so that the A port tracks the VCCA level and the B port tracks the VCCB level. This allows for bi-directional A/B port voltage translation between any two levels from 1.65V to 5.5V. VCCA can equal VCCB from 1.65V to 5.5V. Non-preferential power-up means either VCC can be powered-up first. Internal power-down control circuits place the device in 3-state if either VCC is removed. The two ports of the device have automatic directionsense capability. Either port may sense an input signal and transfer it as an output signal to the other port. Tolerant Output Enable: 5V Packaged in 12-Lead Ultrathin MLP (1.8mm x 1.8mm) Ordering Information Part Number Operating Temperature Range Top Mark FXMA2104UMX -40 to +85°C BX © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 Package 12-Lead, Ultrathin, MLP, 1.8mm x 1.8mm Packing Method 5000 Units on Tape and Reel www.fairchildsemi.com FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications July 2012 OE VCCB Dynamic Driver (with Time Out) Internal Direction Generator & Control VbiasB VbiasA B A VCCA Internal Direction Generator & Control Dynamic Driver (with Time Out) Figure 1. Block Diagram, 1 of 4 Channels © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications Block Diagram www.fairchildsemi.com 2 Figure 2. UMLP (Top-Through View) Pin Definitions Pin # Name Description 1 VCCB B-Side Power Supply 2 VCCA A-Side Power Supply 3, 4, 5, 6 A0, A1, A2, A3 7 GND 8 OE 9, 10, 11, 12 B3, B2, B1, B0, A-Side Inputs or 3-State Outputs Ground Output Enable Input B-Side Inputs or 3-State Outputs Truth Table Control Outputs OE LOW Logic Level 3-State HIGH Logic Level Normal Operation Note: 1. If the OE pin is driven LOW, the FXMA2104 is disabled and the A0, A1, A2, A3, B0, B1, B2 and B3 pins (including dynamic drivers) are forced into 3-state. © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications Pin Configuration www.fairchildsemi.com 3 Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. -0.5 7.0 A Port -0.5 7.0 B Port -0.5 7.0 Control Input (OE) -0.5 7.0 An Outputs 3-State -0.5 7.0 Bn Outputs 3-State -0.5 7.0 An Outputs Active -0.5 VCCA + 0.5V Bn Outputs Active -0.5 VCCB + 0.5V VCCA, VCCB Supply Voltage VIN VO IIK IOK IOH / IOL DC Input Voltage Output Voltage(2) DC Input Diode Current DC Output Diode Current At VIN < 0V -50 At VO < 0V -50 At VO > VCC +50 DC Output Source/Sink Current -50 Units V V mA mA +50 mA ICC DC VCC or Ground Current per Supply Pin ±100 mA PD Power Dissipation 0.129 mW +150 °C At 400KHz TSTG Storage Temperature Range ESD Electrostatic Discharge Capability -65 Human Body Model, JESD22-A114 5 Charged Device Mode, JESD22-C101 2 kV Note: 2. IO absolute maximum rating must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VCCA, VCCB Power Supply Operating A Port VIN Input Voltage Min. Max. Units 1.65 5.50 V 0 5.5 B Port 0 5.5 Control Input (OE) 0 VCCA ΘJA Thermal Resistance TA Free Air Operating Temperature -40 V 301.5 C°/W +85 °C FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications Absolute Maximum Ratings Note: 3. All unused inputs and I/O pins must be held at VCCI or GND, VCCI is the VCC associated with the input side. © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 www.fairchildsemi.com 4 Power-Up/Power-Down Sequencing FXM translators offer an advantage in that either VCC may be powered up first. This benefit derives from the chip design. When either VCC is at 0V, outputs are in a high-impedance state. The control input (OE) is designed to track the VCCA supply. A pull-down resistor tying OE to GND should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up/power-down. The size of the pulldown resistor is based upon the current-sinking capability of the device driving the OE pin. The recommended power-up sequence is: 1. Apply power to the first VCC. 2. Apply power to the second VCC. 3. Drive the OE input HIGH to enable the device. The recommended power-down sequence is: 1. Drive OE input LOW to disable the device. 2. Remove power from either VCC. 3. Remove power from other VCC. Note: 4. Alternatively, the OE pin can be hardwired to VCCA to save GPIO pins. If OE is hardwired to VCCA, either VCC can be powered up or down first. Application Circuit FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications Functional Description Figure 3. Application Circuit © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 www.fairchildsemi.com 5 between the ports until either of the port’s VCC/2 thresholds are reached. After the RC time constant has reached the VCC/2 threshold of either port, the port’s edge detector triggers both dynamic drivers to drive their respective ports in the LOW-to-HIGH (LH) direction, accelerating the rising edge. The resulting rise time resembles the scope shot in Figure 4. Effectively, two distinct slew rates appear in rise time. The first slew rate (slower) is the RC time constant of the bus. The second slew rate (much faster) is the dynamic driver accelerating the edge. The FXMA2104 has open-drain I/Os and requires external pull-up resistors on the eight data I/O pins, as shown in Figure 3. If a pair of data I/O pins (An/Bn) is not used, both pins should be tied to GND (or both to VCC). In this case, pull-down or pull-up resistors are not required. The recommended values for the pull-up resistors (RPUs) are 1KΩ to 10K, depending on the total bus capacitance, the user is free to vary the pull-up resistor value to meet the maximum I2C edge rate per 2 the I C specification (UM10204 rev. 03, June 19, 2007). For example, the maximum edge rate (30% - 70%) during Fast Mode (400kbit/s) is 300ns. If bus capacitance is approaching the maximum 400pF, lower the RPU value to keep the rise time below 300ns (Fast Mode). Section 7.1 of the I2C specification provides an excellent guideline for pull-up resistor sizing. If both the A and B ports of the translator are HIGH, a high-impedance path exists between the A and B ports because both the Npassgates are turned off. If a master or slave device decides to pull SCL or SDA LOW, that device’s driver pulls down (Isink) SCL or SDA until the edge reaches the A or B port VCC/2 threshold. When either the A or B port threshold is reached, the port’s edge detector triggers both dynamic drivers to drive their respective ports in the HIGH-to-LOW (HL) direction, accelerating the falling edge. Theory of Operation The FXMA2104 is designed for high-performance level 2 shifting and buffer / repeating in an I C application. Figure 1 shows that each bi-directional channel contains two series-Npassgates and two dynamic drivers. This hybrid architecture is highly beneficial in an I2C application where auto-direction is a necessity. For example, during the following three I2C protocol events: Clock Stretching Slave’s ACK Bit (9th bit = 0) following a Master’s th Write Bit (8 bit = 0) Clock Synchronization and Multi Master Arbitration the bus direction needs to change from master-to-slave to slave-to-master without the occurrence of an edge. If there is an I2C translator between the master and slave 2 in these examples, the I C translator must change direction when both A and B ports are LOW. The Npassgates can accomplish this task very efficiently because, when both A and B ports are LOW, the Npassgates act as a low resistive short between the two (A and B) ports. Due to I2C’s open-drain topology, I2C masters and slaves are not push-pull drivers. Logic LOWs are “pulled down” (Isink), while logic HIGHs are “let go” (3-state). For example, when the master lets go of SCL (SCL always comes from the master), the rise time of SCL is largely determined by the RC time constant, where R = RPU and C = the bus capacitance. If the FXMA2104 is attached to the master [on the A port] and there is a slave on the B port, the Npassgates act as a low resistive short © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 Figure 4. Waveform C: 600pF, Total RPU: 2.2KΩ FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications Application Information www.fairchildsemi.com 6 The I2C specification mandates a maximum VIL (IOL of 3mA) of VCC • 0.3 and a maximum VOL of 0.4V. If there is a master on the A port of an I2C translator with a VCC 2 of 1.65V and a slave on the I C translator B port with a VCC of 3.3V, the maximum VIL of the master is (1.65V x 0.3) 495mV. The slave could legally transmit a valid logic LOW of 0.4V to the master. The FXMA2104 dynamic drivers have enough currentsourcing capability to drive a 400pF capacitive bus. This is beneficial when an I2C buffer / repeater is required. 2 The I C specification stipulates a maximum bus capacitance of 400pF. If an I2C segment exceeds 2 400pF, an I C buffer / repeater is required to split the segment into two segments, each of which is less than 400pF. Figure 4 is a scope shot of an FXMA2104 driving a lumped load of 600pF. Notice the (30% - 70%) rise time is only 112ns (total RPU = 2.2K). This is well below the maximum edge rate of 300ns. Not only does the FXMA2104 drive 400Pf; it also provides excellent 2 headroom below the I C specification maximum edge rate of 300ns. If the I2C translator’s channel resistance is too high, the voltage drop across the translator could present a VIL to the master greater than 495mV. To complicate matters, 2 the I C specification states that 6mA of IOL is recommended for bus capacitances approaching 400pF. More IOL increases the voltage drop across the 2 2 2 I C translator. The I C application benefits when I C translators exhibit low VOL performance. Figure 5 depicts typical FXMA2104 VOL performance vs. a competitor, given a 0.4V VIL. VOL: FXMA2104 vs. Device B, VIL = 0.4V 0.65 0.6 0.55 VOL (V): Device B VIL = 0.4V FXMA2104 VIL = 0.4V 0.5 0.45 0.4 0 2 4 6 IOL (mA): 8 10 FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications VOL vs. IOL Buffer / Repeater Performance Figure 5. VOL vs. IOL © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 www.fairchildsemi.com 7 The FXMA2104 supports I2C-Bus® isolation for the following conditions: Bus isolation if bus clear Bus isolation if either VCC goes to ground Bus Clear Because the I2C specification defines the minimum SCL frequency of DC, the SCL signal can be held LOW forever; however, this condition shuts down the I2C bus. 2 The I C specification refers to this condition as Bus Clear. In Figure 6, if slave #2 holds down SCL forever, the master and slave #1 are not able to communicate because the FXMA2104 passes the SCL stuck-LOW Either VCC to GND If slave #2 is a camera that is suddenly removed from the I2C bus, resulting in VCCB transitioning from a valid VCC (1.65V – 5.5V) to 0V; the FXMA2104 automatically forces all I/Os on both its A and B ports into 3-state. Once VCCB has reached 0V, full I2C communication between the master and slave #1 remains undisturbed. Slave #1 VCC = 1.8V SCL1 SCL1 SCL1 SDA1 SDA 1 SDA1 Master SDA 2 SCL2 VCCB SCL1 SDA 2 VCC = 3.3V SCL2 OE SDA 2 OE: High Enable Low Disable VCCA : 1.65V – 5.5V VCC Domain VCCB : 1.65V – 5.5V VCC Domain Figure 6. Bus Isolation © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 Slave #2 SDA 1 SCL2 SDA 2 GPIO3 VCCA FXMA 2104 I2C Buffer Translator VCC = 1.8V SCL2 VCC = 3.3V Slave #3 FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications condition from slave #2 to slave #1 as well as the master. However, if the OE pin is pulled LOW (disabled), both ports (A and B) are 3-stated. This results in the FXMA2104 isolating slave #2 from the master and slave #1, allowing full communication between the master and slave #1. 2 I C Bus Isolation www.fairchildsemi.com 8 TA = –40°C to +85°C. Symbol Parameter VIHA High Level Input Voltage A VIHB High Level Input Voltage B VILA Low Level Input Voltage A VILB Low Level Input Voltage B VOL Low Level Output Voltage IL IOFF IOZ Input Leakage Current Power-Off Leakage Current 3-State Output Leakage(6) Condition VCCA (V) VCCB (V) Min. Max. Unit Data Inputs An 1.65–5.50 1.65–5.50 VCCA – 0.4 Control Input OE 1.65–5.50 1.65–5.50 0.7 x VCCA Data Inputs Bn 1.65–5.50 1.65–5.50 VCCB – 0.4 Data Inputs An 1.65–5.50 1.65–5.50 0.4 Control Input OE 1.65–5.50 1.65–5.50 0.3 x VCCA Data Inputs Bn 1.65–5.50 1.65–5.50 0.4 V 1.65–5.50 1.65–5.50 0.4 V 1.65–5.50 1.65–5.50 ±1 µA V V V VIL = 0.15V IOL = 6mA Control Input OE, VIN = VCCA or GND An VIN or VO = 0V to 5.5V 0 5.50 ±2 Bn VIN or VO = 0V to 5.5V 5.50 0 ±2 An, Bn VO = 0V to 5.5V, OE = VIL 5.50 5.50 ±2 An VO = 0V to 5.5V, OE = Don’t Care 5.50 0 ±2 Bn VO = 0V to 5.5V, OE = Don’t Care 0 5.50 ±2 µA µA ICCA/B Quiescent Supply Current(7,8) VIN = VCCI or GND, IO = 0 1.65–5.50 1.65–5.50 5 µA ICCZ Quiescent Supply Current(7) VIN = VCCI or GND, IO = 0, OE = VIL 1.65–5.50 1.65–5.50 5 µA 1.65–5.50 -2 ICCA VIN = 5.5V or GND, IO = 0, OE = Don’t Care, Bn to An 0 Quiescent Supply Current(6) 1.65–5.50 0 2 0 -2 ICCB VIN = 5.5V or GND, IO = 0, OE = Don’t Care, An to Bn 1.65–5.50 Quiescent Supply Current(6) 0 1.65–5.50 2 µA µA Notes: 5. This table contains the output voltage for static conditions. Dynamic drive specifications are given in Dynamic Output Electrical Characteristics. 6. “Don’t Care” indicates any valid logic level. 7. VCCI is the VCC associated with the input side. 8. Reflects current per supply, VCCA or VCCB. © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications DC Electrical Characteristics www.fairchildsemi.com 9 Output Rise / Fall Time Output load: CL = 50pF, RPU = 2.2kΩ, push / pull driver, and TA = -40°C to +85°C. VCCO(10) Symbol 4.5 to 5.5V 3.0 to 3.6V Parameter 2.3 to 2.7V 1.65 to 1.95V Unit Typical trise tfall Output Rise Time; A Port, B Port(11) (12) Output Fall Time; A Port, B Port 3 4 5 7 ns 11 8 6 4 ns Notes: 9. Output rise and fall times guaranteed by design simulation and characterization; not production tested. 10. VCCO is the VCC associated with the output side. 11. See Figure 11. 12. See Figure 12. ( ) Maximum Data Rate 13 Output load: CL = 50pF, RPU = 2.2kΩ, push-pull driver, and TA = -40°C to +85°C. VCCB VCCA Direction 4.5 to 5.5V 3.0 to 3.6V 2.3 to 2.7V 1.65 to 1.95V Unit Minimum 4.5V to 5.5V 3.0V to 3.6V 2.3V to 2.7V 1.65V to 1.95V A to B 26 20 16 9 B to A 26 20 16 9 A to B 26 20 16 9 B to A 26 20 16 9 A to B 26 20 16 9 B to A 26 20 16 9 A to B 26 20 16 9 B to A 26 20 16 9 Note: 13. F-toggle guaranteed by design simulation; not production tested. © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 MHz MHz MHz MHz FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications Dynamic Output Electrical Characteristics www.fairchildsemi.com 10 Output Load: CL = 50pF, RPU = 2.2kΩ, and TA = -40°C to +85°C. VCCB Symbol Parameter VCCA = 4.5 to 5.5V A to B tPLH B to A A to B tPHL B to A OE to A tPZL OE to B OE to A tPLZ OE to B tskew A Port, B Port(14) VCCA = 3.0 to 3.6V A to B tPLH B to A A to B tPHL B to A OE to A tPZL OE to B OE to A tPLZ OE to B tskew A Port, B Port(14) VCCA = 2.3 to 2.7V A to B tPLH B to A A to B tPHL B to A OE to A tPZL OE to B OE to A tPLZ OE to B tskew A Port, B Port(14) VCCA = 1.65 to 1.95V A to B tPLH B to A A to B tPHL B to A OE to A tPZL OE to B OE to A tPLZ OE to B tskew A Port, B Port(14) 1.65 to 1.95V Units 4.5 to 5.5V 3.0 to 3.6V 2.3 to 2.7V Typ. Max. Typ. Max. Typ. Max. Typ. Max. 1 1 2 2 4 3 65 5 0.5 3 3 4 4 5 5 100 9 1.5 1 2 3 2 6 4 65 6 0.5 3 4 5 5 10 7 105 10 1.0 1 3 4 2 5 5 65 7 0.5 3 5 6 6 9 8 105 12 1.0 1 4 6 5 7 10 65 9 0.5 3 7 7 7 15 15 105 16 1.0 2.0 1.5 2 2 4 4 100 5 0.5 5.0 3.0 4 4 8 8 115 10 1.5 1.5 1.5 2 2 5 6 100 4 0.5 3.0 4.0 4 4 9 9 115 8 1.0 1.5 2.0 2 2 6 8 100 5 0.5 3.0 6.0 5 5 11 11 115 10 1.0 1.5 3.0 6 3 7 10 100 9 0.5 3.0 9.0 7 5 15 14 115 15 1.0 2.5 1.5 2 2 5 4.0 100 65 0.5 5.0 3.0 5 5 10 8.0 115 110 1.5 2.5 2.0 2 2 5 4.5 100 65 0.5 5.0 4.0 5 5 10 9.0 115 110 1.0 2.0 3.0 2 2 6 5.0 100 65 0.5 4.0 6.0 5 5 12 10.0 115 115 1.0 1.0 5.0 5 3 9.0 9.0 100 12 0.5 3.0 10.0 6 6 18.0 18.0 115 25 1.0 4.0 1.0 5 4 11 7.0 2.0 8 8 15 40. 1.0 3 3 11 7.0 2.0 7 7 14 5.0 1.5 3 3 14 8.0 3.0 7 7 28 5.0 5.0 8 3 14 10.0 10.0 9 7 23 6 75 75 0.5 14 115 115 1.5 6 75 75 0.5 14 115 115 1.0 6 75 75 0.5 14 115 115 1.0 9 75 75 0.5 19 115 115 1.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications AC Characteristics(17) ns ns Note: 14. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 14). Skew is guaranteed, but not tested. 15. AC Characteristic is guaranteed by Design and Characterization. © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 www.fairchildsemi.com 11 TA = +25°C. Symbol Parameter Condition Typical Unit CIN Input Capacitance Control Pin (OE) VCCA = VCCB = GND 2.2 pF CI/O Input / Output Capacitance, An, Bn VCCA = VCCB = 5.0V, OE = GND 13.0 pF Cpd Power Dissipation Capacitance VCCA = VCCB = 5.0V, VIN = 0V or VCC, f = 400KHz 13.5 pF Figure 7. AC Test Circuit Table 1. Table 2. Propagation Delay Table(17) Test Input Signal Output Enable Control tPLH, tPHL Data Pulses VCCA tPZL (OE to An, Bn) 0V LOW to HIGH Switch tPLZ (OE to An, Bn) 0V HIGH to LOW Switch VCCO CL RL 1.8 ± 0.15V 50pF 2.2kΩ 2.5 ± 0.2V 50pF 2.2kΩ 3.3 ± 0.3V 50pF 2.2kΩ 5.0 ± 0.5V 50pF 2.2kΩ AC Load Table © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications Capacitance www.fairchildsemi.com 12 DATA IN VCCI Vmi tpxx OUTPUT CONTROL GND tpxx DATA OUT VCCO DATA OUT VCCA Symbol Vmi GND tPLZ Vx VOL VY VOL Figure 9. 3-STATE Output Low Enable Time(16) Figure 8. Waveform for Inverting and Non-Inverting Functions(16) DATA OUT GND tPZL Vmo OUTPUT CONTROL VCCA Vmi VCC Vmi VCCI / 2 Vmo VCCO / 2 VX 0.5 x VCCO VY 0.1 x VCCO (16) Figure 10. 3-STATE Output High Enable Time Figure 11. Active Output Rise Time Figure 12. Active Output Fall Time VCCO DATA OUTPUT Vmo Vmo GND tperiod DATA IN VCCI / 2 VCCI / 2 tskew VCCI GND VCCO DATA OUTPUT F-toggle rate, f = 1 / tperiod tskew Vmo Vmo GND tskew = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin) Figure 13. F-Toggle Rate Figure 14. FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications Timing Diagrams Output Skew Time Notes: 16. Input tR = tF = 2.0ns, 10% to 90% at VIN = 1.65V to 1.95V; Input tR = tF = 2.0ns, 10% to 90% at VIN = 2.3 to 2.7V; Input tR = tF = 2.5ns, 10% to 90%, at VIN = 3.0V to 3.6V only; Input tR = tF = 2.5ns, 10% to 90%, at VIN = 4.5V to 5.5 only. 17. VCCI = VCCA for control pin OE or Vmi = (VCCA / 2). © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 www.fairchildsemi.com 13 1.80 0.10 C A (11X) 2.10 B 0.563 0.588 2X 1 1.80 0.40 2.10 PIN#1 IDENT TOP VIEW 0.55 MAX. 0.10 C 0.10 C (12X) 0.20 2X RECOMMENDED LAND PATTERN 0.152 0.45 0.35 0.08 C 0.05 0.00 0.10 SEATING C PLANE SIDE VIEW 0.10 0.10 DETAIL A SCALE : 2X NOTES: 0.35 (11X) 0.45 3 A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD. B. DIMENSIONS ARE IN MILLIMETERS. 6 0.40 DETAIL A C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 1 PIN#1 IDENT 12 9 BOTTOM VIEW D. LAND PATTERN RECOMMENDATION IS BASED ON FSC DESIGN ONLY. 0.25 0.15 (12X) 0.10 C A B 0.05 C E. DRAWING FILENAME: MKT-UMLP12Arev4. PACKAGE EDGE LEAD OPTION 1 SCALE : 2X LEAD OPTION 2 SCALE : 2X Figure 15. 12-Lead Ultrathin MLP, 1.8mm x 1.8mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1 FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications Physical Dimensions www.fairchildsemi.com 14 FXMA2104 — Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / for Open-Drain Applications 15 www.fairchildsemi.com © 2011 Fairchild Semiconductor Corporation FXMA2104 • Rev. 1.0.1