FXL3SD206 Level Shifting Voltage Translator Two-Port SDIO MUX/DEMUX with Three Configurable Power Supplies for SDIO Device Port Expansion Features Description Bi-Directional Interface between Two Levels: 1.65 to 3.6V Fully Configurable: Inputs and Outputs Track VDD Flexible and Programmable VDD of B and C Ports Non-Preferential Power-up; either VDD Can Power Up First Output Remains in 3-State until Active VDD Level is Reached Output Switches to 3-state if either VDD is at GND Power-off Protection Bus-Hold on Data Input Eliminates the Need for SDIO Pull-up Resistors 2:1 MUX/DEMUX of SDIO Devices in 24-Terminal Micro-MLP Package (2.5mm x 3.4mm) Direction Control is Automatic Power Switching Time (VDD_HI to VDD_LO or Reverse) is Less than 1.7µs 60Mbps Throughput ESD Protection Exceeds: 12KV HBM (A, B, and C port I/O to GND) (per JESD22-A114) 1KV CDM (per ESD STM5.3) Applications SDIO Devices Cell Phone, PDA, Digital Camera, Portable GPS FXL3SD206 is a voltage translator with multiplexing and de-multiplexing functions for SDIO devices. It is designed for voltage translation over a wide range of input and output levels, from 1.65V to 3.6V. The multiplexing/de-multiplexing function of this device allows expansion of a host SDIO interface to two SDIO peripheral devices. When selected, each SDIO peripheral can communicate with the host through the same host interface. An alternative application allows two host devices to interface with a single SDIO peripheral. FXL3SD206 — Level Shifting Voltage Translator March 2009 Port A is intended to connect to a host device and the voltage level tracks the VDDA. Ports B and C are intended to connect to peripheral devices. Peripheral I/O voltage levels track either VDD_HI or VDD_LO as determined by the VDD_SEL pin. During normal operation, VDD_HI must be greater than or equal to VDD_LO. The CH_SEL, VDD_SEL, and OE pins are referenced to VDD_CON. Channel communication from either Port A to Port B or Port A to Port C is controlled by the CH_SEL pin. The selected channel remains in 3-state until the VDD of each side reaches an active level and the OE pin reaches a valid high. Internal power-down circuitry places the selected channel of the device in 3-state if either side VDD removed. The direction of data is controlled automatically by the device. No direction control pin is required. The device senses input signals on any port automatically and transfers the data to the corresponding output. Ordering Information Part Number Operating Temperature Range Eco Status FXL3SD206UMX -40 to +85°C Green Package 24-Pin, Micro-MLP, Quad, .6mm Thick, 2.5mm x 3.4mm Body Packing Method Tape & Reel For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com Power Management IC VDDA VDD_CON VDD_LO VDD_HI VDD_HI SD Card VDD Select Card Select VDD_SEL 1CLK CH_SEL HOST In MUX CMD B CMD_B 1D0~D3 Out CMD Output Enable In CMD_ A Out DEMUX In OE D0~D3 CMD C 2D0~D3 CMD_C Out CLK_A CLK 2CLK VDD_LO SDIO Device WiFi LAN / Bluetooth / Memory Module CLK_BC D0_A~D3_A FXL3SD206 — Level Shifting Voltage Translator Application Diagrams D0_BC~D3_BC Figure 1. Single Host to Two SDIO Application Diagram Power Management IC VDD_LO VDDA VDD_CON VDD SEL OE CH SEL VDD Select Output Enable Card Select 1CLK SD Memory Or VDD_HI In MUX CMD CMD B Out CMD B 1D0~D3 VDD_HI Application Processor In CMD A SDIO Device 2CLK Out In DEMUX Out CLK CLK_A D0~D3 D0_A~D3_A CMD C CMD C 2D0~D3 VDD_LO Baseband Processor CLK_BC D0_BC~D3_BC Figure 2. Dual Host to Single SDIO Application © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 2 13 18 19 12 24 7 1 6 Figure 3. Pin Configuration (Top Through View) Pin Definitions Pin # Name Type Description 1 D0_A Data Data Pin of A Port 2 D1_A Data Data Pin of A Port 3 D2_A Data Data Pin of A Port 4 D3_A Data Data Pin of A Port 5 CLK_A Data Clock Pin of A Port 6 ---- NC 7 CMD_A Data 8 ---- NC 9 GND Power 10 CMD_C Data 11 ---- NC 12 CMD_B Data Command Pin of B Port 13 CLK_BC Data Clock Pin of B or C Port 14 D3_BC Data Data Pin of B or C Port 15 D2_BC Data Data Pin of B or C Port 16 D1_BC Data Data Pin of B or C Port Data Pin of B or C Port No Connect Command Pin of A Port No Connect Ground Command Pin of C Port No Connect 17 D0_BC Data 18 VDD_LO Power B or C Port, Low Power Supply 19 VDD_HI Power B or C Port, High Power Supply 20 VDD_CON Power Control Pin Power Supply 21 VDDA Power A-Port Power Supply 22 VDD_SEL Control Power Supply Select Pin of B and C Ports 23 CH_SEL Control Channel Select Pin 24 OE Control Output Enable Pin © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 FXL3SD206 — Level Shifting Voltage Translator Pin Configuration www.fairchildsemi.com 3 FXL3SD206 — Level Shifting Voltage Translator Function Diagram Figure 4. Function Diagram Function Table OE CH_SEL VDD_SEL Output LOW Don’t Care Don’t Care HIGH HIGH HIGH Normal operation; Port A to Port B channel selected; Port B tracks VDD_HI level HIGH HIGH LOW Normal operation; Port A to Port B channel selected; Port B tracks VDD_LO level HIGH LOW HIGH Normal operation; Port A to Port C channel selected; Port C tracks VDD_HI level HIGH LOW LOW Normal operation; Port A to Port C channel selected; Port C tracks VDD_LO level 3-State Note: 1. VDD_CON: This is a power supply pin that is used by the three control pins (VDD_SEL, CH_SEL, and OE). In single host mode, VDD_CON should be tied to the same supply as the VDDA pin. In dual host mode, VDD_CON should be tied to the same supply as either the VDD_HI or the VDD_LO pin, depending upon which host is used to drive the control pins. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 4 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VI VO Parameter Supply Voltage DC Input Voltage Output Voltage (2) IIK DC Input Diode Current IOK DC Output Diode Current IOH/IOL IDD TSTG Conditions VDDA, VDD_HI, VDD_LO, VDD_CON Min. Max. Unit -0.5 4.6 V Data Ports A, B, and C -0.5 4.6 V Control Inputs (OE, CH_SEL, VDD_SEL) -0.5 4.6 V Output 3-State -0.5 4.6 Output Active (Port A) -0.5 VDDA+0.5 Output Active (Port B or C) -0.5 VDD_HI+0.5 Output Active (Port B or C) -0.5 VDD_LO+0.5 VI<0V -50 VO<0V -50 VO>VCC +50 DC Output Source/Sink Current -50 DC VDD or Ground Current per Supply Pin Storage Temperature Range -65 V mA mA +50 mA ±100 mA +150 °C FXL3SD206 — Level Shifting Voltage Translator Absolute Maximum Ratings Note: 2. IO absolute maximum rating must be observed. Recommended Operating Conditions (3) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VDD Parameter Power Supply Operating Conditions VDDA, VDD_HI, VDD_LO, VDD_CON VDD_HI ≥ VDD_LO Input Voltage dt/dV 3.60 0 VDDA 0 VDD_HI (5) 0 VDD_LO -40 +85 Port B and C Free Air Operation Temperature Minimum Input Edge Rate 1.65 (5) Port B and C TA Max. (4) Port A VIN Min. Data Port A at VDDA=1.65 to 3.6V 10 Data Ports B and C at VDD_n=1.65 to 3.6V 10 OE, CH_SEL, VDD_SEL at VDD_CON=1.65V to 3.6V 10 Unit V V °C ns/V Notes: 3. All unused inputs and input/outputs must be held at VDDn or GND. 4. During normal operation, VDD_HI must be greater than or equal to VDD_LO. 5. The input and output voltages of Ports B and C are determined by which VDD is selected. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 5 Power-Up / Power-Down Sequencing FXL translators offer an advantage in that any VDD may be powered up first. This benefit derives from the chip design. When VDDA or both VDD_HI and VDD_LO pins are at 0 volts, outputs are in a high-impedance state (see Power Up Operation table below). As a multiplexer, the device allows the unselected port to remain in a high-impedance state for power saving. The control inputs (OE, CH_SEL, VDD_SEL) are designed to track VDD_CON. An external pull-down resistor tying OE to GND should be used to ensure that bus contention, excessive current, or oscillations do not occur during power-up/power-down. The size of the pull-down resistor is based upon the current-sinking capability of the device driving the OE pin. The recommended power-up sequence is: 1. 2. 3. 4. Apply the power to the first VDD. Apply the power to the second VDD. Set the CH_SEL and VDD_SEL pin according to the application. Drive the OE input high to enable the device. The recommended the power-down sequence is: 1. 2. 3. 4. Drive the OE input low to disable the device. Remove the setting of CH_SEL and VDD_SEL pin. Remove power from either VDD. Remove power from other VDD. During normal operation, VDD_HI must be greater than or equal to VDD_LO. During power-up or power-down, VDD_LO may exceed VDD_HI without damaging the device. Table 1. Power-Up Operation VDDA VDD_HI VDD_LO VDD_SEL Port B or C Outputs OFF Don’t Care Don’t Care Don’t Care High Impedance ON OFF OFF Don’t Care High Impedance ON ON OFF HIGH Enabled, Reference to VDD_HI LOW High Impedance ON OFF ON ON ON ON © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 HIGH High Impedance LOW Enabled, Reference to VDD_LO HIGH Enabled, Reference to VDD_HI LOW Enabled, Reference to VDD_LO FXL3SD206 — Level Shifting Voltage Translator Application Information www.fairchildsemi.com 6 TA=-40°C to 85°C unless otherwise specified. Symbol Parameter Condition VDD_A, VDD_n, (V) Min. Max. Units VIHA Data Inputs Dn_A, CMD_A, CLK_A, 1.65 – 3.6 0.6 x VDD_A V VIHB Data Inputs Dn_BC, CMD_B, CLK_BC, CH_SEL=H 1.65 – 3.6 0.6 x VDD_n V Data Inputs Dn_BC, CMD_C, CLK_BC, CH_SEL=L 1.65 – 3.6 0.6 x VDD_n V VIHC High Level Input (6) Voltage VIH OE, VDD_SEL, CH_SEL 1.65 – 3.6 0.6 x VDD_CON VILA Data Inputs Dn_A, CMD_A, CLK_A, 1.65 – 3.6 0.35 x VDD_A V VILB Data Inputs Dn_BC, CMD_B, CLK_BC, CH_SEL=H 1.65 -3.6 0.35 x VDD_n V Data Inputs Dn_BC, CMD_C, CLK_BC, CH_SEL=L 1.65 -3.6 0.35 x VDD_n V OE, VDD_SEL, CH_SEL 1.65 – 3.6 0.35 x VDD_CON V Data Outputs Dn_A, CMD_A, CLK_A, IHOLD=-20µA 1.65 – 3.6 0.75 x VDD_A V Data Outputs Dn_BC, CMD_B, CLK_BC, CH_SEL=H, IHOLD=-20µA 1.65 – 3.6 0.75 x VDD_n V VOHC Data Outputs Dn_BC, CMD_B, CLK_BC, CH_SEL=L, IHOLD=-20µA 1.65 – 3.6 0.75 x VDD_n V VOLA Data Outputs Dn_A, CMD_A, CLK_A, IHOLD=+20µA 1.65 – 3.6 0.25 x VDD_A V Data Outputs Dn_BC, CMD_B, CLK_BC, CH_SEL=H, IHOLD=+20µA 1.65 – 3.6 0.25 x VDD_n V Data Outputs Dn_BC, CMD_B, CLK_BC, CH_SEL=L, IHOLD=+20µA 1.65 – 3.6 0.25 x VDD_n V VILC Low Level Input (6) Voltage VIL VOHA VOHB VOLB High Level Output (6, 7) Voltage Low Level Output (6, 7) Voltage VOLC V FXL3SD206 — Level Shifting Voltage Translator DC Electrical Characteristics Notes: 6. Port B and Port C share the same data and clock pin, and VDD_n refers to VDD_HI or VDD_LO, whichever is selected. During normal operation, VDD_HI must be greater than or equal to VDD_LO. 7. This is the output voltage for static conditions. Dynamic drive specifications are given in “Dynamic Output Electrical Characteristics. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 7 TA=-40°C to 85°C unless otherwise specified. Symbol IIODH IIODL II IOFF IOZ ICC ICCZ Parameter Condition Bushold Input Data Inputs Dn_A, CMD_A, CLK_A Overdrive High Dn_BC, CMD_B, CMD_C, CLK_BC (8) Current VDD_A (V) VDD_n (V) Min. Max. Units 3.6 3.6 450 µA 2.7 2.7 300 µA 1.95 1.95 200 µA 3.6 3.6 -450 µA 2.7 2.7 -300 µA 1.95 1.95 -200 µA 1.65 -3.6 3.6 ±1.0 µA Bushold Input Overdrive Low (9) Current Data Inputs Dn_A, CMD_A, CLK_A Dn_BC, CMD_B, CMD_C, CLK_BC Input Leakage Current Control Inputs OE, CH_SEL, VDD_SEL, VI=VDD_CON or GND Power Off Leakage Current Dn_A, CMD_A, CLK_A; VO=0 to 3.6V 0 3.6 ±2.0 µA Dn_BC, CMD_B, CMD_C, CLK_BC; VO=0 to 3.6V 3.6 0 ±2.0 µA Dn_A, CMD_A, CMD_B, CMD_C, Dn_BC, CLK_A, CLK_BC; VO=0V or 3.6V; OE=VIL 3.6 3.6 ±2.0 µA Dn_A, CMD_A, CLK_BC; VO=0V or (10) 3.6V; OE=Don’t Care 3.6 0 ±2.0 µA Dn_BC, CMD_B, CMD_C, CLK_BC; (10) VO=0V or 3.6V; OE=Don’t Care 0 3.6 ±2.0 µA 1.65 – 3.6 1.65 – 3.6 5.0 µA 0 1.65 – 3.6 2.0 µA 1.65 - 3.6 0 2.0 µA 1.65 – 3.6 1.65 – 3.6 5.0 µA 3-state Output Leakage Quiescent Supply (11, 12) Current VI=VDDI or GND; IO=0 Quiescent Supply (11) Current VI=VDDI or GND; IO=0, OE=VIL FXL3SD206 — Level Shifting Voltage Translator DC Electrical Characteristics (Continued) Notes: 8. An external driver must source at least the specified current to switch LOW-to-HIGH. 9. An external driver must source at least the specified current to switch HIGH-to-LOW. 10. “Don’t care” indicates any valid logic level. 11. VDDI is the VDD associated with the input side. 12. Reflects current per supply, VDD_A or VDD_n. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 8 A Port (Dn_A, CMD_A, CLK_A), B and C Port (CMD_B, CMD_C) Output Load: CL=15pF, RL ≥ 1MΩ (CI/O=10pF). TA=-40°C to 85°C. Symbol VDD=2.8V to 3.6V VDD=2.3V to 2.7V VDD=1.65V to1.95V Parameter Typ. trise Output Rise Time A Port tfall Output Fall Time A Port IOHD IOLD Max. (13) (14) Dynamic Output Current High (13) (14) Dynamic Output Current Low Typ. Max. Typ. Units Max. 3.0 3.5 4.0 ns 3.0 3.5 4.0 ns -14.0 -10.0 -6.2 mA +14.0 +10.0 +6.2 mA B and C Port (Dn_BC, CLK_BC) Output Load: CL=30pF, RL≥ 1MΩ (CI/O=10pF). TA=-40°C to 85°C. Symbol VDD=2.8V to 3.6V VDD=2.3V to 2.7V VDD=1.65V to 1.95V Parameter Typ. trise Output Rise Time B and C (13) Port tfall Output Fall Time B and C Port IOHD IOLD Dynamic Output Current High (14) (13) (14) Dynamic Output Current Low Max. Typ. Max. Typ. Units Max. 3.0 3.5 4.0 ns 3.0 3.5 4.0 ns -22.4 -15.8 -10.0 mA +22.4 +15.8 +10.0 mA FXL3SD206 — Level Shifting Voltage Translator Dynamic Output Electrical Characteristics Notes: 13. See Figure 9. 14. See Figure 10. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 9 VDD_A=2.8V to 3.6V and TA=-40°C to 85°C. Symbol Parameter VDD_n=2.8V to 3.6V VDD_n=2.3V to 2.7V VDD_n=1.65V to 1.95V Min. Max. Min. Max. Min. Max. Units tPLH, tPHL A to B/C 0.2 3.5 0.3 3.9 0.5 5.4 ns B/C to A 0.2 3.5 0.2 3.8 0.3 5.0 ns tPZL, tPZH OE to A OE to B/C 1.7 1.7 1.7 µs tPCH CH_SEL B to C or C to B 1.7 1.7 1.7 µs tskew A, B, C Port 0.5 0.5 1.0 ns (15) VDD_A=2.3V to 2.7V and TA=-40°C to 85°C. Symbol Parameter VDD_n=2.8V to 3.6V VDD_n=2.3V to 2.7V VDD_n=1.65V to 1.95V Min. Max. Min. Max. Min. Max. Units tPLH, tPHL A to B/C 0.2 3.8 0.4 4.5 0.5 5.6 ns B/C to A 0.3 3.9 0.4 4.5 0.5 5.5 ns tPZL, tPZH OE to A OE to B/C 1.7 1.7 1.7 µs tPCH CH_SEL B to C or C to B 1.7 1.7 1.7 µs tskew A, B, C Port 0.5 0.5 1.0 ns (15) FXL3SD206 — Level Shifting Voltage Translator AC Characteristics VDD_A=1.65V to 1.95V and TA=-40°C to 85°C. Symbol Parameter VDD_n=2.8V to 3.6V VDD_n=2.3V to 2.7V VDD_n=1.65V to 1.95V Min. Max. Min. Max. Min. Max. Units tPLH, tPHL A to B/C 0.3 5.0 0.5 5.5 0.8 6.7 ns B/C to A 0.5 5.4 0.5 5.6 0.8 6.7 ns tPZL, tPZH OE to A OE to B/C tPCH CH_SEL B to C or C to B tskew A, B, C Port (15) 1.7 1.7 1.7 µs 1.7 1.7 1.7 µs 1.0 1.0 1.0 ns Note: 15. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port and switching with the same polarity (LOW to HIGH or HIGH to LOW). See Figure 12. Skew is guaranteed, but not tested. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 10 TA=-40°C to 85°C. VDD_A Direction VDD_A=2.8 to 3.6V VDD_A=2.3 to 2.7V VDD_A=1.65 to 1.95V VDD_n=2.8V to 3.6V VDD_n=2.3V to 2.7V VDD_n=1.65V to 1.95V Min. Min. Min. A to B/C 100 100 80 B/C to A 100 100 80 A to B/C 100 100 80 B/C to A 100 100 80 A to B/C 80 80 60 B/C to A 80 80 60 Units Mbps Mbps Mbps Note: 16. Maximum Data Rate is specified in megabits per second. See Figure 11. It is equivalent to two times the fTOGGLE frequency, specified in megahertz. For example, 100Mbps is equivalent to 50MHZ. Capacitance TA=+25°C. Symbol Parameter CIN Input Capacitance Control Pins (OE, VDD_SEL, CH_SEL) CI/O Input/Output Capacitance CPD Power Dissipation Capacitance Conditions Dn_A, CMD_A,CLK_A Dn_BC, CMD_B, CMD_C, CLK_BC © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 Typical Units VDD_CON=GND 4.0 pF VDD_A=VDD_n=3.3V, OE=VDD_A, CH_SEL=VDD_A or GND 5.0 VDD_A=VDD_n=3.3V, VI=0V or VDD, f=10MHZ 6.5 25 FXL3SD206 — Level Shifting Voltage Translator Maximum Data Rate(16) pF pF www.fairchildsemi.com 11 VCC TEST SIGNAL DUT C1 R1 Figure 5. AC Test Circuit Table 2. Table 3. AC Test Conditions Test Input Signal Output Enable Control tPLH, tPHL Data Pulses VI=VDD_CON tPZL 0V LOW to HIGH Switch tPZH VCCI LOW to HIGH Switch AC Load VCCo CL Port A, B, or C Port A, CMD_B, CMD_C RL Dn_BC, CLK_BC Port A, B, or C 1MΩ 1.8V± 0.15V 15pF 30pF 2.5V ± 0.2V 15pF 30pF 1MΩ 2.8V to 3.6V 15pF 30pF 1MΩ DATA IN FXL3SD206 — Level Shifting Voltage Translator Test Diagrams Vmi VCCI GND tpxx tpxx DATA OUT Vmo VCCO Figure 6. Waveform for Inverting and Non-Inverting Functions Notes: 17. Input tR = tF = 2.0ns, 10% to 90%. 18. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 12 VCC_CON Vmi GND tPZL DATA OUT VY VOL Figure 7. 3-State Output Low Enable Time for Low Voltage Logic Notes: 19. Input tR = tF = 2.0ns, 10% to 90%. 20. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only. OUTPUT CONTROL VCC_CON Vmi GND tPZH DATA OUT VOH Vx FXL3SD206 — Level Shifting Voltage Translator OUTPUT CONTROL Figure 8. 3-State Output High Enable Time for Low Voltage Logic Notes: 21. Input tR = tF = 2.0ns, 10% to 90%. 22. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only. Symbol VDD VMI VDDI /2 VMO VDDo /2 VX 0.9 x VDDo VY 0.1 x VDDo © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 13 VOH 80% x VCCO VOUT 20% x VCCO VOL Time IOHD ≈ (CL + CI / O ) × ΔVOUT (20% − 80%) • VCCO = (CL + CI / O ) × Δt t RISE Figure 9. Active Output Rise Time and Dynamic Output Current High VOH tfall 80% x VCCO FXL3SD206 — Level Shifting Voltage Translator trise VOUT 20% x VCCO VOL Time IOHD ≈ (CL + CI / O ) × Figure 10. ΔVOUT (80% − 20%) • VCCO = (CL + CI / O ) × Δt t FALL Active Output Fall Time and Dynamic Output Current Low tW DATA IN VCCI/2 VCCI/2 VCCI GND Maximum Data Rate, f = 1/tW Figure 11. Maximum Data Rate VCCO DATA OUTPUT Vmo Vmo tskew GND tskew VCCO DATA OUTPUT Vmo Vmo GND tskew = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin) Figure 12. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 Output Skew Time www.fairchildsemi.com 14 2.80 2.23 0.66 0.10 C A 2.50 2X 24 B 0.56 19 1 0.40 2.23 PIN #1 IDENT 3.70 3.40 13 7 0.10 C 0.23 2X TOP VIEW RECOMMENDED LAND PATTERN 0.55 MAX. 0.10 C 0.15 SEATING PLANE 0.08 C FXL3SD206 — Level Shifting Voltage Translator Physical Dimensions C 0.05 0.00 SIDE VIEW 7 23X 0.35 0.45 13 0.40 1 0.45 0.55 24 19 BOTTOM VIEW Figure 13. 0.15 24X 0.25 0.10 C A B 0.05 C 24-Pin, Micro-MLP, Quad, .6mm Thick, 2.5mm x 3.4mm Body Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 15 FXL3SD206 — Level Shifting Voltage Translator © 2009 Fairchild Semiconductor Corporation FXL3SD206 • Rev. 1.0.0 www.fairchildsemi.com 16