ST52T301/E301 8-Bit OTP/EPROM DuaLogic MCUs WITH ADC, UART, TIMER, TRIAC & PWM DRIVER ADVANCED DATA SHEET High Speed dedicated structures for Fuzzy Logic (3.5 µs to compute a 4 In x 1 Out rule) Capability to perform simple boolean and arithmetic operations Up to 4 Input, 2 Output ConfigurableVariables for each Fuzzy Algorithm and up to 300 Rules Up to 16 Triangularand TrapezoidalMembership Functions for each Input variable Up to 256 Singleton Membership Functions for all Consequents CLCC44-W Program and Data EPROM: 2 Kbytes 16 general purpose registers available as Register File PLCC44 Working Clock Frequencies: 5, 10 and 20MHz On-Chip Clock Oscillator driven by Quartz Crystal or Ceramic Resonator One external interrupt Standard TTL compatible input CMOS compatible output 4 channel 8 bit Analog to Digital Converter Bandgap reference 2.5V Digital 8 bit I/O port indepedently programmable with handshake signal S e r ial Commu n ic at io n In t erfa ce wit h asynchronous protocol (UART) Programmable Timer with internal Prescaler Internal Power Fuzzy Control to drive external Triac (up to 25mA source, 50 mA sink current) Internal Fuzzy controlled PWM to drive an external power device Software tools and Emulators availability Windowed and One Time Programmable (OTP) Memory parts available for prototyping and production phases 44 pin Plastic (PLCC44) and Ceramic Windowed Leaded Chip Carrier (CLCC44-W) July 1998 Note: (1) Formerly W.A.R.P.3TC 1.1 GENERAL DESCRIPTION ST52E301 (1) and ST52T301 (1) devices are members of the W.A.R.P.family of 8-bit DuaLogic microcontrollers. They are able to perform, in an efficient way, both booleanand fuzzy algorithms, in order to reach the best performances that the two methodologies allow. TheST52E301is the erasableEPROMversion and the ST52T301 is the OTP version. The ST52x301 is completely developed and produced by STMicroelectronics using the reliable high performance CMOSM5E (O.7µm) process. Thanks to Fuzzy Logic, ST52x301 allows to describe a problemusing a linguistic model instead of a mathematicalmodel.In thisway it is very useful and easy to modelize complex system with very high accuracy. The linguistic approach is based on a set of IF-THEN rules, describing the control behaviour, and on Membership Functions associated to input and output variables. Fuzzy Inference is a set of operations which computes the output values according with the truth values of the involved rules. 1/99 ST52T301/E301 Figure 1. ST52x301 Architectural Block Diagram ALU FUZZY CORE SYSTEM REGISTERS CONTROL UNIT REGISTER FILE OSCILLATO R A/D CONVERT ER BAND-GAP REFERENCE SCI PARALLEL I/O PORT The flexible I/O configuration of ST52x301 allows to interface with a wide range of external devices, like D/A converters, power control devices (SCRs, TRIACs) and external sensors. The OTP (One Time Programmable) device is fully compatible with the EPROM windowed version, which may be used to create prototype systems and for the pre-production phases. The Fuzzy Core includes the fuzzifier (ALPHA calculator), the inference unit and the defuzzifier. It allows to manage up to 300 Rules (4 Inputs and 1 Output). The rules could be shared in different fuzzy subroutines that can be activated by user defined conditions. T he I / O c a p ab ilit ie s, de man d ed f rom microcontroller applications, are fulfilled by ST52x301 with 4 Analog Inputs, an asynchronous Peripheral interface (UART) and an 8-bit I/O communicationport in orderto transferdata from/to the on-chip Register File. The voltage reference provides biasing to the analog portion of the internal circuitry. The internal reference is a 2.5V Bandgap reference. The voltage reference can supply up to 0.1 mA of current to power external circuitry. ST52x301 includes an 8-bit sampling Analog to Dig it al (A/ D) Co n ve r te r wit h a 4 a n a lo g 2/99 2kBytes EPROM TRIAC/PWM DRIVE R PROG.TIMER WITH PRESC ALER channel fast multiplexer (32µs c o n ve rs io n time/channel). It is possible to perform operations on data stored in the Register File (16 bytes), allowing to manage new inputs and feedback outputs. The TRIAC/PWM Driver peripheral allows to manage directly power devices, implementing three different operating modes: Burst Mode (i. e.T h e rmal A pp li ca t ion s), Ph a s e A ng le Partialization (i.e. Motors Control by TRIACs) and high frequency PWM controls. A programmable Timer with Internal Prescaler, using both internal or external clock, is available. The microcontroller configuration is stored in the internal EPROM. A p o we rf u l de velo pmen t e nviron me nt , FUZZYSTUDIO 3.0, consisting of a board an d s of twa re t ool s, a ll ow s an easy configuration and use of ST52x301. ST 52 x3 0 1 i s f u l ly s up po r t ed b y FUZZYSTUDIO3.0 so f t wa re t o ols a llowin g to gra ph ic ally d es ig n a project and obtain an optimized microcode. ST52x301 exploits a SGS-THOMSON patented strategy to store the MFs in its internal memory. ST52T301/E301 Figure 2. CLCC44-W Pin Configuration Figure 3. PLCC44 Pin Configuration 3/99 ST52T301/E301 Table 1. PLCC44 and CLCC44-W Pin Configuration PIN NAME 1 not connected TYPE Programming Phase Working Phase - - 2 AVDD Analog VDD Analog VDD 3 AVSS Analog Ground Analog Ground 4 EVDD EPROM Digital Power Supply EPROM Digital Power Supply 5 EVSS EPROM Digital Ground EPROM Digital Ground 6 VPP EPROM Programming Power supply (12V ±5%) EPROM V DD (5V ±10%) 7 VDD Digital Power Supply Digital Power Supply 8 VSS Digital Ground Digital Ground 9 P0 I/O I/O EPROM Data Digital I/O 10 P1 I/O I/O EPROM Data Digital I/O 11 P2 I/O I/O EPROM Data Digital I/O 12 P3 I/O I/O EPROM Data Digital I/O 13 P4 I/O I/O EPROM Data Digital I/O 14 P5 I/O I/O EPROM Data Digital I/O 15 P6 I/O I/O EPROM Data Digital I/O 16 P7 I/O I/O EPROM Data 17 READY O 18 P8 O 19 TEST I 20 MAIN2 I/O 21 MAIN1 I 22 VDD Digital I/O I/O port Handshaking Signal Digital Output (must be set to 0) (must be set to 0) Zero Crossing/Prescaler Output Zero Crossing Digital Power Supply Digital Ground Digital Power Supply Digital Ground 23 VSS 24 TRIACOUT O 25 MODE I Functionment Mode Selector 26 RESET I General Reset General Reset 27 CE/INT I Chip Enable EPROM External Interrupt 28 TIMEROUT O 29 ERES / TRES I EPROM Address Counter Reset External Timer Reset 30 OE / TCTRL I EPROM Output Enable Timer Start/Stop Signal 31 OSCout I/O Oscillator Output Oscillator Output 32 OSCin I Oscillator Input Oscillator Input 33 CADD / TCLK I EPROM Change Address Clock Timer External Clock 34 VSS Digital Ground Digital Ground Digital Power Supply Digital Power Supply Triac/PWM Driver Output Pulses Functionment Mode Selector Output Timer 35 VDD 36 TxD O 37 RxD I 38 not connected - - 39 not connected - - 40 AIN3 Ainp Analog Input 41 AIN2 Ainp Analog Input 42 AIN1 Ainp Analog Input 43 AIN0 Ainp Analog Input 44 BG Aout Band Gap Output 4/99 SCI Output SCI Input ST52T301/E301 1.2 PIN DESCRIPTION VDD, EVDD, VSS, EVSS, AVDD, AVSS, VPP. In order to avoid noise disturbances, the power supply of the digital part is kept separated from the power supply of the analog part. VDD. Main Power Supply Voltage (5V 10%). VSS. Digital circuit Ground. EVDD. EPROM Main Power Supply Voltage (5V 10%). EVSS. EPROM Digital circuit Ground. AVDD. Analog VDD of the Analog to Digital Converter. AVSS.AnalogVSS of theAnalogto DigitalConverter. Must be tied to VSS. VPP. Main Power Supply for the internal EPROM (12.5V 5%). OSCin and OSCout. These pins are internally connected with the on-chip oscillator circuit. A quar tz crystal or a ceramic resonator can be connectedbetween these two pins in order to allow the correct operations of ST52x301 with various stability/cost trade-offs. An external clock signal can be applied to OSCin, in this case OSCout must be grounded. RESET. This signal is used to restart ST52x301 at the beginningof its program.It also allows to select the program mode for the EPROM. INT. External interrupt active on rising or falling edge. AIN0-AIN3. These 4 lines are connected to the inputs of the analog multiplexer. They allow to acquire 4 analog inputs. BG. A Voltageequal to 2.5V is available on this pin. It can be used for Analog signal conditioning. P0-P7. These 8 lines are organizedas one I/O port. During the Programming phase such port is used for the EPROM data read/write. READY. Handshake signal of the parallel port. P8. Digital output. TxD. Serial data output of the SCI transmitter block. RxD. Serial data input of the SCI receiver block. TRES, TCLK, TCTRL, TIMEROUT. These pins are related with the internal Programmable Timer. The Timer can be reset externally by using TRES. In Working Mode, TRES resets the address counter of the Timer. TRES is active at low level The Timer Clock can be the internal clock or can be supplied externally by using the pin TCLK. An external Start/Stopsignal can be used to control the Timer throughthe pin TCTRL.The Timeroutput is available on the pin TIMEROUT. MAIN1, MAIN2, TRIACOUT. ST52x301 is able to drive a TRIAC in two different modes: Burst mode or Phase Angle Partialization control mode. The Burst mode is used for thermal regulation. MAIN1 and MAIN2 signals are used to detect the zero crossing of the main voltage. Thepulse to drivethe TRIACis givenby TRIACOUT pin. It is possible to use the same pins to implement a PWM Driver. In this case it is possible to fix the period of PWM and to changethe duty cycle on fly. The PWM output is given by TRIACOUT pin. CE, OE, ERES, CADD, VPP. These pins are used to manage the EPROM during the Programming p ha s e . Dur in g t h e P ro g ra mming ph a se (programming) VPP must be set at 12V. In the Working phase VPP must be equal to VDD. ERES in Programming Mode resets the address counter of the EPROM; it is active at high level. In the Working phase OE, CE and CADD are used like handshaking signals for the parallel port. MODE. I t s elec ts t h e fun ct ion ment mo d e (Programming or Working mode). TEST. It enables the testing functionalities; during the Programming and Working phaseit must be set to 0. 5/99 ST52T301/E301 2.1 CONTROL UNIT The Control Unit (CU) manages: Registers File, Input Registers, Configuration Registers, ALU, Accumulator and Multiplexer inputs. Moreover the CU drives the Fuzzy Core and the peripherals (Triac/PWM Driver and Timer). The CU reads the stored instructions on the EPROM (Fetch) and decodifies them. If the instructions are arithmetic or logic, the CU runs them directly, sending the control signals to the related blocks. If there is a STOP instruction, the CU transfers the control to the Fuzzy Core. The Fuzzy Core (FC) will read the next instruction (that must be a fuzzy instruction)from the EPROM. The FC mantains the control of the program until the next STOP instruction. Then the FC transfers the control to the CU. These characteristicsallow to mix fuzzy algorithms with mathematical and logic instructions. Figure 2.1 shows a flow-chart reasuming the logic behaviour of the instructions management. 2 INTERNAL ARCHITECTURE ST52x301 is made up by the following blocks and peripherals: Control Unit Fuzzy Core ALU EPROM Clock Oscillator Analog Multiplexer and A/D Converter Prescaler Timer Bandgap Triac / PWM Driver Digital I/O port Serial Communication Interface ST52x301 Operating Modes ST52x301 works in two modes, Programming and Working Modes, depending on the control signals level RESET, TEST and MODE. The Operating modes are selected by setting the control signal level as specified in the Control Signals Setting table. Table 2.1. Control Signals setting Control Signal Programming Reset Working RESET 0 0 1 TEST 0 0 0 MODE 1 0 0 Figure 2.1. Computation Algorithm Flow Chart CU Reads fromthe EPROM and Decodifies the instruction STOP? No CU executes instruction Yes Fuzzy Core Reads fromthe EPROM and Decodifies the instruction Yes 6/99 STOP? No Fuzzy Core executes instruction ST52T301/E301 Figure 2.2. ST52x301 Block Diagram TxD RxD MAIN1 SCI (UART) TRIAC/PWM MAIN2 DRIVER TRIACOUT P0..P7 P8 I/O PARALLEL PORT READY TCTRL AIN0..AIN3 8 BIT A/D CONVERTER TRES TIMER TCLK EPROM 2 KBytes TIMEROUT CONTROL UNIT Peripheral Register PERIPH_REG_0 PC PERIPH_REG_1 FL AGS ALU PERIPH_REG_2 Input Registers ADC_OUT_0 ADC_OUT_1 ADC_OUT_2 ADC_OUT_3 TMR_OUT TMR_ADC_ST INP_PORT SCI_IN SCI_ST FUZZY_OUT_0 FUZZY_OUT_1 Register File Reg 0 Reg 1 FUZZY CORE Reg 15 Configuration Registers REG_CONF0 REG_CONF1 REG_CONF15 POW ER SUPPLY VDD VPP VSS OSCILLATOR OSCin OSCout RESET RESET 7/99 ST52T301/E301 It is not possibile to stop the fuzzy inference before the end of the defuzzificationof one output.Aset of 26 different arithmetic and logic instructions is available.Each instruction requiresfrom4 to7 clock pulses to be performed. 2.1.1 Program Counter The Program Counter (PC) is a 11-bit register that contains the address of the next memory location to be processed by the core.This memory location may be an opcode,an operand or an address of an operand. The 11-bit length allows the direct addressing mode of 2048 bytes in the program space. After having read the current instruction address, the PC value is incremented. To execute relative jumps the PC and the offset are shiftedthrough the Fuzzy Core or the ALU, where they will be added. The result of this operation is shifted back into the PC. The PC can be changed in the following ways: JP (Jump) instruction PC = Jump Address Interrupt PC = Interrupt Vector RETI instruction PC = Pop (stack) Reset PC = Reset Vector Normal Instruction PC = PC + 1 2.1.2 Flags The ST52x301 core includes two pairs of flags that correspond to 2 different modes: normal mode and interrupt mode. Each pair consist of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during normal operation and one is used during the interrupt mode (CI, ZI). The ST52x301 core uses the pair of flags that correspond to the actual mode: as soon as an interrupt is generated,the ST52x301 core uses the interrupt flagsinstead of the normal flags.When the RETI instruction is executed the normal flags are restored if the MCU was in the normal mode before the interrupt. It should be observed that each flag set can only be addressed in its own routine. The flags are not cleared during the context switching and remain in the state they were at the exit of the last routine switching. 8/99 The Carry flag is set when a carry or a borrow occurs during arithmetic operations, otherwise it is cleared. The switching between the two sets of flags is automatically performed when an interrupt or a RETI instruction occur. 2.2 ADDRESS SPACES W.A.R.P3TC has four separate address spaces: Register File: 16 8-bit registers Input Registers:11 8-bit registers Configuration Registers: 16 8-bit registers Peripheral Registers: 3 8-bit registers Program memory up to 2K Bytes The Program memory will be described in further detail in the MEMORYsection 2.2.1 Register File The Register File (RF) consists of 16 general purpose 8-bit registers Reg0 to Reg15. All the registers in the RF can be specifiedby using a decimal address, e.g. 0 identify the first register of the RF, called Reg0. Reg0:3 are directly connected to the FC input. It means that the input values of the fuzzy algorithm must be loaded into these registers by the user. These registers are used as temporary registers during the macros’ computation. ST52T301/E301 Figure 2.3. Address Spaces description CORE O N -C H IP P E RIP H E R A L S P ro gra m M e m o ry C o n fig u ra tio n R e g isters LDC F In p u t R e gis te rs AL U P E R IP H E R A L B L OC K P e rip h er al R e g isters F U Z ZY R e g ister F ile C OR E LD R I LDP R LD R C LD R R (1 ) L D C F C R i, x Figure 2.4. Register File description Register File Register Description Reg0 Reg1 FUZZY_IN_0 FUZZY_IN_1 Reg2 FUZZY_IN_2 Reg3 Reg4 FUZZY_IN_3 Fuzzy Core Free Reg5 Reg6 Free Free Reg7 Reg8 Free Free Reg9 Reg10 Free Free Reg11 Reg12 Reg13 Free Free Free Reg14 Reg15 Free Free 9/99 ST52T301/E301 2.2.2 Input Registers Bench The Input Registers (IR) bench consists of 11 8-bit registers co ntaining data or status of t he peripherals. All the registers can be specifiedby using a decimal address, e.g. 0 identifies the first register of the IR. The first four registers (ADC_OUT_0:3) of the IR are dedicated to the 4 converted values coming from the ADC. TMR_OUT registers contains the current counted value by the internal Timer; whereas TMR_ST is Figure 2.5. Input Registers Bench description 10/99 the Timer status. For details about TMR_ST, please refer to Timer description. Data read by the Parallel I/O Port are stored automatically in the 6-th register, INP_PORT. Data read by the SCI are stored automatically in the 7-th register SCI_IN and SCI status is stored in the SCI_ST register. For details about SCI_ST, please refer to SCI description. The Fuzzy Core writes the computed output values in the FUZZY_OUT_0:1 registers. ST52T301/E301 Figure 2.6. TMR_ADC_ST Registers Figure 2.7. SCI_ST Registers 11/99 ST52T301/E301 2.2.3 Configuration Registers The ST52x301 setting permits to configure all blocks.Table 2.2 describesthe relatedblock to each bit of the Configuration Registers. Use and meaning of each register will be described in further details in the corresponding section. Table 2.2. Configuration Registers description Register Peripheral Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG_CONF0 PARALLEL PORT IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 REG_CONF1 SCI, CORE, I/O PORT RDRF OVR BRK TDRE TXC REG_CONF2 ADC REG_CONF3 SCI REG_CONF4 TIMER TMLSB REG_CONF5 TIMER TMMSB REG_CONF6 TIMER REG_CONF7 TIMER REG_CONF8 TRIAC TCLSB REG_CONF9 TRIAC TCMSB REG_CONF10 TRIAC REG_CONF11 TRIAC REG_CONF12 TRIAC REG_CONF13 TRIAC REG_CONF14 INTERRUPT REG_CONF15 INTERRUPT 12/99 not used BRSL not used POL TMS PSF FZSL 1 ADRST M RE TE CKSL TMEL IESL TMST TMRST FZSL INPSL INTR INTF INTSL TCST TCRST TCTRS POL MSKAD MSKE CKSL INTSL P8 OUT IADD T8 not used IOSL ECKF MODE TCMSK INPSL UTPMSB UTPLSB EXTI not used INT4 MSKTC INT3 MSKTM MSKSCI INT2 INT1 ST52T301/E301 2.2.4 Peripheral Registers Periph eral Registers contain the initialization values for the Timer, Triac/PWM Driver and Parallel Port. The peripheral initialization value is kept from a location of the Register File, by using a LDPR instruction, or from FUZZY_OUT_0/1 Input Register according with the related Configuration Registers. Table 2.3 describes the related peripheral to each Configuration Register. Use and meaning of each register will be described in further details in the corresponding section. Table 2.3. Peripheral Register description Peripheral Register Peripheral PERIPH_REG_0 Timer PERIPH_REG_1 Triac/PWM Driver PERIPH_REG_2 Parallel Port 13/99 ST52T301/E301 2.4 FUZZY CORE Figure 2.8. Alpha Weigth calculation ST52x301 Fuzzy Core main features are: Up to 4 Inputs with 8-bit resolution Up to 16 Membership Functions (Mbfs) for each Input (64 possible Mbfs) j-th Mbf 1 Up to 2 Outputs with 8-bit resolution Possibility to process fuzzy rules with a max. number of 8 antecedents 2.4.1 Internal Structure The block diagram shown in figure 2.9 describes the structure of ST52x301Fuzzy Core.In this figure we can distinguishdifferentfunctionalblocks:Alpha Calculator, Inference Unit and Defuzzifier. These blocks allow to perform a MAMDANI type fuzzy inference with crisp consequents.It is important to underline that the fuzzy inference is performed by using as inputs the first 4 locationsof the Registers File. 2.4.2 Alpha Calculator Unit This block performs the intersection (alpha weight) between the input values and the related Mbfs (fig. 2.8). Figure 2.9. Fuzzy Core Block Diagram 14/99 αij i-th INPUT VARIABLE Input Value Notice that the inputs for this block come from the first four locations of the Register File; it means the user, to evaluate a fuzzy function, must load the input values in these registers. Alpha Calculato r pe rforms what is called fuzzification: the input data are transformed in activation level (alpha weight) of the Mbfs. ST52T301/E301 2.4.3 Inference Unit It managesthe alphaweights obtainedby the Alpha Calculator Unit to compute the truth value ( ω ) for each rule. This is a calculation of the maximum (for the OR operator) and/or minimum (for the AND operator) performed on alpha values according to the logical connectives of fuzzy rules. It is possibile to link together up to eight conditions by linguistic connectives AND/OR, NOT operator and brackets. Each rule can have at maximum 8 alpha weights (however they are connected). The truth value ω and the related output singleton are passed to the Defuzzifier to complete the inference calculation. Figure 2.11. j-th Singleton 1 ωij ωi0 ωin 0 Xi0 Xij Xin i-th OUTPUT VARIABLE Figure 2.10. IF INPUT 1 IS X1 OR INPUT 2 IS X2 THEN ....... α1 α2 X1 X2 Input 1 Input 2 OR = Max 2.4.4 Defuzzifier This block consists of a Multiplier, two Adders and one Divider. It generates the output crisp values implementing the consequent part of the rules. In this phase each consequent Singleton Xi is multiplied by its weight values ωi, calculated by the Inference Unit in order to compute the upper part of the defuzzification. Each output value (FUZZY_OUT0, FUZZY_OUT1) is deduced from the consequent crisp values (Xi) by using the defuzzification formula: N IF INPUT 1 IS X1 AND INPUT 2 IS X2 THEN ....... Yi = α1 α2 X1 Input 1 ∑Xij ωij j N X2 Input 2 ∑ωij j where: i = 0,1 identifies the current output variable N = number of the active rules on the current output ωij =weigth of the j-th singleton Xij = abscissa of the j-th singleton The two fuzzy outputs are stored in the location 9 and 10 of the Input Registers (FUZZY_OUT_0, FUZZY_OUT_1). 15/99 ST52T301/E301 2.4.5 Input Membership Function The Mbf is memorized by using the following instruction: ST52x301 allows to manage triangular Mbfs. In order to define a Mbf it is necessary to store three different data on the memory: the vertex of the Mbf: V; the lenght of the left semi-base: LVD; the lenght of the right semi-base: RVD; In order to reduce the dimension of the memory area and the computational effort the vertical dimension of the vertex is fixed to 15 (4 bits) By using the previous memorization method it is possible to store different kinds of triangular Memberships Functions. In the following figure is shown a typical example of Mbfs that can be defined in ST52x301 Each Mbf is then defined storing 3 bytes. To store all the information related with the fuzzy project Mbfs, it is necessary to use 192 bytes of the memory (3 bytes*16 Mbfs*4 Inputs = 192 bytes). DATA n m lvd v rvd where n identifies the input, m identifies the Mbf among the 16 possibleMbfs, lvd, v, rvd are the parameters describing the Mbf’s shape. 2.4.6 Output Singleton ST52x301uses for the output variables a particular kind of membership function called Singleton. A Singleton has not a shape, like a traditional Mbf, and it is characterized by a single point identified by the couple (X, ω), where the ω is calculated by the Inference Unit as described before. Often a Singleton is simply identified with its Crisp Value X. Figure 2.12. Mbfs Parameters Figure 2.13. Example of valid Mbfs 15 0 Input Mbf V LVD Output Singleton 15 w 0 16/99 Input Variable RVD X Output Variable ST52T301/E301 2.4.7 Fuzzy Rules. The rules can have the following structures: if A op B op C...........thenZ if (A op B) op ( C op D op E...) ...........thenZ where op is one of the possible linguistic operators (AND/OR) In the first case the rule operators are managed sequentially; in the second one, the priority of the operator is fixed by the brakets. Each rule is codified by using an istruction set, the inference time for a rule with 4 antecedents and 1 consequent is about 3 microseconds. The assembler Instruction Set allowing to manage the fuzzy instructions are reported in the following table: Table 2.4. Fuzzy Instructions Set Instruction Description DATA n m lvd v rvd Stores the Mbf m of the input n with the shape identified by the parameters lvd, v and rvd. LDP n m Fixes the alpha value of the input n with the Mbf m and stores it in the data stack. LDN n m Calculates the negated alpha value of the input n with the Mbf m and store the result in the data stack. FZAND Implements the fuzzy operation AND between the last two values stored in the data stack. FZOR Implements the fuzzy operation OR between the last two values stored in the data stack. LDK Stores the result of the last fuzzy operation executed in the data stack. SKM Stores the result of the last fuzzy operation executed in the memory register M. LDM Copies the value of the register M in the data stack. CON crisp Multiplies the crisp value with the last ω weight. OUT n_out Performs the defuzzification. STOP Ends the fuzzy algorithm. 17/99 ST52T301/E301 Example 1: IF Input1 IS NOT Mbf1 AND Input4 is Mbf12 OR Input3 IS Mbf8 THEN Crisp1 is codified by the following instructions LDN 1 1 calculates the NOT α value of Input1 with Mbf1 and stores the result in the data stack LDP 4 12 fixes the α value of Input4 with M12 and stores the result in the data stack FZAND adds the NOT α and α values obtained with the operations LDN1 1 and LDP 4 12 LDK stores the result of the operation FZAND in the data stack LDP 3 8 fixes the α value of Input3 with Mbf8 and stores the result in the data stack FZOR implements the operation OR between the results obtained with the operations LDK and LDP CON crisp1 multiplies the result of the last Ω operation with the crisp value Crisp1 Example 2, the priority of the operator is fixed by the brakets: IF (Input3 IS Mbf1 AND Input4 IS NOT Mbf15) OR (Input1 IS Mbf6 OR Input6IS NOT Mbf14) THEN Crisp2 LDP 3 1 LDN 4 15 FZAND SKM LDP 1 6 LDN 2 14 FZOR LDK LDM FZOR CON crips2 fixes the α value of Input3 with Mbf1 and stores the result in the data stack calculates the NOT α value of Input4 with Mbf15 and stores the result in the data stack adds NOT α and α values obtained with the operations LDP 3 1 and LDN 4 15 stores the result of the operation FZAND in the memory register M fixes the α value of Input1 with Mbf6 and stores the result in the data stack calculates the NOT α value of Input6 with Mbf14 and stores the result in the data stack implements the operation OR between the α and NOT α values obtained with the two previous operations (LDP 1 6 and LDN 2 14) stores the result of the operation OR in the data stack copies the value of the memory register M in the data stack implements the operation OR between the last two values stored in the data stack (LDK and LDM) multiplies the result of the last Ω operation with the crisp value Crip2 At the end of the fuzzy rules set a byte, to identify the output involved in the rules, and the STOP istruction must be inserted. When the STOP instruction is performed, the control of the algorithm goes back to the CU. 18/99 ST52T301/E301 2.5 ARITHMETIC LOGIC UNIT The 8-bit Arithmetic Logic Unit (ALU) allows to perfo rm arit hme tic calcu la tions and logic instructions which can be divided into 4 groups: Load, Arithmetic, Jump and Program Control instructions (refer to the ST52x301 Assembler Set for further details ). The computation al time required for each instruction consists of one clock pulse for each Cycle plus 3 clock pulses for the decoding phase. Table 2.5. Arithmetic & Logic Instructions Set Load Instructions Menmonic Instruction Bytes Cycles Z S LDCF LDCF conf, const 2 6 - - LDRC LDRC reg, const 2 6 - - LDRI LDRI reg, inp 2 6 - - LDPR LDPR per, reg 1 6 - - LDRR LDRR regi, regj 2 6 - - Mnemonic Instruction Bytes Cycles Z S ADD ADD regi, regj 2 7 I I AND AND regi, regj 2 7 I - SUB SUB regi, regj 2 7 I I SUBO SUBO regi, regj 2 7 I I Mnemonic Instruction Bytes Cycles Z S Arithmetic Instructions Jump Instructions JP JP addr 2 6 - - JPNS JPNS addr 2 6 - - JPNZ JPNZ addr 2 6 - - JPS JPS addr 2 6 - - JPZ JPZ addr 2 6 - - Mnemonic Instruction Bytes Cycles Z S SRX SRX regi 2 5 - - STX STX regi 2 5 - - SCI Instructions Notes: I affected - not affected 19/99 ST52T301/E301 Table 2.6. Arithmetic & Logic Instructions Set (Continue) Program Control Instructions Mnemonic Instruction Bytes Cycles Z S RETI RETI 1 5 I I RINT RINT int 1 4 - - STOP STOP 1 4 - - WAITI WAITI 1 4 - - UDGI UDGI 1 4 - - UEGI UEGI 1 4 - - MDGI MDGI 1 4 - - MEGI MEGI 1 4 - - IRQ IRQ int label 2 6 - - IRQM IRQM mask 2 6 - - IRQP IRQP cost 2 6 - - Notes: I affected - not affected 20/99 ST52T301/E301 3 EPROM The EPRO M memory provides an on-chip user-programmable non-volatile memory, that allows fast and reliable storage of user data. There are 16K bits of memory space with an 8-bit internal parallelism (2Kbytes) addressed by an 11-bit bus. The data bus is of 8 bits. The memory has a double supply: VPP is equal to 12V±5% in Programming Phase and 5V±10% during Working Phase.VDD is equal to 5V±10%. The EPROM memory of ST52x301 is divided in three main blocks (see Figure 3.1): Mbfs Setting with (0 through 191) contains the coordinates of the vertexes of every Mbf defined in the program. Interrupt Vectors (192 through 201) contain the addresses for the interrupt routines. Each address is composed of two bytes. Program Instruction Set (202 through 2048) contains the instruction set of the user program. It can be composed of more Boolean and Fuzzy Algorithms The operation that can be performed, during Programming Phase, on the EPROM are: Writing, Verify, Writing Inhibit, Standby and Erasing. Fig u re 3 . 2 s h ows t h e s ign a ls t imin g in Programming Mode. 3.1 EPROM Programming Phase Procedure Programming mode is selected by applying 12V±5% voltage to the VPP pin and set the control signal as following: RESET: 0, TEST: 0, MODE: 1. CADD, ERES, OE and CE are the control signals used during the Programming Mode. CADD is active on edge, the others are active on level (OE, CE are active low, ERES is active high). 3.1.1 EPROM Writing When the memory is blank, all the bits are at logic level ”1”. The data are introduced by programming only the zeros in the desired memory location; however all input data must contain both ”1” and ”0”. The only way to change ”0” into ”1” is to erase the whole memory ( by exposure to Ultra Violet light) and reprogram it. The memory is in Writing mode when: CE = LOW OE = HIGH with stable data on the data bus P(0:7). The total programming pulse width (CE = 0 V) is, typically, 50 µs (by means of 5 pulses of 10 µs), but beforeactivating such pulse, it is suggested to wait for at least 2 µs after VPP rises at 12 V . After the disactivation of the pulse it is suggested to wait for Figure 3.1. Memory Map 2048 Fuzzy Algorithm Boolean Algorithm · ··· ·· Program InstructionsSet Fuzzy Algorithm Boolean Algorithm 202 201 192 191 INT_EXT INT_TRIAC INT_TIMER INT_SCI INT_ADC Mbf Parameters Interrupt Vectors Mbfs Setting 0 21/99 ST52T301/E301 at least 2 µs before updating the data and the address. The data updating for the next programming is performed, directly by the user, on the data bus P(0:7) while the address is incremented through the pin CADD. 3.1.2 EPROM Verify A Verify mode is available in order to verify the correctness of the data written. It is possible to activate the Verify mode immediately after the writing of each byte: CE = HIGH OE = LOW Then, if any error in writing occured, the user has to repeat the EPROM writing. The data, during this phase, are avalaible on the bus P(0:7) 3.1.3 Writing Inhibit It occurs between the Writing and Verify Mode: CE = HIGH OE = HIGH 3.1.4 Standby Mode The EPROM has a standby mode which reduces the active current from 10mA (Programming mode) to less than 100 µA. The Memory is placed in standby mode by setting CE at HIGH Logic Level (VPP might be equal to 5 V too). When in standby mode, the outputs are in high impedance state. 3.2 Eprom Erasure Thanks to the transparent window present in the CLCC44-W package, its memory contents may be erased by exposure to UV light. Erasure begins when the device is exposed to light with a wavelengthshorter than 4000Å.It should be noted that sunlight, as well as some types of artificial light, includes wavelengths in the 3000-4000Å range which, on prolonged exposure, can cause erasure of memory contents. It is thus recommended that EPROM devices be fitted with an opaque label over the window area in order to prevent unintentional erasure. The recommended erasure procedure for EPROM devices consists of exposureto short wave UV light having a wavelength of 2537Å. The minimum recommended integrated dose (int ensity x exp o-su re t ime) f or co mplet e era su re is 15Wsec/cm 2 . This is equivalent to an erasure time of 15-20 minutes using a UV source having an intensity of 12mW/cm 2 at a distance of 25mm (1 inch) from the device window. Figure 3.2. EPROM Programming Timing Writing P(0:7) Verify DATA IN INPUT PORT 50us typ. CE 3us min. OE CADD ERES RESET 12V VPP 5V 22/99 Inhibit DATA OUT 2us typ. OUTPUT PORT min 2us ST52T301/E301 4 INTERRUPTS The Control Unit (CU) responds to peripheral events and external events through its interrupt channels. When such an event occurs, if it is not maskedand according to a priority order, the current program execution can be suspended to allow the CU to execute a specific response routine. Each interrupt is associated with an interrupt vector that contains the memory address of the related interrupt service routine. Each vector is located in the Program Space (EPROM Memory) at a fixed address (see Interrupt Vectors table fig. 4.2). 4.1 Interrupt Functionment If, at the end of an arithmetic or logic instruction, there are pending interrupts, the one with the highest priority is passed. To pass an interrupt means to store the arithmetic flags and the current PC in the stack and execute the associated Interrupt routine, whose address is located in one of the EPROM memory location between address 192 and 201. The Interruptroutine is performedas a normal code checking, at the end of each instruction, if a higher priority interrupt has to be passed. An Interrupt request with the higher priority stops the lower priority Interrupt. The Program Counter and the arithmetic flags are stored in the stack. With the instruction RETI (Return from Interrupt) the arithmetic flags and Program Counter (PC) are restored from the top of the stack.This stack, used for the Interrupt priority, is a LIFO queue. An Interrupt request cannot stop the processing of the fuzzy rules but this is passed only after the definitionof the fuzzy output or at the end of a logic or arithmetic instruction. 4.2 Global Interrupt Request Enabling When an Interrupt occurs, it generates a Global Interrupt Pending (GIP), that can be hanged up by software. After a GIP a Global Interrupt Request (GIR) will be generate and Interrupt Service Routine associated to the interrupt with higher priority will start. In order to avoid possible conflicts between interrupt masking set in the main program or inside macros, the GIP is hanged up through the User Global Interrup Mask or the Macro Global Interrup Mask (see fig.4.3). UEGI/UDGI instruction switches on/off the User GlobalInterrup Mask enabling/disablingthe GIR for the main program. MEGI/MDGI instructions set the Macro Global Interrupt Mask in order to assure that the macro will not be broken. Figure 4.1. Interrupt Flow NORMAL PROGRAM FLOW INTERRUPT SERVICE ROUTINE INTERRUPT RETI INSTRUCTION Figure 4.2. Interrupt Vectors Mapping 202 201 200 199 198 197 196 195 194 193 192 191 INT_EXT INT_TRIAC INT_TIMER Interrupt Vectors INT_SCI INT_ADC Figure 4.3. Global Interrupt Request generation Global Interrupt Pending Global Interrupt Request User Global Interrupt Mask Macro Global Interrupt Mask 23/99 ST52T301/E301 4.3 Interrupt Sources Table 4.1. Configuration Register 14 Description ST52x301manages interrupt signals generated by the internal peripherals (Timer, Triac/PWM Driver,Analog to Digital Converter and Serial Communication Port) or coming from the INT pin. Th e p o la rit y of t he Ext ern al I nt erru pt is programmed by the EXTI bit of the REG_CONF14 (see Table 4.1 and fig. 4.4). EXTI=0 means that INT_EXT is active on rising edge, otherwise it is active on falling edge. Each peripheral can be programmed in order to generate the associate interrupt;further detailsare described in the related chapter. Bit Name 0 1 Value 2 For example LDCF 14, 6 (CONF_REG14 =00000110) enables interrupts coming from the ADC (INT_ADC) and from the SCI (INT_SCI). 3 Level 5 is associated to the Main Program, levels 4 to 1 are programmable by means of the priority register called REG_CONF15 (see fig.4.5); whereas the higher level is related to the external interrupt (INT_EXT). Timer, Triac/PWM Driver, SCI and ADC are identified by a two bits Peripheral Code (see Table 4.2); in order to set the i-th priority level the user must write the peripheral label i in the related INTi priority level. 4 External Interrupt Masked 1 External Interrupt Not Masked 0 A/D Converter Interrupt Masked 1 A/D Converter Interrupt Not Masked 0 SCI Interrupt Masked 1 SCI Interrupt Not Masked 0 TIMER Interrupt Masked 1 TIMER Interrupt Not Masked 0 TRIAC/ PWM Interrupt Masked 1 TRIAC/ PWM Interrupt Not Masked MSKAD MSKSCI MSKTM 4.5 Interrupt Priority Six priority levels are available: level 5 has the lowest priority, level 0 has the highest priority. 0 MSKE 4.4 Interrupt Maskability The interrupts can be masked by configuring the REG_CONF14. The interrupt is enabled when the bit associated to the mask interrupt is ”1”. Viceversa, when the bit is ”0”, the interrupt is masked and is kept pendent. Description MSKTC 5 not used - 6 not used - 7 EXTI 0 Active on Rising Edge 1 Active on Falling Edge Table 4.2. Interrupts Description Name Description Priority Peripheral Code Maskable EPROM Locations INT_EXT External Interrupt (INT) Ext Highest - yes 200-201 INT_ADC ADC Int Programmable 00 yes 192-193 INT_SCI SCI Int Programmable 01 yes 194-195 INT_TIMER TIMER Int Programmable 10 yes 196-197 INT_TRIAC TRIAC Int Programmable 11 yes 198-199 24/99 ST52T301/E301 Figure 4.4. Interrupt Configuration Register 14 REG_CONF14 Interrupt D7 D6 D5 D4 D3 D2 D1 D0 MSKE - External Interrupt Mask MSKAD - ADC Interrupt Mask MSKSCI - SCI Interrupt Mask MSKTM - TIMER Interrupt Mask MSKTC - TRIAC Interrupt Mask not used not used EXTI - External Interrupt Polarity Figure 4.5. Interrupt Configuration Register 15 REG_CONF15 Interrupt D7 D6 D5 D4 D3 D2 D1 D0 INT1 - HIGH Level Interrupt INT2 - MEDIUM-HIGH Level Interrupt INT3 - MEDIUM-LOW Level Interrupt INT4 - LOW Level Interrupt 25/99 ST52T301/E301 i.e. LDCF 15, 201 (REG_CONF15=11001001) define the following priority levels: Level 1: INT_SCI(SCI Code: 01) Level 2: INT_TIMER(TIMER Code: 10) Level 3: INT_ADC(ADC Code: 00) Level 4: INT_TRIAC(TRIAC Code: 11) When a source provides an Interrupt request, and the request processing is also enabled, the CU changes the normal sequential flow of a program by transfering programcontrol to a selectedservice routine. Whenan interrupt occurs the CU executes a JUMP instruction to the address loaded in the related location of the Interrupt Vector Table 4.3. Configuration Register 15 Description Bit Name Value 0, 1 INT1 Peripheral Code High 2, 3 INT2 Peripheral Code Medium-High 4, 5 INT3 Peripheral Code Medium-Low 6, 7 INT4 Peripheral Code Low Whenthe executionreturns to the original program, it begins immediately following the interrupted instruction. 4.6 Interrupt RESET An eventually pending interrupts can be reset with the instruction RINT inti which resets the i-th interrupt Figure 4.6. Example of a Sequence of Interrupt Requests 26/99 Level ST52T301/E301 5 CLOCK ST52x301 can work by using a 5, 10 or 20 MHz clock. The ST52x301 Clock Generator module generates the internal clock for the internal Control Unit, ALU, Fuzzy Core and on-chip peripherals and it is designed to require a minimum of external components. The system clock may be generatedby using either a qua rtz cr ystal, or a cera mic res onat or (CERALOC); or, at least, by means of an external clock. The different clock generator options connection methods are shown in Figure 5.1. When an external clock is used, it must be connectedon the pin OSCin while OSCout must be grounded. The crystal oscillator start-up time is a function of manyvariables:crystal parameters(especially RS), oscillator load capacitance (CL), IC parameters, ambient temperature, supply voltage. It must be observed that the crystal or ceramic leads and circuit connections must be as short as possible. Typical values for CL1, CL2 are 10pF for a 20 MHz crystal. Figure 5.1. Oscillator Connections 27/99 ST52T301/E301 6. A/D CONVERTER The A/D Converter of ST52x301 is an 8-bit analog to digital converter with up to 4 analog inputs offering 8 bit resolution with a total accuracy of 2 LSB and a typical conversion time of 32 µs. The conversion range is 0 - 2.5 V. The A/D peripheral converts the input voltage with a process of successive approximations using a fixed clock frequency derived from the oscillator. The ADC uses 5 registers: one Configuration Register, REG_CONF2, and four Data Registers. These 4 registers are the first 4 Input Registers. The A/D converter drives the analog Multiplexer in order to sequentially pick up the external inputs to be put in output and stored automatically in 4 8-bit registers. The A/D Converter, at the end of the conversion, will send a signal (end-of-conversion)which can be used like an interrupt signal. The user can select the priority of the A/D interrupt and mask it (see ”Interrupt Routine” chapter) Th e co nve rs io n s ta r t s writ ing ”1” on REG_CONF2(0). The A/D is reset by writing ”0” in REG_CONF2(0). The converted data are automaticallystored in four 8-bit Input Registers. By performing an instruction: LDRI regj ingi the analog input ”ingi” is loadedin theregister”regj” of the Register File. Table 6.1. It is possibile to configurethe Multiplexer by means of the register REG_CONF2, in order to select the number of analog inputs to convert. CONF_REG2 (3:2) 00 Ain0 For example, if the bit 3 and bit 2 of REG_CONF2 are configured at 10, then the Multiplexer will sequentially pick up only the inputs 0,1 and 2. 01 Ain 0, Ain1 10 Ain 0, Ain 1, Ain 2 11 Ain 0, Ain 1, Ain 2, Ain 3 Table 6.1 shows the convertion sequences according to the possible values of the two bit REG_CONF2 (3:2). Figure 6.1. A/D Converter Structure 28/99 INPUT SEQUENCE ST52T301/E301 The power consumption of the device can be reduced by turning off the A/D converter, To switch off the A/D converter the CONF_REG2(0) bit must be reset to ”0”. The A/D Converter features a sample and hold. The input voltage Ain, which has to be converted must be constant, for 12.8 µs. An internal bandgap reference is available on pin 44, BG. By using this signal as reference for the signal to be converted, the conversion accuracy is not strongly related with the variation of the power supply. The power supply of the A/D converter (AVDD and AVSS ) in order to avoid interferences is mantained separated from the power supply of the digital core. Figure 6.2. Configuration Register REG_CONF2 ADC Configuration Register REG_CONF2 D7 D6 D5 D4 D3 D2 D1 D0 Reset ADC Must be 1 ADC input selection Not used 29/99 ST52T301/E301 7.TIMER TSTART starts/stops the Prescaler counting.It can be given on the pin TCTRL or it is forced by TMST bit of REG_CONF6 register. The TSTART signal allows to work in two different modes: LEVEL (Time Counter): If the TSTART signal is high the Timer starts the count. When the TSTART is low the count is stopped and the current value is stored in the TMR_OUT register of the Input register Bench, then it can be transferred to the j-th location of the Registers File by using the instruction: LDRI reg-j 4 EDGE(Period Counter): After the reset, when the first edge of the TSTART signal appears, the Timer starts the count, at the next TSTART the Timer is stopped. In this way it is possible to measure the period of an external signal. The functionment modality is set by the TMEL configuration bit of REG_CONF6 register. The starting value of the Counter can be either a value contained in the Register File or directly a Fuzzy Output. If INPSL (REG_CONF7(3)) is set to ”1” then the value comes from one of the locations of the Register File (LDRP 0, reg-i); on the contrary it is generated by the Fuzzy Core. The choice between the two possible fuzzy outputs is set by the FZSL configuration bit of REG_CONF6 register FZSL=0/1 means the starting value is the loaded from the FUZZY_OUT_0/1. ST52x301 offers one on-chip Timer peripheral. TheTimer consists of an 8-bit counter with a 16-bit programmable prescaler, thus giving a maximum count o f 224, and control logic that allows configuring the functionment and the type of peripheral outputs. Figure 7.2 shows the Timer block diagram and Figure 7.3 shows the internal structure of the Timer. The content of the 8-bit counter can be read/written and is incrementedon the Rising Edge of the 16-bit prescaler output (PRESCOUT). Moreover, it can be read under program control at any instant of the counting phase and loaded in a location of the Register File. The prescaler can be given any value between 0 and FFFFh setting the 4-th (TMLSB) and 5-th (TMMSB) locations of the Configuration Registers Bench. 7.1 Timer Functionment The Timer requires three signals: TMRCLK, TRST and TSTART (see Figure 7.3). Each of them can be generated internally or externally, this possibility is programmable by the user. TMRCLK increments the counted value of the Presc ale r. It can b e, by se tting CKSL of REG_CONF6 register, the internal clock signal (CLKM) or the signal provided on the pin TCLK. TRST resets to zero the contentof the 8 bit counter. It is generated by the TRES or RESET external signals or it is forcedby TMRSTbit of REG_CONF6 register. Figure 7.1. Timer Functionalities start start Level stop start start stop Edge Reset Clock Counted Value 30/99 0 0 1 2 3 3 3 0 ST52T301/E301 Figure 7.2. Timer Peripheral Block Diagram 31/99 ST52T301/E301 Figure 7.3. Timer Internal Structure 32/99 ST52T301/E301 7.2 Timer Interrupt It is possible to enable the Timer Interrupt by software control.The Timer can be programmed to generate an Interrupt request until the end of the count or when there is an external TSTART signal. The Timer can generate programmable Interrupts in to 4 different modes: Interrupt mode 1: Interrupt on counter Stop. Interrupt mode 2: Interrupt on Rising Edge of TIMEROUT. Interrupt mode 3: Interrupt on Falling Edge of TIMEROUT. Interrupt mode 4: Interrupt on both edges of TIMEROUT. In order to program the interrupt mode INTSL, INTF and INTR bits of the REG_CONF7 must be set following the indications shown in the Table7.1.The Timer interrupt can be used to exit the MCU from the WAIT mode. 7.3 Timer Configuration The Timer configuration needs to set 4 registers of the Configuration Register Bench. CONF_REG4: TMLSB contains the less significative bits of the Prescaler starting value. CONF_REG5: TMMSB contains the more significative bits of the Prescaler starting value Figure 7.4. TIMEROUT Signal Type Prescout*Counter Timer Output Type 1 Type 2 Table 7.1. Timer Interrupt Setting INTERRUPT MODE INTSL INTF INTR 1 1 X X 2 0 1 0 3 0 0 1 4 0 1 1 Figure 7.5. Timer Configuration Register 4 and 5 REG_CONF4 Timer D7 D6 D5 D4 D3 D2 D1 D0 TMLSB - Prescaler Init Value Less Significative Bits REG_CONF5 Timer D7 D6 D5 D4 D3 D2 D1 D0 TMMSB - Prescaler Init Value More Significative Bits 33/99 ST52T301/E301 CONF_REG6: TMRST sets the internal INR signal. TMST sets the internal INS signal. IESL selects the source of the TRES and TSTART signals. IESL=”0” signals are the internal INR and INS. IESL=”1” signals come from the TRES and TCTRL pins. TMEL selects the TSTART signal allowing to work in Level Mode or in Edge Mode like previously described. TMEL=”0” means Edge Mode TMEL=”1” means Level Mode. CKSL selects the source of the TMRCLK (working Timer frequency). CKSL=”0”, the TMRCLK is the internal MCLK divided by the Prescaler starting value. CKSL=”1”, the TMRCLK is an external clock by TCLK pin. TMS TIMEROUT is a signal with frequency equal to the working Timer frequency divided by the starting value of the Prescaler (16 bit) and Counter (8 bit). The Timer output can be eithera square wave with duty-cycle 50% or a pulse signal (with the pulse durationequal to the Prescaler output signal period). TMS=”1”, TIMEROUT is a square wave TMS= ”0”, TIMEROUT is a pulse signal. POL defines the polarity of the Timer output signal (TIMEROUT). Table 7.2. Configuration Register 6 Description Bit Name 0 TMRST 1 4 Description 0 Stop 1 Start 0 Stop 1 Start 0 Internal Signals 1 External Signals 0 on Edge 1 on Level 0 Internal Timer Clock 1 External Timer Clock 0 Pulse Wave (Type 2) 1 Square Wave (Type 1) 0 Positive Polarity 1 Negative Polarity TMST 2 3 Value IESL TMEL CKSL 5 6 7 TMS POL not used - Figure 7.6. Timer Configuration Register 6 REG_CONF6 Timer D7 D6 D5 D4 D3 D2 D1 D0 TMRST - Internal Timer Reset TMST - Internal Timer Start IESL - Internal/External Signals Selector TMEL - Edge/Level Timer Abilitation CKSL - Internal/External Clock Select TMS - Timer Output Shape POL - Timer Output Polarity not used 34/99 ST52T301/E301 CONF_REG7: INTSL It allows to select the interrupt mode for the Timer. INTSL=”0” Interrupt is generated on the falling edge of the Counter Stop. INTSL=”1” the interrupt is generated on the edges of TIMEROUT. INTF INTR INPSL selects the source of the value of the Counter between a location of the Register File and the Fuzzy Core. INPSL=”0”, Counter value coming from the FC. INPSL=”1”, Counter value coming from the RF. FZSL FZSL= ”0”, the valueof the TimerCounter is equal to FUZZY_OUT_0 FZSL= ”1”, the valueof the TimerCounter is equal to FUZZY_OUT_1 Table 7.3. Configuration Register 7 Description Bit Name 0 Value Description 0 INT_TMR on Falling Edge of Counter Stop 1 INT_TMR on Edges of TIMEROUT 0 NO INT_TMR on Falling Edge of TIMEROUT 1 INT_TMR on Falling Edge of TIMEROUT 0 NO INT_TMR on Rising Edge of TIMEROUT 1 INT_TMR on Rising Edge of TIMEROUT 0 Timer Data Input coming from the Fuzzy Core 1 Timer Data Input coming from a Register File location 0 Timer Data Input coming from FUZZY_OUT_0 1 Timer Data Input coming from FUZZY_OUT_1 INTSL 1 INTF 2 INTR 3 INPSL 4 FZSL 5 not used - 6 not used - 7 not used - Figure 7.7. Timer Configuration Register 7 REG_CONF7 Timer D7 D6 D5 D4 D3 D2 D1 D0 INTSL - Interrupt Generator Selector INTF - Interrupt on TIMEROUT Falling Edge INTR - Interrupt on TIMEROUT Rising Edge INPSL - Input Data Selector FZSL - Fuzzy Input Selector not used not used not used 35/99 ST52T301/E301 8 I/O PORT ST52x301 is provided with dedicated lines for input/output.These lines, grouped into an 8-bit I/O Port P(0:7), can be programmed to provide parallel input/output with a handshake line (READY) to carry data in/out. The I/O Port is not able to perform operations on the single bit, and the communication cannot be performed at the same time in input and output. It is possible to program the parallel port direction by using the register REG_CONF0 in order to set which bits are in input and which are in output. T he po r t h a s a n i n t ern a l reg ist e r (PERIPH_REG_2) dedicated to hold output data coming from the Register File through an LDPR instruction. Input data are automaticallystored in the IN_PORT register, 6-th location of the Input Register. P8 pin is a digital output line available directly connected to the OUT bit of the REG_CONF1; then it can be set by using a LDCF instruction. (see table 8.2 and Figure 8.8) Figure 8.2. 36/99 Figure 8.1. TTL CMOS INP_PORT(i) P(0:7) I/O PIN PERIPH_REG_2(i) TRISTATE IO(i) REG_CONF0(i) OUT REG_CONF1(0) P8 OUTPUT PIN ST52T301/E301 8.1 I/O PORT CONFIGURATION REG_CONF0 allows dynamic change in I/O Port configurationduring program execution setting the communication direction of each bit. IOi setting equal to ”0” configures the i-th bit of the P(0:7) I/O Port in input. Data coming from external digital devices are stored in the 6-th location (INP_PORT)of the Input register bench. IOi=”1” sets the i-th bit of the port in output. Data stored in the i-th location of the Register File is written on the port by using the instruction: LDPR 2, regi Table 8.1. Configuration Register 0 Setting Bit Name 0 IO0 1 2 3 4 5 6 7 Value Description 0 Input Pin 1 Output Pin 0 Input Pin 1 Output Pin 0 Input Pin 1 Output Pin 0 Input Pin 1 Output Pin 0 Input Pin 1 Output Pin 0 Input Pin 1 Output Pin 0 Input Pin 1 Output Pin 0 Input Pin 1 Output Pin IO1 IO2 IO3 IO4 IO5 IO6 IO7 Figure 8.3. Configuration Register 0 REG_CONF0 I/O Port D7 D6 D5 D4 D3 D2 D1 D0 IO0 - I/O Communication Direction Bit IO1 - I/O Communication Direction Bit IO2 - I/O Communication Direction Bit IO3 - I/O Communication Direction Bit IO4 - I/O Communication Direction Bit IO5 - I/O Communication Direction Bit IO6 - I/O Communication Direction Bit IO7 - I/O Communication Direction Bit 37/99 ST52T301/E301 8.2 INPUT HANDSHAKE Figure 8.5 illustrates the timing associated with the READY Handshake signal, when the instruction LDRI reg 6 is performed. When the LDRI instruction is executed to read the port, ST52x301 resets the READY signal to indicate that it is not possible to change the input data during this phase of reading. To synchronizethe transmission with READY signal will prevent the INP_PORT data from changing while ST52x301 is reading the port. READ PORT signal represented in figure 8.5 is an ST52x301 internal signal. Input data on the port are continuously sampled and are strobed into the port only when READY is set. Figure 8.4. One Line Input Handshake EXTERNAL PERIPHERAL W.A.R.P.3TC P(7:0) DATA I/O PORT R EADY IOP x x x x x x x 0 REG_CONF1 Figure 8.5. One Line Input Handshake Timing CLK READ PORT PIO(7:0) READY 38/99 DATA IN NEW DATA IN ST52T301/E301 8.3 OUTPUT HANDSHAKE Figure 8.6. One Line Output Handshake Figure 8.7 illustrates the timing associated with the READY Handshake signal, when the instruction LDPR 2 reg is performed. WhenREADY is reset no significantdata are on the output port pins, because ST52x301 is writing into the PERIPH_REG_2. When the data is ready in PERIPH_REG_2, READY signal is set. The rising edge of READY signal can be used as a latching signal. No peripheral acknowledge is waited for. If the signal READY is high, it means that the data out is still not read.In this case, the following LDPR instruction is stored in a one register peripheral stack. If the READY is maintained high, the following LDPR instructions store the data coming from the Registers File on the same register stack. Figure 8.7. One Line Output Handshake Timing 39/99 ST52T301/E301 It means that each LDPR instruction deletesthe old value contained in the parallel port stack register and rewrite a newvalue on the same stack register. Only the last LDPR instruction is executed if the READY signal is maintained high during several LDRP instructions. Table 8.2 Configuration Register 1 Setting Bit Name Value 0 P8 - Description Digital Output Bit 00 5 MHz 01 10 MHz 10 20 MHz 11 20 MHz 0 SCI End Transmission Interrupt Disabled 1 SCI End Transmission Interrupt Enabled 0 SCI Transmission Data Register Empty Interrupt Disabled 1 SCI Transmission Data Register Empty Interrupt Enabled 0 SCI Break Error Interrupt Disabled 1 SCI Break Error Interrupt Enabled 0 SCI Overrun Error Interrupt Disabled 1 SCI Overrun Error Interrupt Enabled 0 SCI Received Data Register Full Interrupt Disabled 1 SCI Received Data Register FullInterrupt Enabled 1 ECKF 2 3 4 5 6 7 Figure 8.8. 40/99 TXC TDRE BRK OVR RDRF ST52T301/E301 9 SERIAL COMMUNICATION INTERFACE The Serial Communication Interface (SCI) integrated into the fuzzy processor ST52x301 provides a gene ral p urpose shift register peripheral, that allows to link several widely distributed MCUs, through their SCI subsystem. The SCI gives a serial interface providing communication with common baud rates, up to 38400 Hz, and flexible character format. The SCI is a full-duplex UART-type asynchronous system with standard Non Return to Zero (NRZ) format for the transmitted/received bit. The length of the transmitted word is 10/11 bits (1 start bit, 8/9 data bits, 1 stop bit). The SCI is composed of three modules: Receiver, Transmitter and Baud-Rate Generator and it is configured by means of Configuration Registers 3 and 1. Figure 9.1. SCI transmitted word structures 9.1 SCI RECEIVER BLOCK T he SCI Rec eive r b lo ck ma n ag e s t h e synchronization of the serial data stream and stores the data characters. The SCI Receiver is mainly formed by two sub-systems: Recovery Buffer Block and SCDR_RX Block. The RE configuration bit set to ”1” (Configuration Register 3) enables the SCI Receiver. The SCI receives data coming from the RxD pin and drives the Recovery Buffer Block, that is a high-speed shift register operating at a clock frequency (CLOCK_RX) 16 times higher than the fixed baud rate (CLOCK_TX). This sampling rate, higher than the Baud Rate clock, allows to detect Figure 9.2. SCI Block Diagram 41/99 ST52T301/E301 the START condition,theNoise errorand the Frame error. When the SCI Receiver is in IDLE status, it is waiting for the START condition, that is obtained with a logic level 0, consecutive to a logic level 1. This conditionis detected,if,with thefixedsampling time, three logic levels 0 are sampled after three logic levels 1. The recognition of the START bit forces the SCI Receiver Block to enter in an data acquisition sequence, according to serial mode. The 2 bits, M, of the ConfigurationRegister 3 allow to definethe serial mode with the conventionshown in table 9.2. The bit, T8, in caseof M = 10 is used to set the parity check to perform, as indicated in the previous table 9.2. The recognition of STOP condition allows to transfer the received data, from Recovery Bufferto SCDR_RX buffer, adding the eventual ninth data bit, according to the meaning shown in the previous table 9.2. After this operation, RXF flag of SCI Status Input Register 8 (fig. 9.3) is set to logic level 1. The Control Unit reads the data from SCDR_RX buffer (in read-only mode) with SRX instruction and provides a reset at logic level 0 to RDRF flag. If a data of Recovery Buffer is ready to be transferred into SCDR_RX buffer, but the previous one was not yet read by the Core, an OVERRUN Error takes place: the status flag OVERR indicates the error condition. In this case the information stored in SCDR_RX buffer is not altered, but the one that has caused the OVERRUN error can be overwritten by a new data coming from the serial data line. Table 9.1 Configuration Register 3 Setting Bit Name 0 TE 1 42/99 Description 0 Transmission DISABLED 1 Transmission ENABLED 0 Receiver DISABLED 1 Receiver ENABLED 00 8, No Parity, 1 bit stop 01 8, No Parity, 2 bit stop 10 8, Parity, 1 bit stop 11 9, No Parity, 1 bit stop 0 Parity Odd, if Parity is selected (M = 10); otherwise 9th Data bit 1 Parity Even, if Parity is selected (M = 10); otherwise 9th Data bit RE 2 M 3 4 T8 5 BRSL Recovery Buffer Block This block is structured as a synchronised finite state machine on the CLOCK_RX signal falling edge. When the Recovery Buffer Block is in IDLE state it waits for the reception of the correct 1 and 0 sequence representing the START. The recognition takes place by sampling the input RxD at CLOCK_RX f requency, that has a frequency 16 times higher than CLOCK_TX. For this reason, while the external transmitter sends a single bit, the Recovery Buffer Block samples 16 states (from SAMPLE1 to SAMPLE16). Value 6 000 600 Hz 001 1200 Hz 010 2400 Hz 011 4800 Hz 100 9600 Hz 101 19200 Hz 110 38400 Hz 111 External Clock 7 ST52T301/E301 The analysis of RxD input signal is carried out looking three samples for each bits received.0 If these three samples are not equal, then the noise error flag, NSERR, of Input Register 8 is set to 1 and the received data value will be the one assumed by the majority of the samples. By means of the procedure described above, to avoid SCI becomes IDLE, because of a limited noise due t o an erroneous sampling, th e transmissionis recognizedas correct and the noise flag error is set. At the end of the cycle relative to the reception of a bit, Recovery Buffer Block will repeat the same steps 9 times: one step for each received bit, plus one for the stop acquisition(10 times in caseof 9-bit data, double stop or parity check). At the end of datareception,Recovery BufferBlock, will supply information on eventual frame errors by setting to 1 FRERR flag bit of Input Register 8. A frame error can occur if the parity check has not been successfully achieved or if STOP bit has not been detected. If Recovery Buffer Block receives 10 consecutive bits at logic level 0, a break error occurres, and interrupt routine request starts. SCDR_RX block It is a finite state machine synchronized with the falling edge of the clock master signal, CKM. The SCDR_RX block waits the signal of complete reception, from the Recovery Buffer, to load the word received. Moreover, the SCDR_RCX block loads the values of FRERR and NSERR flag bits (Input Register 8), and sets the RXF flag to 1. Using SRX instruction the data are transferred to Register File and RXF flag is reset to 0, to indicate SCDR_RX block is empty. If a new data arrives before the previous one has been transferred to Register File, an overrun error occurres and OVERR flag, of Input Register 8, is set to 1. Table 9.2 Configuration Register 1 Setting Bit Name Value 0 P8 - Description Digital Output Bit 00 5 MHz 01 10 MHz 10 20 MHz 11 20 MHz 0 SCI End Transmission Interrupt Disabled 1 SCI End Transmission Interrupt Enabled 0 SCI Transmission Data Register Empty Interrupt Disabled 1 SCI Transmission Data Register Empty Interrupt Enabled 0 SCI Break Error Interrupt Disabled 1 SCI Break Error Interrupt Enabled 0 SCI Overrun Error Interrupt Disabled 1 SCI Overrun Error Interrupt Enabled 0 SCI Received Data Register Full Interrupt Disabled 1 SCI Received Data Register FullInterrupt Enabled 1 ECKF 2 3 4 5 6 7 TXC TDRE BRK OVR RDRF 43/99 ST52T301/E301 Figure 9.3. SCI Status Input Register 9.2 SCI TRANSMITTER BLOCK The SCI Transmitter Block consists of the following underblocks: SCDR_TX and SHIFT REGISTER, synchronized, respectively, with the clock master signal (CKM) and the CLOCK_TX. The whole block receives through Configuration Register 3 (M bits) the settings for the following transmission modes (see table 9.1): 8-bit word and a single stop signal 8-bit word plus a paritybit and a singlestop signal 8-bit word plus a double stop signal 9-bit word In case of 9 bit frame transmission, the most significat ive bit arrives through T8 of th e Configuration Register 3. In an 8-bit transmission, instead, T8 is used to configure the SCI, according to information containedin M (see table 9.1):in particularto chose the polarity control (even or odds) to implement the parity check. After a RESET signal, RST, the SCDR_TX block is in IDLE state until it receivesenabling signal, TE=1, of Configuration Register 3. If TE=1, using STX instruction the data, to be transmitted, are transferred from Register File to SCDR_TX block and the flag of Input Register 8, TXEM, is reset to 0, to indicate SCDR_TX block is full. If the core supplies a new data, this could not be loaded in the SCDR_TX block until the current data has not been unloaded on the Shift Register block. This means that only when TXEM is 1, it is possible to load data in the SCDR_TX Block. When the SHIFT REGISTER Block loads the data to be transmitted on an internal buffer, TXEND is 44/99 reset to 0 to indicate the beginning of a new transmission. At the end of transmission TXEND is set to 1, allowing to load in the SHIFT REGISTER a new data coming from SCDR_TX. It is important to underline that TXEND = 1 does not mean SCDR_TX is ready to receivea newdata. For this reason it is better to utilise the TXEM signal to synchronize the STX instruction to the SCI TRANSMITTER block If ST52x301 core resets TE to 0, the transmission is interrupted, but the SCI Transmitter block completes the transmission in progress before to reset. 9.3 Baud Rate Generator Block The Baud Rate Generator Block performs the division of the clock master signal (CKM), in a set of synchronism frequencies for the serial bit reception/transmission on the external line. Table 9.1. shows the set of frequenciesselected by means of BRSL (Configuration Register 3). Reception frequency (CLOCK_RX) is 16 times higher than transmission frequency (CLOCK_TX) . If BRSL is equal to 111, CLOCK_RX and CLOCK_TX signals coincide with clock master, CKM. ST52T301/E301 10 TRIAC/PWM DRIVER ST52x301 offers a peripheral able to generate a signal on pin 24, TRIACOUT, to drive an external device, like a TRIAC, a IGBT or a Power Mos. Triac/PWM driver can perform 3 different working modes according to REG_CONF10 bits, MODE (see Table 10.4): MODE = ”01”: PWM MODE = ”10”: Burst Mode Triac Control (Thermal Regulations) Note: in this case CKSL of REG_CONF10 must be set to ”1x”. (see Table 10.4) MODE = ”11”: Phase Angle Partialization Triac Control (Motor Control) The Triac/PWM Driver can be initialized by using a value fixed by a controlalgorithm, that can be either the output of a fuzzy inference or the result of an arithmetic calculus stored in the Register File. In the latter case, by using the LDPR 1,reg-i instruction, the value, contained in the i-th register of Register File, is stored in the Triac Driver/PWM peripheral register PERIPH_REG_1. Figure 10.1 shows the internal structure of Triac/PWM Driver. PWM Mode The PWM working mode is obtained by setting REG_CONF10 bits, MODE, at ”01” value. It consists of a signal, with fixed period , whose duty cycle can be modified. Figure 10.1. TRIAC/PWM Driver Simplified Block Diagram 45/99 ST52T301/E301 The PWM period can be generated, internally, by dividing the master clock or, externally, by using an external clock signal. In both cases, the clock signal is divided by a 16-bit Prescaler, managed by REG_CONF8 an d REG_CONF9 (see Figure 10.2). The duty cycle is fixedby a value,that can be either the output of a fuzzy inference or the result of an arithmetic calculus. In the first case, it can be loaded directly in the register of the peripheral, otherwise it can be stored in one location of the Register File for further manipulations and then used for the control of the PWM. Burst Mode It is based on turning on and off the TRIAC, for a fixed integer number of main voltage periods, in order to control the power transferred to the load. For this reason a Burst Mode TRIAC control consists of a signal, with a period, T, containing an integer number of the main voltage periods, whose duty cycle is proportional to the number of periods in which the TRIAC is ON (Duty Cycle). This kind of Triac control is mainly used for thermal regulation. Theduty cycle is fixedby a valuethat can be directly the output of a fuzzy inference or the result of an arithmetic calculus. In order to work in Burst mode, it is necessary to detect the pre-post zero-crossing of main voltage, by using an external inserting circuitry. The user can define the period T, by means of the internal 16-bit prescaler, setting REG_CONF8 and REG_CONF9 (see Figure 10.2).T is proportional to the main voltage period, it is in the range 0 to 21.8 sec (if the main frequency is 50Hz). The width and the polarity of the pulses can be programmed according to the Triac and the circuit characteristics. Phase Angle Partialization Mode This method is based on turning on the TRIAC only for a part (phase angle) of each main voltage period. When the phase angle is large the energy (power)supplied to the load is low, viceversa, when the phase angle is small the energy supplied to the load is high. The phase angle can be fixed by a fuzzy algorithm or by a value stored in the Register File. The phase angle is an 8-bit value. The peripheral is programmable in order to work with a main voltage frequency of 50 or 60 Hz. Figure 10.2. TRIAC/PWM Configuration Register 8 and 9 REG_CONF8 TRIAC / PWM D7 D6 D5 D4 D3 D2 D1 D0 TCLSB - Prescaler init value Least Significative Bits REG_CONF9 TRIAC / PWM D7 D6 D5 D4 D3 D2 D1 D0 TCMSB - Prescaler init value Most Significative Bits 46/99 ST52T301/E301 10.1 PWM GENERATOR WORKING MODE When REG_CONF10 (3:2) bits, MODE, are ”01”, the peripheral is programmed to work in PWM Mode. By using the 16-bit prescaler, the PWM period can be generated by dividing the internal master clock, or an external clock signal applied on the pin MAIN1, or the main voltage frequency, by using the circuit shown in Figure 10.6. NOTE: The external clock signal, applied on MAIN1 pin, must have a frequency at least three time smaller than the internal master clock. The clock source can be selected by using REG_CONF10(5:4)bits, CKSL(see Table 10.4 and Figure 10.9). If the clock source selected is not the main voltage frequency(CKSL=1x), MAIN2 pin can be configured as input or output, by using REG_CONF10(7) bit, IOSL (see Table 10.4). If MAIN2 is an output, on this pin it is possible to get the prescaler output signal Tck. The period of the PWM signal is obtained by using the following relation: T=256*Tck where Tck is the output of the 16-bit prescaler managed by REG_CONF8 and REG_CONF9 (see Figure 10.2). NOTE. In PWM working mode, the value N, stored in the 16-bit prescaler, must be in the range from 2 to 216-1 By using a 20 MHz clock master it is possible to obtain a PWM frequency in the range 1.2 Hz to 26.04 KHz. The value Ton is prop ortional to a value, INIT_VALUE, that can be a fuzzy output or a value coming from Register File, according with the I NP SL a n d F Z S L c o nf igu rat io n b it s o f REG_CONF12 (see Table 10.6 and Figure 10.12). The Ton is equal to: Ton= INIT_VALUE*Tck. It means the Ton can be fixed by the control algorithm that can be either the output of a fuzzy inference or the result of an arithmetic calculus. In the second case, the data, stored in the i-th location of the Register File, can be loaded by using the instruction: LDPR 1, reg-i. If the INIT_VALUE is 255 the Toff is equal to Tck. Table 10.1. MODE - Triac/PWM Working Mode Settings Value Note: Description 01 PWM Driver 10 Burst Mode Control (1) 11 Phase Angle Control (1) REG_CONF10(5) must be set to ”1” Table 10.2. PWM Frequencies 1/T MCLK Frequency min max 5 MHz 0.3Hz 6.51 kHz 10 MHz 0.6 Hz 13.02 kHz 20 MHz 1.2 Hz 26.04 kHz Figure 10.3. PWM Functionament T = 256 * Tck Ton = INIT_VALUE* Tck Toff TRIACOUT 47/99 ST52T301/E301 10.2 BURST MODE When REG_CONF10 (3:2) bits, MODE, are ”10” the peripheral is programmed to work in BURST MODE. Notice that when you are working in Burst mode CKSL must be set to ”1x”. (see Table 10.4) A square wave, Tb, is generated with a duty cycle proportional to the power the user intends to transfer on the load. A pulse is generated for each zero crossing of the main voltage included in the Ton of the fixed period. Figure 10.4 shows the typical Burst Control working mode.The period T of the signal Tb (see Figure 10.4) is equal to 256*Tck. Thesignal Tckis generatedprogrammingthe 16-bit Prescaler, by REG_CONF8 and REG_CONF9 (see Figure 10.2). Tck is equal to the main voltage frequency (50 or 60 Hz) divided by N+1, where N value is from 0 to 216-1. The value Ton is prop ortional to a value, INIT_VALUE, that can be a fuzzy output or a value coming from Register File, according with the I NPS L a n d F Z S L c o nf ig urat io n b it s of REG_CONF12 (see Table 10.6 and Figure 10.12). On TRIACOUT pin is generated a sequence of pulses, programmed, by using REG_CONF11(0) bit, POL (see Table 10.5), in order to be positive or negative, to drive the Triac in different quadrants. The number of generated pulses, N_PULSES, is: N_PULSES = 2 [(N+1)*INIT_VALUE - N] where N is the value stored in the 16-bit pescaler. Then Ton = (N_PULSES / 2)* TPOWER LINE The first pulse is obtained during the first zero crossing of the main voltage and the last one is generated after INIT_VALUE*Tck clock pulses, where Tck is the Prescaler output, generated by using the main voltage frequencyapplied to MAIN1 and MAIN2 pins. Theperipheral can be programmed in order to work with 50 or 60 Hz main voltage frequency, by setting the REG_CONF10(6) bit, PSF (see Table 10.4). Ranges of the Tb signal period depend on the power line frequency (see Table 10.3). In order to drive a Triac in Burst Mode it is required to generate a sequence of pulse, that must be centred on the zero crossing of the power line as shown in the Figure 10.7. For this reason, the pre zero crossing and the post zero crossing of the power line must be detected. To detect the zero-crossing and get also the main voltage frequency, the user must generate MAIN1 and MAIN2 signals, by using the circuit shown in Figure 10.6. MAIN1 and MAIN2 signals are used in the block called PULSE GENERATOR of the peripheral (see Figure 10.1). In particular the pulses are generated by using the rise edge of the signal MAIN1 and the falling edge of the signal MAIN2. Figure 10.5 shows the generation of the Triac pulses Tp . The first firing pulse for the Triac is generated on the zero crossing of the power line, while the next pulses are centred on the zero crossing. Table 10.3. TRIACOUT Signal Period min max 50 Hz 5.12 s 335544 s 60 Hz 4.26 s 279620 s Figure 10.4. Burst Working Mode T = 256 * Tck Ton Tb 1.5 1 0.5 Power 0 Line -0.5 -1 -1.5 TRIACOUT 48/99 T Power Line Frequency ST52T301/E301 Normally the Triac firing pulses start 1/3 Tp before the zero crossing and the lengthof the pulses is Tp, see Figure 10.5. The length Tp of the pulses is programmable by using UTP value, that is a 14-bits number, obtained with REG_CONF12(5:0) bits, UTPMSB, and REG_CONF13, UTPLSB (see figure 10.12 and table 10.6): UTP(13:0) = [UTPMSB(5:0) UTPLSB(7:0)] TP = TMCLK * UTP The value Tp is in the range 0 to 4.9 ms when the clock master is 20 MHz. According to REG_CONF11(0) configuration register bit, POL, it is possible to set the firing Figure 10.5. Burst Mode pulse polarity TP MCLK Frequency min max 5 MHz 0.0012 ms 19.6608 ms 10 MHz 0.0006 ms 9.8304 ms 20 MHz 0.0003 ms 4.9152 ms pulses polarity; in order to obtain positive or negative gate Triac currents, allowing to work respectively in I and IV quadrants, or in the II and III quadrants (see Figures 10.5 and 10.12). To increase the immunity of the peripheral against the electrical noise of the main voltage, a pr og ramma ble ma sk ing t ime, by u s in g REG_CONF11(5:2) bits, TCMSK (see Table 10.5) Figure 10.7 Burst Mode Zero Crossing 1.5 1 1 0.5 Power Line 0.5 0 Main Voltage 0 (0.5) (1) Positive Triac Gate Current II and III quadrants Ig -0.5 -1 Tp TMASK Tp TMASK Tp TRIACOUT -1.5 Ig Negative Triac Gate Current I and IV quadrants MAIN1 2/3 Tp 1/3 Tp Tp MAIN2 Figure 10.6 Burst Mode Zero Crossing Circuit 49/99 ST52T301/E301 and Figure 10.11), is introduced after each firing pulse (see Figure 10.7): Masking time =(2^TCMSK*200 +100) nS. If TCMSK is 0 then Masking time is 0. In fact, to avoid the detection of electrical noise, during the masking time no signal, coming from MAIN1 and MAIN2, is taken into account. Working in the II and III quadrant the peripheral implements the following procedure: 1) The firing pulse is set to ”1” on the rising edge of MAIN1. 2) The firing pulse is reset to ”0” after the time Tp fixed by program. 3) The firing pulse is reset to ”0” for a time equal to the fixed masking time. 4) On the falling edge of MAIN2 the firing pulse is set to ”1” 5) The firing pulse is reset to ”0” after the time Tp fixed by program. 6) The firing pulse is reset to ”0” for a time equal to the fixed masking time. Following this approach it is possible to filter electrical noise and oscillations on the signal MAIN1 and MAIN2. It is possible to generate a programmable Interrupt in four different ways: 1) No Interrupt; 2) Interrupt on the rising edge of the signal Tb. 3) Interrupt on the falling edge of the signal Tb. 4) Interrupt on both the edge of the signal Tb. The Interrupt is programmable by using the register REG_CONF11(7:6), INTSL (see Table 10.5). TCMSK MaskingTime 0000 0 µs 0001 0.5 µs 0010 0.9 µs 0011 1.7 µs 0100 3.3 µs 0101 6.5 µs 0110 12.9 µs 0111 25.7 µs 1000 51.3 µs 1001 102.5 µs 1010 204.9 µs 1011 409.7 µs 1100 819.3 µs 1101 1638.9 µs 1110 3276.9 µs 1111 6553.7 µs 10.3 PHASE ANGLE PARTIALIZATION WORKING MODE When REG_CONF10 (3:2) bits, MODE, are ”11” the peripheral is programmed to work in PHASE ANGLE PARTIALIZATION mode. In this mode Triac is controlled each period of the main voltage. The power transferred to the load is proportional to the CURRENT FLOW ANGLE γ. This kind of Triac control is suitable to drive the Triac Figure 10.8. Phase Angle Partialization Mode 1.5 VA2-A11 0.5 L Loa d Il A2 A1 N 0 1.5 (0.5) α Phase Angle Il1 (1) 0.5 (1.5) 0 (0.5) γ Current Flow Angle (1) (1.5) 50/99 180 0 360 0 ST52T301/E301 with inductive load (i.e. universal or monophase motors). In the figure 10.8 is shown the relation between the Phase Angle α and the Current flow angle γ . The peripheral allows to control the Phase Angle or equivalentlythe time T1 (see Figure 10.9). It is possibleto changeTime T1 settingthe contents of the peripheral register PERIPH_REG_1. This value could be directly loaded by using one of the two fuzzy outputs or by using a value coming from the Registers File, according with INPSL and FZSL configurationbits of REG_CONF12 (seeTable 10.6 and Figure 10.13). In order to synchronizethe peripheral with the zero crossing of the main voltage the two pins MAIN1 and MAIN2 must be connected together if the externalcircuit is the one shownin the Figure10.10. It is possible to use different circuits for the zero crossing detection, but the MAIN1 signal rising edge must be synchronized with a main voltage zero crossing and the MAIN2 signal falling edge Figure 10.9 Phase Angle Partialization mode Tr Mains 1.5 Voltage Tr/2 1 Ti 0.5 0 (0.5) (1) T1 T1 Tmax (1.5) 8 mS 10 mS 20 mSec must be synchronized with the following main voltage zero crossing, always. Theperipheral can be programmed in order to work with 50 or 60 Hz main voltage frequency by setting the REG_CONF10(6) bit, PSF (see Table 10.4). If main voltage frequencyis equal to 50 Hz, then Tr, see figure 10.9, is equal to 20 mSec and T1 is: T1 = PERIPH_REG_1(0:7)*(1/25.5)ms. The length of the semiperiod Ti/2 is programmable by using the registers REG_CONF12(0:5) and REG_CONF13, (see figure 10.12).By using a clock master equal to 20 MHz the pulse width is in the range from 0.2 to 250 µs. The duty cycle of Ti is always 50 %. In order to avoid problems for the Triac firing when the load is inductive 8 different pulses are generated by the peripheral. If the time T1 is bigger than a fixed time Tmax then no pulses are generatedand the Triacis maintained off. This feature was implemented in order to avoid the firing of the Triac in the second half period of the main voltage. The firing pulses are generated when the contents of the PERIPH_REG_1 is less or equal to 204, otherwise they are not generated. When the frequency of the main voltage is 50 Hz, T1max is equal to 8 mSec. It is possible to generate a programmable interrupt in four different ways: 1) no Interrupt; 2) Interrupt on the rising edge of the signal MAIN1 3)Interrupt on the falling edge of the signal MAIN2 4) Interrupt on both the edges of the signal MAIN1. The Interrupt is programmableby using the register REG_CONF11(7:6), INTSL 10.4.TRIAC/PWM DRIVER PROGRAMMING Figure 10.10 Phase Angle Partialization Zero Crossing 51/99 ST52T301/E301 It is possible SET or RESET the TRIAC/PWM Peripheral by using the REG_CONF10(0) bit, TCRST (see Table 10.4). If TRIAC/PWM Peripheral is SET, It is possible START or STOP it, by using the REG_CONF10(1) bit, TCST (see Table 10.4), to start or stop the internal counter without resetting it. It is possible to enablethe TRIACOUT, byusing the REG_CONF11(0) bit, TCTRS (see Table 10.5 and Figure 10.11). IF TCTRS is 0 the TRIAC/PWM Peripheraloutput is in tristate status. Table 10.5 Configuration Register 11 Description Bit 0 1 Name Value 0 Output pulse Polarity = positive 1 Output pulse Polarity = negative 0 TRIACOUT status = Tristate 1 TRIACOUT status = Enabled POL TCTRS 2 3 Description Masking time =(2^TCMSK*200 +100) nS. TCMSK=0 →Masking time=0 TCMSK 4 5 Table 10.4 Configuration Register 10 Description Bit Name 0 TCRST Value 0 1 00 No Interrupt source selected 01 Interrupt on falling edge of the TRIAC/PWM signal, or of the Main Voltage 10 Interrupt on rising edge of the TRIAC/PWM signal, or of the Main Voltage 11 Interrupt on both of edges of the TRIAC/PWM signa,l or of the Main Voltage 6 Description INTSL Triac Reset 1 Triac Set 0 Triac Stop 7 TCST 1 Triac Start 00 not used 01 PWM signal Generator 10 Burst Mode 11 Phase Partialization 00 Clock Master 01 External Clock on MAIN1 1x Main Voltage Frequency 2 MODE (1) Table 10.6. Configuration Register 12 Description 3 4 CKSL 5 Bit Name 0÷5 UTPMSB 6 6 0 Main Power at 50 Hz 1 Main Power at 60 Hz 0 MAIN2 Input pin Description Output Impulse Width most significative bits 0 TRIAC/PWM Input from Fuzzy Output 1 TRIAC/PWM Input from Register File 0 TRIAC/PWM Input from Fuzzy Output 1 1 TRIAC/PWM Input from Fuzzy Output 2 INPSL PSF 7 IOSL 1 Note: Value (1) 52/99 MAIN2 Output pin CKSL must be set to ”1x” 7 FZSL ST52T301/E301 Figure 10.11. TRIAC/PWM Configuration Register 10 Figure 10.12 TRIAC/PWM Configuration Register 11 Figure 10.13 TRIAC/PWM Configuration Registers 12 and 13 53/99 ST52T301/E301 11 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings This product contains devices to protect the inputs against damage due to high static voltages, however it is advised to take normal precaution to avoid any voltage higher than maximum rated voltagees. For proper operation it is recommended that VI and VO must be higher than VSS and smaller than VDD. Reliability is enhanced if unu sed inputs are connected to an appropriated logic voltage level Table 11.1. Absolute Maximum Ratings Symbol VDD Parameter Supply Voltage Value Unit -0.5 to 7 V VI Input Voltage VSS-0.3 to VDD+0.3 (1) V VO Output Voltage VSS-0.3 to VDD+0.3 (1) V Analog Supply Voltage VSS-0.3 to VDD+0.3 (1) V VDDA, VSSA VPP EPROM Programming Voltage Standard Output Source Sink Current (2) IO TRIACOUT Output Source Sink Current TOPT Operating Temperature TSTG Storage Temperature 13 V ±20 mA ±80 (3) mA 0 to +85 °C -65 to +150 °C Note: Stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 1. Wit hin these limits, clamping diodes are garanteed to be not conductive. 2. All except TRIACOUT pin 3. For not more than 1 sec. 54/99 ST52T301/E301 (VSS or VDD) RECOMMENDED OPERATING CONDITIONS (Operating Condition: VDD=5V±5%-TA=0 °C to 85 °C, unless otherwise specified) Table 11.2. Recommended Operation Condition Symbol Parameters Test Conditions Min Typ Max Unit V DD Operating Supply Voltage 4.75 5.0 5.25 V VPP Programming Voltage 11.4 12 12.6 V VO Ouput Voltage VSS VDD V VSS VDD V 20 MHz VDDA, VSSA Analog Supply Voltage fOSC Notes: Oscillator Frequency (1) Vss ≤ VSSA < VDDA ≤ VDD 5 10 1. For correct behaviour of some peripherals, it is possible to work only with one of the 5 - 10 - 20 MHz frequencies. 55/99 ST52T301/E301 DC ELECTRICAL CHARACTERISTICS (Operating Condition: VDD=5V±5%-TA=0 °C to 85 °C, unless otherwise specified) Table 11.3 DC Electrical Characteristics Symbol Parameter Test Conditions Min Typ Max Unit TTL type Schmitt trig. Low Level Input Voltage VDD =4.75 V see fig.11.6 0.7 V CMOS type Schmitt trig. Low Level Input Voltage VDD =4.75 V see fig.11.7 1.2 V TTL type Schmitt trig. High Level Input Voltage VDD =5.25 V see fig.11.6 2 V CMOS type Schmitt trig. High Level Input Voltage VDD =5.25 V see fig.11.7 3.5 V VIL V IH Standard Low Level Output Voltage IOL =4mA 0.4 V VOL TRIACOUT Low Level Output Voltage IOL =50mA (1) IOL =-4mA Standard High Level Output Voltage VOH (1) TRIACOUT High Level Output Voltage 2 VDD-0.5 V V IOL =50mA VDD-2 V TTL type Schmitt trig. Hysteresis Voltage see fig. 11.6 1.2 V CMOS type Schmitt trig. Hysteresis Voltage see fig. 11.7 2.0 V VHys IIL Low Level Leakage Input Current VI=VSS -1 µA IIH High Level Leakage Input Current VI=VDD +4 µA IOL Tri-State Output Leakage Current VO=VSS or VDD ±10 mA Supply Current in RESET mode VPP connected with VDD; VRESET =VSS FOSC= 10 MHz 11 mA Supply Current in RUN mode VPP connected with VDD; FOSC= 10 MHz 11 mA Analog Supply Current in RESET mode VPP connected with VDD; VRESET =VSS FOSC= 10 MHz 3 mA Analog Supply Current in RUN mode VPP connected with VDD; FOSC= 10 MHz 10 mA IDD IDDA 56/99 ST52T301/E301 AC ELECTRICAL CHARACTERISTICS (Operating Condition: VDD=5V±5%-TA=0 °C to 85 °C, unless otherwise specified) Table 11.4. AC Electrical Characteristics Symbol Parameter Test Conditions Min Typ Max Unit RS Input protection Resistor All Input Pins 1 kΩ CIN Input Capacitance All Input Pins 10 pF Output Capacitance All Ouput Pins 10 pF COUT Table 11.5. Timing Parameters Symbol Parameters Test Conditions Min Typ Max Unit fOSC Oscillator Frequency tCLH Clock High 25 20 MHz ns tCLL Clock Low 25 ns tSET Setup see fig 11.1 5 ns tHLD Hold see fig. 11.1 5 ns tWRESET Minimum Reset Pulse Width 100 ns tWINT Minimum External Interrupt Pulse Width 100 ns tIR Input Rise Time see fig.11.2 15 ns tIF Input Fall Time see fig.11.2 15 ns tOR Output Rise Time CLOAD=10 pF see fig.11.2 10 ns tOF Output Fall CLOAD=10 pF see fig.11.2 10 ns Figure 11.1. Data Input Timing Figure 11.2. I/O Rise and Fall Timing 57/99 ST52T301/E301 Figure 11.3. Input Pin Equivalent Circuit Figure 11.4. Equivalent Tristate Output Circuit 58/99 Figure 11.5. Equivalent Output Circuit ST52T301/E301 Figure 11.6. TTL-level Input Schmitt Trigger Figure 11.7. CMOS-level Input Schmitt Trigger Note: Only for RETE1 and RETEIO signals TIMER CHARACTERISTICS (Operating Condition: VDD=5V±5%-TA=0 °C to 85 °C, unless otherwise specified) Table 11.7. Timer Characteristics Symbol tRES Parameter Resolution fIN External Input Frequency on timer Internal Input Frequency on timer tW Pulse Width on TIMEROUT pin Min Typ Max µs 1/FOSC 20 1/FOSC Unit MHz µs 59/99 ST52T301/E301 A/D CONVERTER CHARACTERISTICS (Operating Condition: VDD=5V±5%-TA=0 °C to 85 °C, unless otherwise specified) Table 11.8. A/D Converter Characteristics Symbol Parameter Res Resolution ATOT Total Accuracy (1) tC Conversion Time Test Conditions Min Typ Max Unit 8 bit FOSC > 5 MHz FOSC > 10 MHz FOSC > 20 MHz ±2 LSB FOSC =5 - 10 - 20 MHz 32 µs VAN Conversion Range VZI Zero Scale Voltage Conversion result= 00 Hex VSSA V VFS Full Scale Voltage (bandgap) Conversion result= FF Hex 2.474 V ∆V FS% Full Scale Voltage (bandgap) precision v/s VDDA variation VDDA=5V±5% ADI Analog Input Current during Conversion fOSC = 20 MHz (2) 2.5 VSSA 1 V % µΑ 2 Analog Input Capacitance 2 pF ASI Analog Source Impedance 1 kΩ ORI Output Reference Impedance ORL Output Reference Load 0.1 mA Analog Reference Load Capacitance 10 pF ACIN ORLC Source-Off and Drain-Off Leakage Currents are in the range of nA. Notes: 1. Noise at VDDA, VSSA <40 mV 2. Excluding Pad Capacitance. 60/99 Ω 100 ST52T301/E301 INSTRUCTION SET ADD Addition Format: ADD regi, regj Operation: regi <- regi + regj Description: The contents of the Register File j-th register specified as source is added to the destination i-th register, leaving the result in the destination register. The result is 255 if overflow occurs. Flags: Z set if result is zero, cleared otherwise. S set if overflow, cleared otherwise. Bytes: 2 Cycles: 7 Example: If the register 4 contains the value 45 and the register 11 contains the value 15, then the instruction ADD 4,11 1001000 0100|1011 causes the register 4 of the Register File to be loaded with the value 60. If the register 4 contains the value 200 and the register 11 contains the value 100, the instruction causes the register 4 to be loaded with the value 44 (result-256) and the S flag to be set 61/99 ST52T301/E301 AND Logical AND Format: AND regi, regj Operation: regi <- regi AND regj Description: The instruction logically ANDs the contents of the Register File j-th register specified as source and the destination i-th register in the Register File, leaving the result in the destination register. Flags: Z set if result is zero, cleared otherwise. S not affected. Bytes: 2 Cycles: 7 Example: If the register 4 contains the value 10011100 and the register 12 contains the value 01010101, then the instruction AND 4,12 10010001 0100|1100 causes the register 4 of the Register File to be loaded with the value 00010100. 62/99 ST52T301/E301 CON Consequent Format: CON cost Operation: Dividend Register <- Dividend Register + cost*teta Divisor <- Divisor + teta Description: This intruction computes the values to add in the defuzzification registers, at the end of the single rule. The specified constant is the crisp value representing the output crisp membership function: it is multiplied by the last fuzzy operation result. 63/99 ST52T301/E301 DATA Membership Functions data Format: Operation: DATA var mbf lvd vtx rvd ADM location 16*var+mbf ADM location 16*var+mbf+64 ADM location 16*var+mbf+128 <- lvd <- vtx <- rvd Description: This instruction is a pseudo instruction (it does not correspond to any operation executed by the processor) that allows to store membership functions data in the ADM (Antecedent Data Memory). The var and the mbf data identify the membership function. The lvd data is the left semibase distance of the M.F., the vtx data is the position of the vertex and rvd is the right semibase distance. 64/99 ST52T301/E301 FZAND Fuzzy AND Format: FZAND Operation: K <- stack0 AND stack1 Description: This instruction computes the AND operation between the two values stored in the fuzzy stack, previously loaded with LDP, LDN or LDK instructions, and stores it in the register K. 65/99 ST52T301/E301 FZOR Fuzzy OR Format: FZOR Operation: K <- stack0 OR stack1 Description: This instruction computes the OR operation between the two values stored in the fuzzy stack, previously loaded with LDP, LDN or LDK instructions and stores it in the register K. 66/99 ST52T301/E301 IRQ Interrupt Vector Format: IRQ int label Operation: interrupt vector <- label (PC = Program Counter) Description: This instruction allows to specify the interrupt int service routine start address at label location. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: The instruction: IRQ 1 IntRout1 determinates that if interrupt 1 is serviced, the program counter (PC) is loaded with the memory address value labelled with IntRout1. The instruction IRQ is a dummy instruction used to store data in the chip memory. It is neither stored in memory nor executed.A series of IRQ instructions must be ended by a dummy end operation. Remark: 67/99 ST52T301/E301 IRQM Mask Interrupt Format: IRQM mask Operation: interrupt mask register <- mask Description: The interrupts are masked with the specified mask. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: The instruction: IRQM 10 1011|1110 00001010 enables the interrupts 1 and 3 and disables all the others. 68/99 ST52T301/E301 IRQP Interrupt Priority Format: IRQP cost Operation: interrupt priority register <- cost Description: The interrupts priority is set according the specified values. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: The instruction: IRQP 198 1011|1111 11|00|01|10 determines the interrupt 2 to have highest priority, interrupt 1 medium priority and interrupt 0 lower priority. Remark: each couples of bits must have different values, that is interrupts must have different priority level.enables the interrupts 1 and 3 and disables all the others. 69/99 ST52T301/E301 JP Unconditional Jump Format: JP addr Operation: PC <- addr (PC = Program Counter) Description: The instruction replaces the PC value with the specified value causing an unconditional jump to another location in the program memory. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: The instruction: JP 1123 1010|0100 01100011 causes the PC to be loaded with the value 1123 and the program to continue from that location. 70/99 ST52T301/E301 JPNS Jump on Non Sign Flag Format: JPNS addr Operation: if S=0, PC <- addr (PC = Program Counter) Description: If the S flag is cleared then the PC value is replaced with the specified value, causing a jump to another location in the program memory. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: If the S flag is cleared then the instruction: JPNS 1123 1111|0100 01100011 causes the PC to be loaded with the value 1123 and the program to continue from that location. 71/99 ST52T301/E301 JPNZ Jump on Non Zero Flag Format: JPNZ addr Operation: if Z=0, PC <- addr (PC = Program Counter) Description: If the Z flag is cleared then the PC value is replaced with the specified value, causing a jump to another location in the program memory. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: If the Z flag is cleared then the instruction: JPNZ 1123 1101|0100 01100011 causes the PC to be loaded with the value 1123 and the program to continue from that location. 72/99 ST52T301/E301 JPS Jump on Sign Flag Format: JPS addr Operation: if S=1, PC <- addr (PC = Program Counter) Description: If the S flag is set then the PC value is replaced with the specified value, causing a jump to another location in the program memory. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: If the S flag is set then the instruction: JPS 1123 1110|0100 01100011 causes the PC to be loaded with the value 1123 and the program to continue from that location. 73/99 ST52T301/E301 JPZ Jump on Zero Flag Format: JPZ addr Operation: if Z=1, PC <- addr (PC = Program Counter) Description: If the Z flag is set then the PC value is replaced with the specified value, causing a jump to another location in the program memory. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: If the Z flag is set then the instruction: JPZ 1123 1110|0100 01100011 causes the PC to be loaded with the value 1123 and the program to continue from that location. 74/99 ST52T301/E301 LDCF Load Constant into Configuration Register Format: LDCF conf, const Operation: conf <- const Description: The immediate constant value (const) specified as source is loaded into the destination peripheral configuration register (conf). Flags: Z,S not affected. Bytes: 2 Cycles: Example: 6 The instruction: LDCF 5,43 1011|0101 00101011 causes the peripheral configuration register 5 to be loaded with the value 43. 75/99 ST52T301/E301 LDK Load Stack with K register Format: LDK Operation: stack0 <- K Description: This instruction loads in the stack the value temporarily stored in the register K that is the result of the last fuzzy operation. 76/99 ST52T301/E301 LDM Load Stack with M register Format: LDM Operation: stack0 <- M Description: This instruction loads in the stack the value temporarily stored in the register M with a SKM operation. 77/99 ST52T301/E301 LDN Load Negative alpha value Format: LDN var mbf Operation: stack <- 15 - computed alpha value related to mbf M.F. of var Variable Description: This instruction performs the fuzzyfication and loads in the stack the negated alpha value of the M.F. mbf of var Variable. 78/99 ST52T301/E301 LDP Load Positive alpha value Format: LDP var mbf Operation: stack <- computed alpha value related to mbf M.F. of var Variable Description: This instruction performs the fuzzyfication and loads in the stack the alpha value of the M.F. mbf of var Variable. 79/99 ST52T301/E301 LDPR Load Register into Peripheral Register Format: LDPR per, reg Operation: per <- reg Description: The contents register specified as source (reg) is loaded into the destination peripheral register (per). Flags: Z, S not affected. Bytes: 1 Cycles: 5 (6 if parallel port with H/S is addressed) Example: If the register 7 of the Register File contains the value 25 then the instruction: LDPR 2,7 01|10|0111 causes the register 2 of the Peripheral Register (i.e. parallel port) to be loaded with the value 25. 80/99 ST52T301/E301 LDRC Load constant into Register Format: LDRC reg, const Operation: reg <- const Description: The immediate constant value specified as source is loaded into the destination register in the Register File. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: The instruction: LDRC 5,43 1000|0101 00101011 causes the register 5 of the Register File to be loaded with the value 43. 81/99 ST52T301/E301 LDRI Load Input register into Register file Format: LDRI reg, inp Operation: reg <- inp Description: The contents of a input register specified as source (inp) is loaded into the destination register in the Register File (reg). Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: If the register 2 of the A/D converter contains the value 25 then the instruction: LDRI 5,2 000|xxxxx 0101|0010 x = don’t care causes the register 5 of the Register file to be loaded with the value 25. 82/99 ST52T301/E301 LDRR Load Register into Register Format: LDRR regi, regj Operation: regj <- regi Description: The contents of the Register File j-th register specified as source is loaded into the destination i-th register. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: If the register 2 of the Register File contains the value 25 then the instruction: LDRR 5,2 100101100101|0010 causes the register 5 of the Register file to be loaded with the value 25. 83/99 ST52T301/E301 MDGI Macro Disable Global Interrupt Format: MDGI Operation: MGI bit <- 0 Description: All the interrupts are disabled by this instruction. This instruction is used by FUZZYSTUDIO 3.0 Compiler macros to disable interrupt during macro execution. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: After the instruction: MDGI 10011010 all the interrupts cannot be acknowledged and remain pending 84/99 ST52T301/E301 MEGI Macro Enable Global Interrupt Format: MDGI Operation: MGI bit <- 1 Description: The not masked interrupts are enabled by this instruction only if a UDGI instruction has not specified before, not followed by a UEGI instruction. This instruction is used by FUZZYSTUDIO 3.0 Compiler macros to disable interrupt during macro execution. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: After the instruction: MEGI 10011011 not masked interrupts can be acknowledged if the interrupts are not globally disabled by the UDGI instruction 85/99 ST52T301/E301 OUT Output computation Format: OUT const Operation: Output Register const <- defuzzyfication result of the const output Description: This instruction performs the defuzzyfication of the specified output (const can assume only the values 0 or 1) and loads in the correspondent Fuzzy Output Register the result. 86/99 ST52T301/E301 RETI Return from Interrupt Format: RETI Operation: PC <- stack Z <- stack S <- stack Description: This instruction resumes the program execution exactly at the point it was left when an interrupt occurred. Z and S flag are set to the status they had when the interrupt service routine was started. Flags: Z,S restored to the original setting before an interrupt occured. Bytes: 1 Cycles: 5 Example: If the PC stack contains the value 1123 and the program is processing an interrupt service routine, then the instruction RETI 10010101 causes the PC to be loaded with the value 1123 and the flags to be restored to the status before the interrupt occurred. 87/99 ST52T301/E301 RINT Reset Interrupt Format: RINT int Operation: cancel pending interrupt n. int Description: The specified pending interrupt is cancelled if not currently in service. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: The instruction: RINT 2 0001|x|010 x = don’t care causes the bit 2 of the interrupt pending register to be cleared so that the interrupt 2 is not acknowledged. Remark: 88/99 The use of RINT istruction has no effect if a specified interrupt has already been aknowledged and related service routine has not been completed. ST52T301/E301 SKM Store K register in M register Format: SKM Operation: M <- K Description: This instruction stores the result of the last performed fuzzy operation (stored in the temporary register K) in the temporary buffer M. 89/99 ST52T301/E301 SRX SCI Reception Format: SRX regi Operation: regi <- SCDR_RX Description: The contents of the SCDR_RX block of the SCI receiver block, is transferred in the Register File i-th register specified as destination. Flags: Z,S not affected. Bytes: 2 Cycles: 5 Example: If the SCDR_RX block of the SCI receiver block contains the value 45, then the instruction SRX 4 00101101 causes the register 4 of the Register File to be loaded with the value 45. 90/99 ST52T301/E301 STOP Stop Program Execution Format: STOP Operation: Stop section Description: This instruction separates arithmetic instructions and fuzzy instructions. Also it ends a IRQ specification section. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: The instruction: STOP 10010111 if put after arithmetic instructions, it allows to start a block of fuzzy instruction and vice versa. 91/99 ST52T301/E301 STX SCI Transmission Format: STX regi Operation: SCDR_TX <- regi Description: The contents of the Register File i-th register specified as source is transferred in the SCDR_TX block of the SCI transmitter block, to be transmitted. Flags: Z,S not affected. Bytes: 2 Cycles: 5 Example: If the register 4 contains the value 45, then the instruction STX 4 00101101 causes the serial transmission of 45. 92/99 ST52T301/E301 SUB Subtraction Format: SUB regi, regj Operation: regi <- regi -regj Description: The contents of the Register File j-th register specified as source is subtracted from the destination i-th register, leaving the result in the destination register. Flags: Z set if result is zero, cleared otherwise. S set if underflow, cleared otherwise. Bytes: 2 Cycles: 7 Example: If the register 4 contains the value 45 and the register 11 contains the value 15, then the instruction SUB 4,11 10010010 0100|1011 causes the register 4 of the Register File to be loaded with the value 30. If the register 4 contains the value 100 and the register 11 contains the value 200, the instruction causes the register 4 to be loaded with the value 156 (result+256) and the S flag to be set. 93/99 ST52T301/E301 SUBO Subtraction with Offset Format: SUBO regi, regj Operation: regi <- regi - regj +128 Description: The contents of the Register File register specified as source are subtracted from the destination register in the Register File, the value 128 is added to the result that is stored in the destination register. This operation allows the use of the signed byte considering the values between 0 and 127 as negative, 128 as 0, and the values between 129 and 255 as positive. Flags: Z set if result is zero or if overflow occurs, cleared otherwise. S set if underflow or overflow, cleared otherwise. Bytes: 2 Cycles: 7 Example: If the register 4 contains the value 45 and the register 11 contains the value 15, then the instruction SUBO 4,11 10010011 0100|1011 causes the register 4 of the Register File to be loaded with the value 158. The value 45 corresponds to -83, the value 11 corresponds to -113; so the operation is equivalent to perform -83 - (-113) = 30. As a matter of fact the result 158 corresponds to the value 30. If the register 4 contains the value 50 and the register 11 contains the value 200, the instruction causes the register 4 to be loaded with the value 234 (result+256) and the S flag to be set. If the register 4 contains the value 200 and the register 11 contains the value 50, the instruction causes the register 4 to be loaded with the value 22 (result-256) and the S and Z flags to be set. 94/99 ST52T301/E301 UDGI User Disable Global Interrupt Format: UDGI Operation: UGI bit <- 0 Description: All the interrupt are disabled by this instruction. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: After the instruction: UDGI 10011000 all the interrupts cannot be acknowledged and remain pending. 95/99 ST52T301/E301 UEGI User Enable Global Interrupt Format: UEGI Operation: UGI bit <- 1 Description: All the interrupts are enabled by this instruction. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: After the instruction: UEGI 10011001 not masked interrupts can be acknowledged if the interrupt are not globally disabled by the MDGI instruction. 96/99 ST52T301/E301 WAITI Wait for interrupt Format: WAITI Operation: Wait state Description: This instruction causes the program to stop, without halting the peripherals, until an interrupt occurs.. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: The instruction: WAITI 10010100 halts the program execution leaving the peripherals running on, until an interrupt occurs. 97/99 ST52T301/E301 CLCC44 PACKAGE MECHANICAL DATA mm DIM MIN inch. MAX MIN TYP MAX A 17.27 17.78 .680 .662 B 16.33 16.81 .643 .662 C 12.01 .475 C1 13.03 .513 c1 1.30 0.52 D 1.82 d1 E 2.23 0.72 0.889 d2 98/99 TYP 2.362 16.26 .088 .035 .093 16.76 .640 .660 e 1.27 .050 e3 12.50 .500 F 0.431 .017 F1 0.762 .030 F2 0.965 .038 M 0.508 .020 M1 1.016 .040 R 0.762 .030 ST52T301/E301 PLCC44 PACKAGE MECHANICAL DATA mm DIM MIN TYP inch. MAX MIN TYP MAX A 17.4 17.65 0.685 0.695 B 16.51 16.65 0.650 0.656 C 3.65 3.7 0.144 1.146 D 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 16 0.590 d2 E 0.68 14.99 0.027 0.630 e 1.27 0.050 e3 1.27 0.500 F 0.46 0.018 F1 0.71 0.028 G 0.101 0.004 M 1.16 0.046 M1 1.14 0.045 99/99 ST52T301/E301 ORDERING INFORMATION PART NUMBER PACKAGE ST52E301/C CLCC44-W ST52T301/P PLCC44 Full Product Information at http://www.st.com Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lifesupport devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1998 STMicroelectronics – Printed in Italy – All Rights Reserved FUZZYSTUDIO is a registered trademark of STMicroelectronics DuaLogic is a trademark of STMicroelectronics MS-DOS, Microsoft and Microsoft Windows are registered trademarks of Microsoft Corporation. MATLAB is a registered trademark of Mathworks Inc. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.