TDA7266P 3+3W DUAL BRIDGE AMPLIFIER PRODUCT PREVIEW 1 ■ ■ ■ ■ ■ ■ ■ ■ FEATURES TECHNOLOGY BI20II WIDE SUPPLY VOLTAGE RANGE (3.5 - 12V) OUTPUT POWER: – 3+3W @THD = 10%, RL = 8Ω, VCC = 7.5V – 4+4W Music Power @THD = 10%, RL = 8Ω, VCC = 8.5V SINGLE SUPPLY MINIMUM EXTERNAL COMPONENTS: – NO SVR CAPACITOR – NO BOOTSTRAP – NO BOUCHEROT CELLS – INTERNALLY FIXED GAIN STAND-BY & MUTE FUNCTIONS SHORT CIRCUIT PROTECTION THERMAL OVERLOAD PROTECTION Figure 1. Package PowerSSO24 (Slug Down) Table 1. Order Codes Part Number Package TDA7266P PowerSSO24 (Slug Down) 2 DESCRIPTION The TDA7266P is a dual bridge amplifier specially designed for LCD TV/Monitor, PC Motherboard, TV and Portable Audio applications. Figure 2. Test and Application Diagram VCC C3 0.22µF +5V S-GND ST-BY 7 8 + 5 OUT1+ 6 OUT1- 20 OUT2+ 19 OUT2- C2 100nF C7 100nF 14 R3 10K 11 C4 10µF Vref C5 0.22µF IN2 MUTE C1 470µF 18 17 R4 10K 10 + + - C6 1µF 1 PW-GND 24 + D03AU1531A July 2004 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. REV. 2 1/12 TDA7266P Table 2. Absolute Maximum Ratings Symbol Parameter Value Unit Vs Supply Voltage 20 V IO Output Peak Current (internally limited) 1.5 A Top Operating Temperature 0 to 70 °C -40 to 150 °C Tstg, Tj Storage and Junction Temperature Figure 3. Pin Connection (Top view) PW GND 1 24 PW GND N.C. 2 23 N.C. N.C. 3 22 N.C. N.C. 4 21 N.C. OUT1+ 5 20 OUT2+ OUT1- 6 19 OUT2- +VS 7 18 +VS IN1 8 17 IN2 N.C. 9 16 N.C. MUTE 10 15 N.C. STBY 11 14 SGND N.C. 12 13 N.C. D03AU1532 Table 3. Themal Data Symbol R th j-case 2/12 Parameters Thermal Resistance Junction to Case Typ. Value Unit 1.5 °C/W TDA7266P Table 4. Electrical Characteristcs (Refer to test circuit; VCC = 7.5V, RL = 8Ω, f = 1KHz, Tamb = 25°C unless otherwise specified) Symbol VCC Iq Parameter Supply Range Min. Output Offset Voltage PO Output Power PO Output Music Power (*) Total Harmonic Distortion Typ. 3.5 Total Quiescent Current VOS THD Test Condition CT AMUTE Supply Voltage Rejection 120 THD 10% PO = 1W f = 100Hz, VR =0.5V mV 3 W 4 W 0.03 0.2 % 1 % Crosstalk 46 60 dB Mute Attenuation 60 80 dB 150 °C Closed Loop Voltage Gain 25 26 Voltage Gain Matching Ri Input Resistance VTMUTE Mute Threshold eN mA dB GV IST-BY V 56 Thermal Threshold VTST-BY 12 40 Tw ∆GV Unit 40 PO = 0.1W to 2W f = 100Hz to 15KHz SVR Max. dB 0.5 dB 25 30 for VCC > 6.4V; Vo = -30dB 2.3 2.9 4.1 V for VCC < 6.4V; Vo = -30dB VCC/2 -1 VCC/2 -0.75 VCC/2 -0.5 V 0.8 1.3 1.8 V 100 µA St-by Threshold St-by Current V6 = GND Total Output Voltage 27 A Curve 150 KΩ µV (*) Measured on demoboard of figure 8 with gaussian noise signal which simulates Music/Speech programmes. 3/12 TDA7266P 3 APPLICATIVE SUGGESTIONS 3.1 STAND-BY AND MUTE FUNCTIONS 3.1.1 (A) Microprocessor Application In order to avoid annoying "Pop-Noise" during Turn-On/Off transients, it is necessary to guarantee the right Stby and mute signals sequence.It is quite simple to obtain this function using a microprocessor (Fig. 4 and 5). At first St-by signal (from µP) goes high and the voltage across the St-by terminal (Pin 11) starts to increase exponentially. The external RC network is intended to turn-on slowly the biasing circuits of the amplifier, this to avoid "POP" and "CLICK" on the outputs. When this voltage reaches the St-by threshold level, the amplifier is switched-on and the external capacitors in series to the input terminals (C1, C3) start to charge. It's necessary to mantain the mute signal low until the capacitors are fully charged, this to avoid that the device goes in play mode causing a loud "Pop Noise" on the speakers. A delay of 100-200ms between St-by and mute signals is suitable for a proper operation. Figure 4. Microprocessor Application VCC C1 0.22µF IN1 7 8 + 5 C5 470µF OUT1+ 6 OUT1- 20 OUT2+ 19 OUT2- 18 - ST-BY R1 10K 11 C2 10µF S-GND µP 14 Vref C3 0.22µF IN2 MUTE R2 10K 17 + + - 10 C4 1µF PW-GND 1 - 24 + D03AU1533 4/12 C6 100nF TDA7266P Figure 5. Microprocessor Driving Signals +VS(V) +7.5 VIN (mV) VST-BY pin 11 1.8 1.3 0.8 VMUTE pin 10 4.1 2.9 2.3 Iq (mA) VOUT (V) OFF ST-BY PLAY MUTE MUTE ST-BY OFF D03AU1535A 3.1.2 B) Low Cost Application In low cost applications where the µP is not present, the suggested circuit is shown in fig.6. The St-by and mute terminals are tied together and they are connected to the supply line via an external voltage divider. The device is switched-on/off from the supply line and the external capacitor C4 is intended to delay the St-by and mute threshold exceeding, avoiding "Popping" problems. So to avoid any popping or clicking sond, it is important to clock: a Correct Sequence: At turn-ON, the Stand-by must be removed at first, then the Mute must be released after a delay of about 100-200ms. On the contrary at turn-OFF the Mute must be activated as first and then the Stand-by. With the values suggested in the Application circuit the right operation is guaranteed. b Correct Threshold Voltages: In order to avoid that due to the spread in the internal thresholds (see the above limits) a wrong external voltage causes uncertain commutations for the two functions we suggest to use the following values: Mute for Vcc>6.4V : VT = 2.3V Mute for Vcc<6.4V : VT = Vcc/2 - 1 Stand-by : VT = 0.8V 5/12 TDA7266P Figure 6. Stand-alone low-cost Application VCC C3 0.22µF R1 24K 5 C1 470µF OUT1+ 6 OUT1- 20 OUT2+ 19 OUT2- 18 + IN1 ST-BY R2 47K 7 8 C2 100nF C7 100nF 11 C4 10µF S-GND 14 - Vref C5 0.22µF + 17 + IN2 - MUTE PW-GND 10 1 - 24 + D03AU1534A Figure 7. Application Circuit VCC R1 +5V JP1 C3 0.22µF R2 IN1 S-GND ST-BY 7 8 + 5 OUT1+ 6 OUT1- 20 OUT2+ 19 OUT2- 14 R3 10K 11 C4 10µF Vref C5 0.22µF IN2 MUTE C1 470µF 18 17 R4 10K 10 + + - C6 1µF 1 PW-GND 24 + D03AU1551 6/12 C2 100nF C7 100nF TDA7266P Figure 8. PCB Component Layout Figure 9. PCB Copper Top (Top view) Figure 10. PCB Copper Bottom (Top view) 7/12 TDA7266P 4 PCB LAYOUT AND EXTERNAL COMPONENTS Regarding the PCB layout care must be taken for three main subjects: 1) Signal and Power Gnd separation 2) Dissipating Copper Area 3) Filter Capacitors positioning 1) Signal and Power Gnd separation: To the Signal GND must be referred the Audio Input Signals, the Mute and Stand-by Voltages and the device PIN.14. This Gnd path must be as clean as possible in order to improve the device THD+Noise and to avoid spurious oscillations across the speakers. The Power GND is directly connected to the Output power Stage transistors (Emitters) and is crossed by large amount of current, this path is also used in this device to dissipate the heating generated (no needs of external heatsinker). Referring to the typical application circuit, the separation between the two GND paths must be obtained connecting them separately (star routing) to the bulk Electrolithic capacitor C1 (470µF). Regarding the Power Gnd dimensioning we have to consider the Dissipated Power the Thermal Protection Threshold and the Package thermal Characteristics. 2) Dissipating Copper Area: Dissipated Power: The max dissipated power happens for a THD near 1% and is given by the formula: 2 V CC P dmax ( W ) = 2 ⋅ -------------- + Iq V CC 2 Rl π -----2 This gives for: Vcc = 7.5V, Rl = 8Ω ,Iq = 40mA a dissipated power of Pd = 3W. Thermal Protection: The thermal protection threshold is placed at a junction temperature of 150°C. Package Thermal Characteristics: The thermal resistance Junction to Ambient obtainable with a GND copper Area of 3x3 cm and with 16 via holes (see picture) is about 25°C/W. This means that with the above mentioned max dissipated Power (Pd=3W) we can expect a 75°C, this gives a safety margin before the thermal protection intervention in the consumer environments where a 50°C ambient is specified as maximum Figure 11. 3)Filter Capacitors Positioning: The two Ceramic capacitors C2/C7 (100nF) must be placed as close as possible respectively to the two Vcc pins ( 7 - 18) in order to avoid the possibiltiy of oscillations arising on the output Audio signals. 8/12 TDA7266P 5 TYPICAL CHARACTERISTICS (Referred to application circuit of figure 8 unless otherwise specified) Figure 15. Gain vs Frequency Figure 12. Distortion vs Frequency Level(dBr) THD(%) 5.0000 10 4.0000 Vcc = 7.5V Rl = 8 ohm Pout = 1W 3.0000 Vcc = 7.5V Rl = 8 ohm 1 2.0000 1.0000 0.0 -1.000 Pout = 100mW 0.1 -2.000 -3.000 Pout = 2W -4.000 -5.000 0.010 100 1k 10 20k 10k 100 1k 10k 100k frequency (Hz) frequency (Hz) Figure 16. Mute Attenuation vs Vpin.10 Figure 13. Distortion vs Output Power % 10 5 2 Attenuation (dB) 10 Vs= 7.5V Rl= 8 Ohm F= 1 KHz 0 -10 -20 1 -30 0.5 -40 -50 0.2 -60 0.1 -70 0.05 -80 -90 0.02 -100 0.01 100m 200m 300m 400m500m W 700m 1 2 3 1 2.5 3 3.5 4 4.5 5 Vpin.10(V) Attenuation (dB) % 10 5 Vs= 8 .5V Rl= 8 Ohm F= 1 KHz 1 0.5 0.2 0.1 0.05 0.02 0.01 100m 2 Figure 17. Stand-By attenuation vs Vpin 11 Figure 14. Distortion vs Output Power 2 1.5 200m 300m 400m 600m 800m W 1 2 3 4 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 Vpin.11 (V) 9/12 TDA7266P Figure 18. PowerSSO24 Mechanical Data & Package Dimensions DIM. mm MIN. TYP. inch MAX. MIN. 2.47 0.084 TYP. MAX. A 2.15 A2 2.15 2.40 0.084 0.094 a1 0 0.075 0 0.003 b 0.33 0.51 0.013 0.020 c D (1) E (1) 0.23 0.32 0.009 0.012 10.10 10.50 0.398 0.413 7.4 7.6 0.291 0.299 e 0.8 e3 8.8 G h L 0.346 0.004 0.06 10.10 10.50 0.002 0.398 0.40 0.55 N OUTLINE AND MECHANICAL DATA 0.031 0.10 G1 H 0.097 0.85 0.413 0.016 0.022 0.033 10˚ (max) X 4.10 4.70 0.161 0.185 Y 6.50 7.10 0.256 0.279 (1) “D and E1” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”) (2) No intrusion allowed inwards the leads. (3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side PowerSSO24 7412828 A 10/12 TDA7266P Table 5. Revision History Date Revision Description of Changes May 2004 1 First Issue July 2004 2 Electrical Characteristics: Deleted TYP. Value VCC 11/12 TDA7266P Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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