IKSEMICON IL44608

TECHNICAL DATA
External Components Reliable
and Flexible SMPS Controller
IL44608
DESCRIPTION
The IL44608N is a high performance voltage mode controller
designed for off–line converters. This high voltage circuit that integrates the start–up current source and the oscillator capacitor, requires few external components while offering a high flexibility and
reliability.
The device also features a very high efficiency stand–by management consisting of an effective Pulsed Mode operation. This
technique enables the reduction of the stand–by power consumption
to approximately 1.0 W while delivering 300 mW in a 150 W
SMPS.
● Integrated Start–Up Current Source
● Lossless Off–Line Start–Up
● Direct Off–Line Operation
● Fast Start–Up
PACKAGE
PDIP-8
General Features
● Flexibility
● Duty Cycle Control
● Under-voltage Lockout with Hysteresis
● On Chip Oscillator Switching Frequency 40, 75, or 100 kHz
● Secondary Control with Few External Components
Pin Connection
Protections
● Maximum Duty Cycle Limitation
● Cycle by Cycle Current Limitation
● Demagnetization (Zero Current Detection) Protection
● “Over VCC Protection” Against Open Loop
● Programmable Low Inertia Over Voltage Protection
against Open Loop
● Internal Thermal Protection
SMPS Controller
● Pulsed Mode Techniques for a Very High Efficiency
Low Power Mode
● Lossless Startup
● Low dV/dT for Low EMI Radiations
Ordering Information
Device
Switching Frequency
IL44608N40
40 kHz
IL44608N75
75 kHz
IL44608N100
100 kHz
Package
Plastic
DIP–8
Plastic
DIP–8
Plastic
DIP–8
2011, February, Rev. 01
IL44608N
PIN FUNCTION DESCRIPTION
Pin
Symbol
1
Demag
2
Isense
3
Control
Input
4
5
Ground
Driver
6
VСС
7
8
Vi
Function
The Demag pin offers 3 different functions: Zero voltage crossing detection (50 mV), 24 μA current detection and 120 μA current detection. The 24 μA level is used to detect the secondary reconfiguration status and the 120 μA level to detect an Over Voltage status called Quick OVP.
The Current Sense pin senses the voltage developed on the series resistor inserted in the source of
the power MOSFET. When Isense reaches 1.0 V, the Driver output (pin 5) is disabled. This is
known as the Over Current Protection function. A 200 μA current source is flowing out of the pin
3 during the start–up phase and during the switching phase in case of the Pulsed Mode of operation. A resistor can be inserted between the sense resistor and the pin 2, thus a programmable peak
current detection can be performed during the SMPS stand–by mode.
A feedback current from the secondary side of the SMPS via the opto–coupler is injected into this
pin. A resistor can be connected between this pin and GND to allow the programming of the Burst
duty cycle during the Stand–by mode.
This pin is the ground of the primary side of the SMPS.
The current and slew rate capability of this pin are suited to drive Power MOSFETs.
This pin is the positive supply of the IC. The driver output gets disabled when the voltage becomes higher than 15 V and the operating range is between 6.6 V and 13 V. An intermediate voltage level of 10 V creates a disabling condition called Latched Off phase.
This pin is to provide isolation between the Vi pin 8 and the VCC pin 6.
This pin can be directly connected to a 500 V voltage source for start–up function of the IC. During the Start–up phase a 9.0 mA current source is internally delivered to the VCC pin 6 allowing a
rapid charge of the VCC capacitor. As soon as the IC starts–up, this current source is disabled.
Figure 1. Representative Block Diagram
2011, February, Rev. 01
IL44608N
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Total Power Supply Current
ICC
30
mA
Output Supply Voltage with Respect to Ground
VCC
16
V
All Inputs except Vi
Vinputs
–1.0 to +16
V
Line Voltage Absolute Rating
Vi
500
V
Recommended Line Voltage Operating Condition
Vi
400
V
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation at TA = 85°C
PD
600
mV
Thermal Resistance, Junction–to–Air
RQJA
100
ºC/W
Operating Junction Temperature
TJ
150
ºC
Operating Ambient Temperature
TA
–25 to +85
ºC
* Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS(VCC = 12 V, for typical values TA = 25°C, for min/max values TA = –25°C to +85°C unless otherwise
noted)
Characteristic
OUTPUT SECTION
Output Resistor
Sink Resistance
Source Resistance
Output Voltage Rise Time (from 3.0 V up to 9.0 V) (Note 1.)
Output Voltage Falling Edge Slew–Rate (from 9.0 V down to 3.0 V)
(Note 1.)
CONTROL INPUT SECTION
Duty Cycle @ Ipin3 = 2.5 mA
Duty Cycle @ Ipin3 = 1.0 mA
Control Input Clamp Voltage (Switching Phase) @ Ipin3 = –1.0 mA
Latched Phase Control Input Voltage (Stand–by) @ Ipin3 = +500 _A
Latched Phase Control Input Voltage (Stand–by) @ Ipin3 = +1.0 mA
CURRENT SENSE SECTION
Maximum Current Sense Input Threshold
Input Bias Current
Stand–By Current Sense Input Current
Start–up Phase Current Sense Input Current
Propagation Delay (Current Sense Input to Output @ VTH T MOS = 3.0 V)
Leading Edge Blanking Duration
Leading Edge Blanking Duration
Leading Edge Blanking Duration
Leading Edge Blanking + Propagation Delay
Leading Edge Blanking + Propagation Delay
Leading Edge Blanking + Propagation Delay
OSCILLATOR SECTION
Normal Operation Frequency
Normal Operation Frequency
Normal Operation Frequency
Maximum Duty Cycle @ f = fosc
OVERVOLTAGE SECTION
Quick OVP Input Filtering (Rdemag = 100 k Ω)
Propagation Delay (Idemag > Iovp to output low)
Quick OVP Current Threshold
Protection Threshold Level on VCC
Minimum Gap Between VCC–OVP and Vstup–th
IL44608N40
IL44608N75
IL44608N100
IL44608N40
IL44608N75
IL44608N100
IL44608N40
IL44608N75
IL44608N100
Symbol
Min
Typ
Max
Unit
ROL
ROH
tr
5.0
-
8.5
15
50
15
-
Ω
ns
tf
-
50
-
ns
d2mA
d1mA
36
4.75
3.4
3.4
-
2.0
48
5.25
4.3
3.7
%
%
V
V
V
TPLH(In/Out)
TLEB
TLEB
TLEB
TDLY
TDLY
TDLY
0.95
-1.8
180
180
500
370
300
220
480
250
200
-
1.05
1.8
220
220
900
570
500
V
μA
μA
μA
ns
ns
ns
ns
ns
ns
ns
fosc
fosc
fosc
dmax
36
68
90
78
-
44
82
110
86
kHz
kHz
kHz
%
Tfilt
TPHL(In/Out)
IOVP
VCC–OVP
VCC–OVP – Vstup
105
14.8
1.0
250
2.0
-
140
15.8
-
ns
μs
μA
V
V
VLP–stby
VLP–stby
VCS–th
IB–cs
ICS–stby
ICS–stup
NOTE 1: This parameter is measured using 1.0 nF connected between the output and the ground.
2011, February, Rev. 01
IL44608N
ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = 25°C, for min/max values TA = –25°C to +85°C unless otherwise noted) (Note2 )
Characteristic
DEMAGNETIZATION DETECTION SECTION (Note 3.)
Demag Comparator Threshold (Vpin1 increasing)
Demag Comparator Hysteresis (Note 4.)
Propagation Delay (Input to Output, Low to High)
Input Bias Current (Vdemag = 50 mV)
Negative Clamp Level (Idemag = –1.0 mA)
Positive Clamp Level @ Idemag = 125 μA
Positive Clamp Level @ Idemag = 25 μA
OVERTEMPERATURE SECTION
Trip Level Over Temperature
Hysteresis
STAND–BY MAXIMUM CURRENT REDUCTION SECTION
Normal Mode Recovery Demag Pin Current Threshold
K FACTORS SECTION FOR PULSED MODE OPERATION
ICCS / Istup
IL44608N40
ICCS / Istup
IL44608N75
ICCS / Istup
IL44608N100
ICCL / Istup
(Vstup – UVLO2) / (Vstup – UVLO1)
(UVLO1 – UVLO2) / (Vstup – UVLO1)
ICS / Vcsth
Demag ratio Iovp / Idem NM
(V3 1.0 mA – V3 0.5 mA) / (1.0 mA – 0.5 mA)
Vcontrol Latch–off
SUPPLY SECTION
Minimum Start–up Voltage
VCC Start–up Voltage
Output Disabling VCC Voltage After Turn On
Hysteresis (Vstup–th – Vuvlo1)
VCC Undervoltage Lockout Voltage
Hysteresis (Vuvlo1 – Vuvlo2)
Absolute Normal Condition VCC Start Current @ (Vi = 100 V) and
(VCC = 9.0 V)
Switching Phase Supply Current (no load)
IL44608N40
IL44608N75
IL44608N100
Latched Off Phase Supply Current
Hiccup Mode Duty Cycle (no load)
Symbol
Min
Typ
Max
Unit
Vdmg–th
Hdmg
30
-0.6
-0.9
30
300
-
69
-0.4
mV
mV
ns
μA
V
2.05
-
2.8
V
1.4
-
1.9
V
Thigh
Thyst
-
160
30
-
ºC
ºC
Idem–NM
20
-
30
μA
10 x K1
10 x K1
10 x K1
103 x K2
102 x Ksstup
102 x Ksl
106 x Ycstby
Dmgr
R3
V3
2.4
2.8
3.1
46
1.8
90
175
3.0
-
1800
4.8
3.8
4.2
4.5
63
2.6
150
225
5.5
-
Ω
V
Vilow
Vstup–th
Vuvlo1
Hstup–uvlo1
Vuvlo2
Huvlo1–uvlo2
12.5
9.5
6.2
-
3.1
3.4
50
13.8
10.5
7.0
-
V
V
V
V
V
V
–(ICC)
7.0
-
12.8
mA
2.0
2.4
2.6
0.3
-
10
3.6
4.0
4.5
0.68
-
tPHL(In/Out)
Idem–lb
Vcl–neg–dem
Vcl–pos–
dem–H
Vcl–pos–
dem–L
ICCS
ICC–latch
_Hiccup
mA
mA
%
NOTE 2 : Adjust VCC above the start–up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction
temperature as close to ambient as possible.
NOTE 3 : This function can be inhibited by connecting pin 1 to GND.
NOTE 4 : Guaranteed by design (non tested).
2011, February, Rev. 01
IL44608N
OPERATING DESCRIPTION
The pin 3 senses the feedback current provided by the
opto coupler. During the switching phase the switch S2 is
closed and the shunt regulator is accessible by the pin 3.
The shunt regulator voltage is typically 5.0 V. The dynamic resistance of the shunt regulator represented by the zener
diode is 20 Ω. The gain of the Control input is given on
Figure 11/, which shows the duty cycle as a function of the
current injected into the pin 3.
A 4.0 kHz filter network is inserted between the shunt
regulator and the PWM comparator to cancel the high frequency residual noise.
The switch S3 is closed in Stand–by mode during the
Latched Off Phase while the switch S2 remains open. (See
section PULSED MODE DUTY CYCLE CONTROL).
The resistor Rdpulsed (Rduty cycle burst) has no effect on
the regulation process. This resistor is used to determine
the burst duty cycle described in the chapter “Pulsed Duty
Cycle Control”
Current Sense
The inductor current is converted to a positive voltage
by inserting a ground reference sense resistor RSense in series with the power switch.
The maximum current sense threshold is fixed at 1.0 V.
The peak current is given by the following equation:
Ipk max =
1
(A)
R SENSE ( Ω )
In stand–by mode, this current can be lowered as due activation of a 200 μA current source:
Ipk max − stby =
PWM Latch
The IL44608 works in voltage mode. The on–time is
controlled by the PWM comparator that compares the oscillator sawtooth with the regulation block output (refer to
the block diagram on page 2).
The PWM latch is initialized by the oscillator and is reset by the PWM comparator or by the current sense comparator in case of an over current. This configuration ensures that only a single pulse appears at the circuit output
during an oscillator cycle.
1 - (R cs (kΩ) × 0,2)
(A)
R SENSE (Ω)
The current sense input consists of a filter (6.0 k Ω, 4.0
pF) and of a leading edge blanking. Thanks to that, this pin
is not sensitive to the power switch turn on noise and
spikes and practically in most applications, no filtering
network is required to sense the current.
Finally, this pin is used:
– as a protection against over currents (Isense > I)
– as a reduction of the peak current during a Pulsed
Mode switching phase.
The overcurrent propagation delay is reduced by producing
a sharp output turn off (high slew rate). This results in an
abrupt output turn off in the event of an over current and in
the majority of the pulsed mode switching sequence.
2011, February, Rev. 01
IL44608N
Demagnetization Section
The IL44608N demagnetization detection consists of a
comparator designed to compare the VCC winding voltage
to a reference that is typically equal to 50 mV.
This reference is chosen low to increase effectiveness
of the demagnetization detection even during start–up.
A latch is incorporated to turn the demagnetization
block output into a low level as soon as a voltage less than
50 mV is detected, and to keep it in this state until a new
pulse is generated on the output. This avoids any ringing
on the input signal which may alter the demagnetization
detection.
For a higher safety, the demagnetization block output is
also directly connected to the output, which is disabled
during the demagnetization phase.
The demagnetization pin is also used for the quick, programmable OVP. In fact, the demagnetization input current
is sensed so that the circuit output is latched off when this
current is detected as higher than 120 μA.
The complete demagnetization status DMG is used to
inhibit the recharge of the CT capacitor. Thus in case of
incomplete transformer demagnetization the next switching
cycle is postpone until the DMG signal appears. The oscillator remains at 2.4 V corresponding to the sawtooth valley
voltage. In this way the SMPS is working in the so called
SOPS mode (Self Oscillating Power Supply). In that case
the effective switching frequency is variable and no longer
depends on the oscillator timing but on the external working conditions (Refer to DMG signal in the Figure 6)
This function can be inhibited by grounding it but in
this case, the quick and programmable OVP is also disabled.
Oscillator
The IL44608 contains a fixed frequency oscillator. It
is built around a fixed value capacitor CT successively charged and discharged by two distinct current
sources ICH and IDCH. The window comparator
senses the CT voltage value and activates the sources
when the voltage is reaching the 2.4 V/4.0 V levels.
The OSC and Clock signals are provided according to
the Figure 6. The Clock signals correspond to the CT capacitor discharge. The bottom curve represents the current
flowing in the sense resistor Rcs. It starts from zero and
stops when the sawtooth value is equal to the control voltage Vcont. In this way the SMPS is regulated with a voltage mode control.
2011, February, Rev. 01
IL44608N
Overvoltage Protection
The IL44608 offers two OVP functions:
– a fixed function that detects when VCC is higher than
15.4 V
– a programmable function that uses the demag pin.
The current flowing into the demag pin is mirrored and
compared to the reference current Iovp (120 μA). Thus this
OVP is quicker as it is not impacted by the VCC inertia and
is called QOVP.
In both cases, once an OVP condition is detected, the
output is latched off until a new circuit START–UP.
Start–up Management
The Vi pin 8 is directly connected to the HV DC rail
Vin. This high voltage current source is internally connected to the VCC pin and thus is used to charge the VCC
capacitor. The VCC capacitor charge period corresponds to
the Start–up phase. When the VCC voltage reaches 13 V,
the high voltage 9.0 mA current source is disabled and the
device starts working. The device enters into the switching
phase.
It is to be noticed that the maximum rating of the Vi pin
8 is 500 V. ESD protection circuitry is not currently added
to this pin due to size limitations and technology constraints. Protection is limited by the drain–substrate junction in avalanche breakdown. To help increase the application safety against high voltage spike on that pin it is possible to insert a small wattage 1.0 k Ω series resistor between the Vin rail and pin 8.
The Figure 7 shows the VCC voltage evolution in case
of no external current source providing current into the
VCC pin during the switching phase. This case can be encountered in SMPS when the self supply through an auxiliary winding is not present (strong overload on the SMPS
output for example). The Figure 17 also depicts this working configuration. In case of the hiccup mode, the duty
cycle of the switching phase is in the range of 10%.
Mode Transition
The LW latch Figure 8 is the memory of the working
status at the end of every switching sequence.
Two different cases must be considered for the logic at
the termination of the SWITCHING PHASE:
1. No Over Current was observed
2. An Over Current was observed
These 2 cases are corresponding to the signal labeled
NOC in case of “No Over Current” and “OC” in case of
Over Current. So the effective working status at the end of
the ON time memorized in LW corresponds to Q=1 for no
over current and Q=0 for over current.
This sequence is repeated during the Switching phase.
Several events can occur:
1. SMPS switch OFF
2. SMPS output overload
3. Transition from Normal to Pulsed Mode
4. Transition from Pulsed Mode to Normal Mode
1. SMPS Switch off
When the mains is switched OFF, so long as the bulk
electrolithic bulk capacitor provides energy to the SMPS,
the controller remains in the switching phase. Then the
peak current reaches its maximum peak value, the switching frequency decreases and all the secondary voltages are
reduced. The VCC voltage is also reduced. When VCC is
equal to 10 V, the SMPS stops working.
2011, February, Rev. 01
IL44608N
2. Overload
In the hiccup mode the 3 distinct phases are described
as follows (refer to Figure 7):
The SWITCHING PHASE: The SMPS output is low
and the regulation block reacts by increasing the ON time
(dmax = 80%). The OC is reached at the end of every
switching cycle. The LW latch (Figure 8) is reset before
the VPWM signal appears. The SMPS output voltage is
low. The VCC voltage cannot be maintained at a normal
level as the auxiliary winding provides a voltage which is
also reduced in a ratio similar to the one on the output (i.e.
Vout nominal / Vout short–circuit). Consequently the VCC
voltage is reduced at an operating rate given by the combination VCC capacitor value together with the ICC working
consumption (3.2 mA) according to the equation 2. When
VCC crosses 10V the WORKING PHASE gets terminated.
The LW latch remains in the reset status.
The LATCHED–OFF PHASE: The VCC capacitor voltage continues to drop. When it reaches 6.5 V this phase is
terminated. Its duration is governed by equation 3.
The START–UP PHASE is reinitiated. The high voltage start–up current source (–ICC1 = 9.0 mA) is activated
and the MODE latch is reset. The VCC voltage ramps up
according to the equation 1. When it reaches 13 V, the IC
enters into the SWITCHING PHASE.
The NEXT SWITCHING PHASE: The high voltage
current source is inhibited, the MODE latch (Q=0) activates the NORMAL mode of operation. Figure 3 shows
that no current is injected out pin 2. The over current sense
level corresponds to 1.0 V.
As long as the overload is present, this sequence repeats.
The SWITCHING PHASE duty cycle is in the range of
10%.
3. Transition from Normal to Pulsed Mode
In this sequence the secondary side is reconfigured (refer to the typical application schematic on page 13). The
high voltage output value becomes lower than the NORMAL mode regulated value. The TL431 shunt regulator is
fully OFF. In the SMPS stand–by mode all the SMPS outputs are lowered except for the low voltage output that
supply the wake–up circuit located at the isolated side of
the power supply. In that mode the secondary regulation is
performed by the zener diode connected in parallel to the
TL431.
The secondary reconfiguration status can be detected
on the SMPS primary side by measuring the voltage level
present on the auxiliary winding Laux. (Refer to the Demagnetization Section). In the reconfigured status, the
Laux voltage is also reduced. The VCC self–powering is no
longer possible thus the SMPS enters in a hiccup mode
similar to the one described under the Overload condition.
In the SMPS stand–by mode the 3 distinct phases are:
The SWITCHING PHASE: Similar to the Overload
mode. The current sense clamping level is reduced according to the equation of the current sense section, page 5.
The C.S. clamping level depends on the power to be
delivered to the load during the SMPS stand–by mode.
Every switching sequence ON/OFF is terminated by an OC
as long as the secondary Zener diode voltage has not been
reached. When the Zener voltage is reached the ON cycle
is terminated by a true PWM action. The proper SWITCHING PHASE termination must correspond to a NOC condition. The LW latch stores this NOC status.
The LATCHED OFF PHASE: The MODE latch is set.
The START–UP PHASE is similar to the Overload
Mode. The MODE latch remains in its set status (Q=1).
The SWITCHING PHASE: The Stand–by signal is validated and the 200 μA is sourced out of the Current Sense
pin 2.
4. Transition from Stand–by to Normal
The secondary reconfiguration is removed. The regulation on the low voltage secondary rail can no longer be
achieved, thus at the end of the SWITCHING PHASE, no
PWM condition can be encountered. The LW latch is reset.
At the next WORKING PHASE a NORMAL mode status takes place.
In order to become independent of the recovery time constant on the secondary side of the SMPS an additional reset
input R2 is provided on the MODE latch. The condition
Idemag<24 μA corresponds to the activation of the secondary reconfiguration status. The R2 reset insures a direct
return into the Normal Mode
Pulsed Mode Duty Cycle Control
During the sleep mode of the SMPS the switch S3 is
closed and the control input pin 3 is connected to a 4.6 V
voltage source thru a 500 Ω resistor. The discharge rate of
the VCC capacitor is given by ICC–latch (device consumption
during the LATCHED OFF phase) in addition to the current drawn out of the pin 3. Connecting a resistor between
the Pin 3 and GND (RDPULSED) a programmable current is
drawn from the VCC through pin 3. The duration of the
LATCHED OFF phase is impacted by the presence of the
resistor RDPULSED. The equation 3 shows the relation to the
pin 3 current.
Pulsed Mode Phases
Equations 1 through 8 define and predict the effective
behavior during the PULSED MODE operation. The equations 6, 7, and 8 contain K, Y, and D factors. These factors
are combinations of measured parameters. They appear in
the parameter section “Kfactors for pulsed mode operation” page 4. In equations 3 through 8 the pin 3 current is
the current defined in the above section “Pulsed Mode Duty Cycle Control”
2011, February, Rev. 01
IL44608N
EQUATION 1
Start–up Phase Duration:
C Vcc × (VSTUP − UOLO2)
I STUP
t START − UP =
where: Istup is the start–up current flowing through VCC pin
CVcc is the VCC capacitor value
EQUATION 2
Switching Phase Duration:
t switch =
C Vcc × (VSTUP − UOLO1)
I ccS + I G
where: IccS is the no load circuit consumption in switching phase
IG is the current consumed by the Power Switch
EQUATION 3
Latched–off Phase Duration:
t latched − off =
C Vcc × (UVLOP1 − UOLO2)
I ccL + I pin3
where: IccL is the latched off phase consumption
Ipin3 is the current drawn from pin3 adding a resistor
EQUATION 4
Burst Mode Duty Cycle:
d BM =
t start -up
t SWITCH
+ t switch + t latched-off
EQUATION 5
d BM =
C Vcc
C Vcc × (VSTUP − UVLO1)
I ccS + I G
× (VSTUP − UVLO2) C Vcc × (VSTUP − UVLO1) C Vcc × (UVLO1 − UVLO2)
+
+
I STUP
I ccS + I G
I ccL + I Ipin3
EQUATION 6
d BM =
1

I +I  
I +I 
1 +  k S/Stup × ccS G  +  k S/L × ccS G 

I stup  
I ccL + I pin3 

where: kS/Stup = (Vstup – UVLO2)/(Vstup – UVLO1)
kS/L = (UVLO1 – UVLO2)/(Vstup – UVLO1)
EQUATION 7
d BM =
1
 I +I

 

I stup
 
1 + ccS G ×  k S/Stup +  k S/L ×



I stup
I
I
+

ccL
pin3   



2011, February, Rev. 01
IL44608N
EQUATION 8
d BM =
1



I
1 +  k1 + G

I stup




 

 


 

 
1
 × k S/Stup +  k S/L ×
 

 I pin3   

 

k2 + 


 I   
 stup   


where: k1 = Iccs/Istup
k2 = IccL/Istup
kS/Stup = (Vstup–UVLO2)/(Vstup–UVLO1)
kS/L = (UVLO1–UVLO2)/(Vstup–UVLO1)
PULSED MODE CURRENT SENSE CLAMPING LEVEL
Equations 9, 10, 11 and 12 allow the calculation of the Rcs value for the desired maximum current peak value during the
SMPS stand–by mode.]
EQUATION 9
Ipk stby =
Vcs − th − (R cs × I cs )
RS
where: Vcs–th is the CS comparator threshold
Ics is the CS internal current source
RS is the sensing resistor
Rcs is the resistor connected between pin 2 and RS
EQUATION 10
Ipk stby = Vcs − th

I
1 −  R cs × cs
Vcs − th
× 
RS
EQUATION 11
Ipk stby = Vcs − th ×



1 − (R cs × Ycs −stby )
RS
where: Ycs–stby = Ics/Vcs–th
Taking into account the circuit propagation delay (δtcs) and the Power Switch reaction time (δtps):
EQUATION 12
1 − (R cs × Ycs −stby ) Vin × (δ t cs + δt ps )

Ipk stby = Vcs − th ×
+
RS
LP


2011, February, Rev. 01
IL44608N
Figure 9. Output Switching Speed
Figure 10. Frequency Stability
The data in Figure 9 corresponds to the waveform in Figure 10. The Figure 10 shows VCC, ICC, Isense (pin 2) and Vout
(pin 5). Vout (pin 5) in fact shows the envelope of the output switching pulses. This mode corresponds to an overload condition.
The secondary reconfiguration is activated by the mP through the switch. The dV/dt appearing on the high voltage
winding (pins 14 of the transformer) at every TMOS switch off, produces a current spike through the series RC network R7,
C17. According to the switch position this spike is either absorbed by the ground (switch closed) or flows into the thyristor
gate (switch open) thus firing the MCR22–6. The closed position of the switch corresponds to the Pulsed Mode activation.
In this secondary side SMPS status the high voltage winding (12–14) is connected through D12 and DZ1 to the 8.0 V low
voltage secondary rail. The voltages
The Figure 11 shows the SMPS behavior while working in the reconfigured mode. The top curve represents the VCC voltage (pin 6 of the IL44608). The middle curve represents the 8.0 V rail. The regulation is taking place at 11.68 V. On the
bottom curve the pin 2 voltage is shown. This voltage represents the current sense signal. The pin 2 applied to the secondary
windings 12–14, 10–11 and 6–7 (Vaux) are thus divided by ratio N12–14 / N9–8 (number of turns of the winding 12–14
over number of turns of the winding 9–8). In this reconfigured status all the secondary voltages are lowered except the 8.0
V one. The regulation during every pulsed or burst is performed by the zener diode DZ3 which value has to be chosen higher than the normal mode regulation level. This working mode creates a voltage ripple on the 8.0 V rail which generally must
be post regulated for the microProcessor supply. voltage is the result of the 200 mA current source activated during the
start–up phase and also during the working phase which flows through the R4 resistor. The used high resolution mode of the
oscilloscope does not allow to show the effective ton current flowing in the sensing resistor R11.
Figure 11. SMPS Pulsed Mode
2011, February, Rev. 01
IL44608N
The Figure 11 represents a complete power supply using the secondary reconfiguration.
The specification is as follows:
Input source:
85 Vac to 265 Vac
3 Outputs
112 V/0.45 A
16 V/1.5 A
8.0 V/1.0 A
Output power
80 W
Stand–by mode
@ Pout = 300 mW, 1.3 W
2011, February, Rev. 01
IL44608N
PACKAGE DIMENSIONS
2011, February, Rev. 01