Revised April 1999 74VCX16500 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16500 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in a highimpedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active HIGH and OEBA is active LOW). The VCX16500 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74VCX16500 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. ■ 1.65V–3.6V VCC supply operation ■ 3.6V tolerant inputs and outputs ■ tPD (A to B, B to A) 2.9 ns max for 3.0V to 3.6V VCC 3.5 ns max for 2.3V to 2.7V VCC 7.0 ns max for 1.65V to 1.95V VCC ■ Power-down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ Static Drive (IOH/IOL) ±24 mA @ 3.0V VCC ±18 mA @ 2.3V VCC ±6 mA @ 1.65V VCC ■ Uses patented noise/EMI reduction circuitry ■ Latchup performance exceeds 300 mA ■ ESD performance: Human body model > 2000V Machine model >200V Note 1: To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistors; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74VCX16500MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 1999 Fairchild Semiconductor Corporation DS500089.prf www.fairchildsemi.com 74VCX16500 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs March 1998 74VCX16500 Connection Diagram Pin Descriptions Pin Names Description OEAB Output Enable Input for A to B Direction (Active HIGH) OEBA Output Enable Input for B to A Direction (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, CLKBA Clock Inputs A1–A18 Side A Inputs or 3-STATE Outputs B1–B18 Side B Inputs or 3-STATE Outputs Function Table (Note 2) Inputs OEAB LEAB Outputs CLKAB An Bn L X X X Z H H X L L H H X H H H L ↓ L L H L ↓ H H H L H X B0 (Note 3) H L L X B0 (Note 4) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Note 2: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA and CLKBA. OEBA is active LOW. Note 3: Output level before the indicated steady-state input conditions were established. Note 4: Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. www.fairchildsemi.com 2 74VCX16500 Logic Diagram 3 www.fairchildsemi.com 74VCX16500 Absolute Maximum Ratings(Note 5) Supply Voltage (VCC ) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V Recommended Operating Conditions (Note 7) Power Supply Output Voltage (VO) Operating −0.5V to +4.6V Outputs 3-STATE Outputs Active (Note 6) DC Input Diode Current (IIK) VI < 0V −0.5 to VCC + 0.5V −50 mA Output Voltage (VO) Output in Active States VO < 0V −50 mA VO > VCC +50 mA 0.0V to 3.6V Output Current in IOH/IOL ±50 mA VCC = 3.0V to 3.6V ±24 mA VCC = 2.3V to 2.7V ±18 mA VCC = 1.65V to 2.3V DC VCC or Ground Current per Storage Temperature Range (TSTG) 0V to VCC Output in 3-STATE DC Output Source/Sink Current Supply Pin (ICC or Ground) 1.2V to 3.6V −0.3V to 3.6V Input Voltage DC Output Diode Current (IOK) (IOH/IOL) 1.65V to 3.6V Data Retention Only ±100 mA ±6 mA Free Air Operating Temperature (TA) −65°C to +150°C −40°C to +85°C Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 5: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions tables will define the conditions for actual device operation. Note 6: IO Absolute Maximum Rating must be observed. Note 7: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW. DC Electrical Characteristics (2.7V < VCC ≤ 3.6V) Symbol Parameter Conditions VCC (V) VIH HIGH Level Input Voltage 2.7–3.6 VIL LOW Level Input Voltage 2.7–3.6 VOH HIGH Level Output Voltage VOL LOW Level Output Voltage Min Max Units 0.8 V 2.0 IOH = −100 µA 2.7–3.6 VCC − 0.2 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 2.2 V V IOH = −24 mA 3.0 IOL = 100 µA 2.7–3.6 0.2 IOL = 12 mA 2.7 0.4 IOL = 18 mA 3.0 0.4 IOL = 24 mA 3.0 0.55 II Input Leakage Current 0V ≤ VI ≤ 3.6V 2.7–3.6 ±5.0 IOZ 3-STATE Output Leakage 0V ≤ VO ≤ 3.6V 2.7–3.6 ±10 VI = VIH or VIL IOFF Power Off Leakage Current 0V ≤ (VI, VO) ≤ 3.6V 0 10 ICC Quiescent Supply Current VI = VCC or GND 2.7–3.6 20 VCC ≤ (VI, VO) ≤ 3.6V (Note 8) 2.7–3.6 ±20 ∆ICC Increase in ICC per Input VIH = VCC − 0.6V 2.7–3.6 750 Note 8: Outputs disabled or 3-STATE only. www.fairchildsemi.com 4 V µA µA µA µA µA Symbol Parameter Conditions VCC Min Max Units 0.7 V (V) VIH HIGH Level Input Voltage 2.3–2.7 VIL LOW Level Input Voltage 2.3–2.7 VOH HIGH Level Output Voltage VOL LOW Level Output Voltage IOH = −100 µA 1.6 2.3–2.7 VCC − 0.2 IOH = −6 mA 2.3 2.0 IOH = −12 mA 2.3 1.8 1.7 V V IOH = −18 mA 2.3 IOL = 100 µA 2.3–2.7 0.2 IOL = 12 mA 2.3 0.4 IOL = 18 mA 2.3 0.6 2.3–2.7 ±5.0 µA 2.3–2.7 ±10 µA 0 10 µA II Input Leakage Current 0 ≤ VI ≤ 3.6V IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V IOFF Power Off Leakage Current 0 ≤ (VI, VO) ≤ 3.6V ICC Quiescent Supply Current VI = V CC or GND 2.3–2.7 20 VCC ≤ (VI, VO) ≤ 3.6V (Note 9) 2.3–2.7 ±20 VI = V IH or VIL V µA Note 9: Outputs disabled or 3-STATE only. DC Electrical Characteristics (1.65V ≤ VCC < 2.3V) Symbol Parameter Conditions VCC (V) VIH HIGH Level Input Voltage 1.65 - 2.3 VIL LOW Level Input Voltage 1.65 - 2.3 VOH HIGH Level Output Voltage IOH = −100 µA VOL LOW Level Output Voltage Min Max 0.65 × VCC Units V 0.35 × VCC V 1.65 - 2.3 VCC − 0.2 IOH = −6 mA 1.65 1.25 IOL = 100 µA 1.65 - 2.3 0.2 1.65 0.3 1.65 - 2.3 ±5.0 µA 1.65 - 2.3 ±10 µA µA IOL = 6 mA II Input Leakage Current 0 ≤ VI ≤ 3.6V IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V VI = V IH or VIL V IOFF Power Off Leakage Current 0 ≤ (VI, VO) ≤ 3.6V 0 10 ICC Quiescent Supply Current VI = V CC or GND 1.65 - 2.3 20 VCC ≤ (VI, VO) ≤ 3.6V (Note 10) 1.65 - 2.3 ±20 V µA Note 10: Outputs disabled or 3-STATE only. 5 www.fairchildsemi.com 74VCX16500 DC Electrical Characteristics (2.3V ≤ VCC ≤ 2.7V) 74VCX16500 AC Electrical Characteristics (Note 11) TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V Min fMAX Maximum Clock Frequency tPHL Propagation Delay tPLH Bus to Bus tPHL Propagation Delay tPLH Clock to Bus tPHL Propagation Delay tPLH LE to Bus tPZL Output Enable Time tPZH tPLZ Output Disable Time tPHZ Max 250 VCC = 2.5 ± 0.2V VCC = 1.8 ± 0.15V Min Min Max 200 Units Max 100 MHz 0.6 2.9 0.8 3.5 1.5 7.0 ns 0.6 4.2 0.8 5.3 1.5 9.8 ns 0.6 3.8 0.8 4.9 1.5 9.8 ns 0.6 3.8 0.8 4.9 1.5 9.8 ns 0.6 3.7 0.8 4.2 1.5 7.6 Setup Time 1.5 1.5 tH Hold Time 1.0 1.0 1.0 ns tW Pulse Width 1.5 1.5 4.0 ns tOSHL Output to Output tOSLH Skew (Note 12) 0.5 2.5 ns tS 0.5 ns 0.75 ns Note 11: For CL = 50pF, add approximately 300ps to the AC maximum specification. Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Symbol VOLP Parameter Quiet Output Dynamic Conditions CL = 30 pF, VIH = VCC, VIL = 0V Peak VOL VOLV Quiet Output Dynamic CL = 30 pF, VIH = VCC, VIL = 0V Valley VOL VOHV Quiet Output Dynamic CL = 30 pF, VIH = VCC, VIL = 0V Valley VOH VCC (V) TA = +25°C Typical Units 1.8 2.5 3.3 0.25 0.6 0.8 V 1.8 2.5 3.3 −0.25 −0.6 −0.8 V 1.8 2.5 3.3 1.5 1.9 2.2 V TA = +25°C Units 6 pF 7 pF 20 pF Capacitance Symbol CIN Parameter Input Capacitance Conditions VI = 0V or VCC VCC = 1.8V, 2.5V, or 3.3V, CI/O Output Capacitance VI = 0V, or VCC, VCC = 1.8V, 2.5V or 3.3V CPD Power Dissipation Capacitance VI = 0V or VCC, f = 10 MHz VCC = 1.8V, 2.5V or 3.3V www.fairchildsemi.com 6 74VCX16500 AC Loading and Waveforms FIGURE 1. AC Test Circuit TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V; VCC x 2 at VCC = 2.5 ± 0.2V; 1.8 ± 0.15V tPZH, tPHZ GND FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic Symbol VCC 3.3V ± 0.3V 2.5V ± 0.2V 1.8 ± 0.15V Vmi 1.5V VCC /2 VCC /2 Vmo 1.5V VCC /2 VCC /2 VX VOL + 0.3V VOL + 0.15V VOL + 0.15V VY VOH − 0.3V VOH − 0.15V VOH − 0.15V 7 www.fairchildsemi.com 74VCX16500 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.