Precision Edge® Micrel, Inc. 3.3V, PRECISION, 33MHz to 500MHz ® SY89531L Precision Edge PROGRAMMABLE LVPECL AND HSTL BUS SY89531L CLOCK SYNTHESIZER FEATURES ■ Integrated synthesizer plus fanout buffers, clock drivers, and translator in a single 64-pin package ■ 3.3V ±10% power supply ■ Low jitter: <50ps cycle-to-cycle ■ Low pin-to-pin skew: <50ps ■ 33MHz to 500MHz output frequency range ■ Direct interface to crystal: 14MHz to 18MHz ■ LVPECL/HSTL outputs ■ TTL/CMOS compatible control logic ■ 3 independently programmable output frequency banks: • 9 differential output pairs @BankB (HSTL) • 2 differential output pairs @BankA (LVPECL) • 2 differential output pairs @BankC (LVPECL) ■ ExtVCO input allows synthesizer and crystal interface to be bypassed ■ Available in 64-pin EPAD-TQFP Precision Edge® DESCRIPTION The SY89531L programmable clock synthesizer/driver is part of a 3.3V, high-frequency, precision PLL-based clock synthesizer family optimized for multi-frequency, multiprocessor server, enterprise networking and other computing applications that require the highest precision and integration. The device integrates the following blocks into a single monolithic IC: • PLL (Phase-Lock-Loop)-based synthesizer • Fanout buffers • Clock generator (dividers) • Logic translation (LVPECL, HSTL) This level of integration minimizes the additive jitter and part-to-part skew associated with the discrete alternative, resulting in superior system-level timing as well as reduced board space and power. For applications that must interface to a reference clock, see the SY89536L. Datasheets and support documentation can be found on Micrel’s web site at: www.micrel.com. PRODUCT SELECTION GUIDE APPLICATIONS ■ ■ ■ ■ ■ Servers Workstations Parallel processor-based systems Other high-performance computing Communications Input Device Crystal Output BankA BankB BankC SY89531L X Reference LVPECL HSTL LVPECL SY89532L* X LVPECL LVPECL LVPECL SY89533L* X LVPECL LVDS LVPECL SY89534L* X LVPECL LVPECL LVPECL SY89535L* X LVPECL LVDS LVPECL SY89536L* X LVPECL HSTL LVPECL *Refer to individual data sheet for details. Precision Edge is a registered trademark of Micrel, Inc. M9999-010808 [email protected] or (408) 955-1690 Rev.: C 1 Amendment: /0 Issue Date: January 2008 Precision Edge® SY89531L Micrel, Inc. PACKAGE/ORDERING INFORMATION NC GND VCCA VCC_LOGIC VCC_LOGIC OUT_SYNC FSEL_A0 FSEL_A1 FSEL_A2 VCCOA QA0 /QA0 QA1 /QA1 VCCOB QB0 Ordering Information(1) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC NC NC VCO_SEL /EXTVCO EXTVCO LOOP_REF LOOP_FILTER GND XTAL2 XTAL1 VBB_REF M(3) M(2) M(1) M(0) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 /QC1 QC1 /QC0 QC0 VCCOC FSEL_C2 FSEL_C1 FSEL_C0 GND FSEL_B2 FSEL_B1 FSEL_B0 GND VCCOB VCCOB /QB8 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 /QB0 QB1 /QB1 QB2 /QB2 QB3 /QB3 QB4 /QB4 QB5 /QB5 QB6 /QB6 QB7 /QB7 QB8 Part Number Package Type Operating Range Package Marking Lead Finish SY89531LHC H64-1 Commercial SY89531LHC Sn-Pb SY89531LHCTR(2) H64-1 Commercial SY89531LHC Sn-Pb SY89531LHZ(3) H64-1 Commercial SY89531LHZ with Matte-Sn Pb-Free bar-line indicator Pb-Free SY89531LHZTR(2, 3) H64-1 Commercial SY89531LHZ with Matte-Sn Pb-Free bar-line indicator Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 64-Pin EPAD-TQFP (H64-1) M9999-010808 [email protected] or (408) 955-1690 2 Precision Edge® SY89531L Micrel, Inc. PIN DESCRIPTION Power Pin Number Pin Name Pin Function 60, 61 VCC_Logic Power for Core Logic: Connect to 3.3V supply. 3.3V power pins are not internally connected on the die, and must be connected together on the PCB. 62 VCCA Power for PLL: Connect to “quiet” 3.3V supply. 3.3V power pins are not internally connected on the die, and must be connected together on the PCB. 55 30, 31, 50 21 VCCOA VCCOB VCCOC 9, 25, 63, 29 (exposed pad) GND Power for Output Drivers: Connect all VCCOA and VCCOC pins to 3.3V supply and VCCOB pins to 1.8V supply. Ground: Exposed pad must be soldered to a ground plane. Configuration Pin Number Pin Name Pin Function 4 VCO_SEL LVTTL/CMOS Compatible Input: Selects between internal or external VCO. For external VCO, leave floating. Default condition is logic HIGH. Internal 25kΩ pull-up. When tied LOW, internal VCO is selected. 7 LOOP REF Analog Input/Output: Provides the reference voltage for PLL loop filter. 8 LOOP FILTER 13,14,15,16 M (3:0) 22, 23, 24 FSEL_C (2:0) LVTTL/CMOS Compatible Input: Bank C post divide select. Internal 25kΩ pull-up. Default is logic HIGH. See “Post-Divide Frequency Select” table. FSEL_C0 = LSB. 26, 27, 28 FSEL_B (2:0) LVTTL/CMOS Compatible Input: Bank B post divide select. Internal 25kΩ pull-up. Default is logic HIGH. See “Post-Divide Frequency Select” table. FSEL_B0 = LSB. 56, 57, 58 FSEL_A (2:0) LVTTL/CMOS Compatible Input: Bank A post divide select. Internal 25kΩ pull-up. Default is logic HIGH. See “Post-Divide Frequency Select” table. FSEL_A0 = LSB. 59 OUT_SYNC Analog Input/Output: Provides the loop filter for PLL. See “External Loop Filter Considerations” for loop filter values. LVTTL/CMOS Compatible Input: Used to change the PLL feedback divider. Internal 25kΩ pull-up. M0 = LSB. Default is logic HIGH. See “Feedback Divide Select” table. Banks A, B, C Output Synchronous Control: (LVTTL/CMOS compatible). Internal 25kΩ pull-up. After any bank has been programmed, toggle with a HIGH-LOW-HIGH pulse to resynchronize all output banks. Input/Output Pin Number Pin Name 1, 2, 3 NC 10, 11 XTAL2, XTAL1 12 VBB_REF 5, 6 /EXT_VCO, EXT_VCO Differential “Any In” Compatible Input Pair. Allows for external VCO connection. The “Any In” input structure accepts many popular logic types. See “Input Interface for ExtVCO Pins” section for interface diagrams. Can leave unconnected if using internal VCO. 51, 52, 53, 54 QA1 to QA0 Bank A 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_A (0:2). Terminate outputs with 50Ω to VCC –2V. See “Output Termination Recommendations” section. 32–49 QB8 to QB0 Bank B Output Drivers: Differential HSTL outputs. See “Output Termination Recommendations” section. Output frequency is controlled by FSEL_B (0:2). 17, 18, 19, 20 QC1 to QC0 Bank C 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_C (0:2). Terminate outputs with 50Ω to VCC–2V. See “Output Termination Recommendations” section. 64 NC M9999-010808 [email protected] or (408) 955-1690 Pin Function No Connect: Leave floating. Crystal Input. Directly connect a series resonant crystal across inputs. Reference Output Voltage. Used for single-ended input. Maximum sink/source current = 0.5mA. No Connect: Leave floating. 3 Precision Edge® SY89531L Micrel, Inc. Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Supply Voltage (VIN) ................................... –0.5V to +4.0V VCC Pin Potential to Ground Pin (All VCC) .. –0.5V to +4.0V Input Voltage (except XTAL 1,2 pins) (VIN) ... –0.5V to VCCI XTAL 1, 2 Input Voltage (VXTAL 1,2) ...... (VCC–1.9V) to VCC DC Output Current (IOUT) –LVPECL, HSTL outputs ..................................... –50mA Lead Temperature (soldering, 20 sec.) ..................... 260°C Storage Temperature (TS) ....................... –65°C to +150°C Supply Voltage VCCOA and VCCOC ...................................... 3.0V to 3.6V VCCOB ......................................................... 1.6V to 2.0V Ambient Temperature (TA) ............................. 0°C to +85°C Package Thermal Resistance (Junction-to-Ambient) With Die attach soldered to GND: TQFP (θJA) Still-Air .............................................. 23°C/W TQFP (θJA) 200lfpm ............................................ 18°C/W TQFP (θJA) 500lfpm ............................................ 15°C/W With Die attach NOT soldered to GND, Note 3 TQFP (θJA) Still-Air .............................................. 44°C/W TQFP (θJA) 200lfpm ............................................ 36°C/W TQFP (θJA) 500lfpm ............................................ 30°C/W Package Thermal Resistance (Junction-to-Case) TQFP (θJC) ......................................................... 4.3°C/W DC ELECTRICAL CHARACTERISTICS Power Supply Symbol Parameter Condition Min Typ Max Units VCCA VCC_Logic PLL and Logic Supply Voltage Note 4 3.0 3.3 3.6 V VCCOA/C Bank A and C VCC Output 3.0 3.3 3.6 V VCCOB Bank B VCC Output LVPECL/HSTL 1.6 1.8 2.0 V — 230 295 mA ICC Note 1. Note 2. Note 3. Note 4. Note 5. Total Supply Current Note 5 Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. It is recommended that the user always solder the exposed die pad to a ground plane for enhanced heat dissipation. VCCA, VCC_LOGIC, VCCOA/C are not internally connected together inside the device. They must be connected together on the PCB. VCCOB is a separate supply. No load. Outputs floating, Banks A, B, and C enabled. M9999-010808 [email protected] or (408) 955-1690 4 Precision Edge® SY89531L Micrel, Inc. DC ELECTRICAL CHARACTERISTICS LVCMOS/LVTTL Input Control Logic (VCCA, VCC_LOGIC, VCCOA/C = +3.3V ±10%) Symbol Parameter VIH Condition Min Typ Max Units Input HIGH Voltage 2.0 — — V VIL Input LOW Voltage — — 0.8 V IIH Input HIGH Current — — 150 µA IIL Input LOW Current — — –300 µA Min Typ Max Units ExtVCO (Pins 5, 6) INPUT (All VCC pins except VCCOB = +3.3V ±10%, VCCOB = +1.8V ±10%) Symbol Parameter Condition VID Differential Input Voltage 100 — — mV VIH Input HIGH Voltage — — VCC +0.3 V VIL Input LOW Voltage –0.3 — — V Min Typ Max Units 100K LVPECL Output (All VCC pins except VCCOB = +3.3V ±10%, VCCOB = +1.8V ±10%)(Note 6) Symbol Parameter Condition VOH Output HIGH Voltage VCC–1.145 VCC–1.020 VCC–0.895 V VOL Output LOW Voltage VCC–1.945 VCC–1.820 VCC –1.695 V VBB Output Reference Voltage VCC–1.325 VCC–1.425 VCC–1.525 V VOUT Output Voltage Swing — 800 — mV Min Typ Max Units HSTL Output (Bank B QB0:8) (All VCC pins except VCCOB = +3.3V ±10%, VCCOB = +1.8V ±10%)(Note 7) Symbol Parameter VOUT Output Voltage Swing — 800 — mV VOH Output HIGH Voltage 1.0 — 1.2 V VOL Output LOW Voltage 0.2 — 0.4 V Note 6. Note 7. Condition All LVPECL outputs loaded with 50Ω to VCC–2V. All HSTL outputs loaded with 50Ω to GND. M9999-010808 [email protected] or (408) 955-1690 5 Precision Edge® SY89531L Micrel, Inc. AC ELECTRICAL CHARACTERISTICS VCC_LOGIC = VCCA = VCCOA/C = +3.3V ±10%, VCCOB = +1.8V ±10% Symbol Parameter Condition Min Typ Max Units fIN Xtal Input Frequency Range Note 8 14 — 18 MHz fOUT Output Frequency Range w/Internal VCO 33.33 — 500 MHz w/External VCO — — 622.08 MHz 600 — 1000 MHz External VCO Frequency — — 1250 MHz tskew Within Device Skew — — 50 ps Note 9 Within-Bank PECL — — 50 ps Within-Bank HSTL — — 75 ps Between Banks — — 150 ps — — 200 ps — — 10 ms tVCO Internal VCO Frequency Range Part-to-Part Skew tLOCK Maximum PLL Lock Time tJITTER Cycle-to-Cycle Jitter Period Jitter tpw (min) Note 10 (Pk-to-Pk) Note 11 — 25 — ps (RMS) Note 12 — — 50 ps 50 — — ns — — 1.0 2.0 — — MHz MHz Minimum Pulse Width Target PLL Loop Bandwidth Feedback Divider Ratio: 72 Feedback Divider Ratio: 34 Note 13 Note 13 tDC fOUT Duty Cycle 45 50 55 % tr, tf Output Rise/Fall Time (20% to 80%)LVPECL_Out HSTL_Out — 100 250 — 450 450 ps ps — — 10 ns tHOLD_FSEL 5 — — ns tSETUP_FSEL 5 — — ns tOUTPUT_SYNC 1 — — VCO clock cycle FSEL-to-Valid Output Transition Time — — 1 µs 500 — — ps tOUTPUT_RESET Note 14 tSETUP_OUT_SYNC Note 8. Note 9. Note 10. Note 11. Note 12. Note 13. Note 14. Fundamental mode crystal. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC =Tn– Tn+1 where T is the time between rising edges of the output signal. Period Jitter definition: For a specified amount of time (i.e., 1ms), there are N periods of a signal, and Tn is defined as the average period of that signal. Period jitter is defined as the variation in the period of the output signal for corresponding edges relative to Tn. Using recommended loop filter components. See “Functional Description, External Loop Filter Considerations.” See “Timing Diagrams.” M9999-010808 [email protected] or (408) 955-1690 6 Precision Edge® SY89531L Micrel, Inc. TIMING DIAGRAMS Conditions: Internal VCO, unless otherwise stated. VCO FSEL 001 010 FOUT OUT_SYNC tOUTPUT_SYNC tOUTPUT_RESET tHOLD_FSEL tSETUP_FSEL TIME Frequency Programming (Internal VCO Clock) VCO (ext.) FSEL 001 010 FOUT OUT_SYNC tOUTPUT_SYNC tOUTPUT_RESET TIME tSETUP_OUT_SYNC Frequency Programming (External VCO Clock) VCO FSEL 001 010 FOUT OUT_SYNC fSEL to VALID OUTPUT TRANSITION TIME TIME Output Frequency Update to Valid Output M9999-010808 [email protected] or (408) 955-1690 7 Precision Edge® SY89531L Micrel, Inc. FUNCTIONAL BLOCK DIAGRAM NC NC NC NC GND VCCA VCC_Logic VCC_Logic OUT_Sync FSEL_A0 (LSB) FSEL_A1 FSEL_A2 VCCOA QA0 /QA0 QA1 /QA1 VCCOB 1 2 3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 QB0 48 /QB0 3 VCO_SEL 4 /ExtVCO 5 ExtVCO 6 Loop Ref 7 Loop Filter 8 47 QB1 46 /QB1 45 QB2 Buf 0 = Internal VCO enabled 1 = Internal VCO disabled (default) VCO Select 44 /QB2 2x 3-Bit Divider A 2, 4, 6, 8, 10, 12,18 43 QB3 A EN 42 /QB3 Mux 1 GND 9 14MHz to 18MHz XTAL2 10 Oscillator XTAL1 Phase Detector 11 VBB_Ref 12 VCC—1.425V Reference or Bandgap Reference 41 QB4 5 Clock Charge Pump Buf 40 /QB4 VCO 3-Bit Divider B 2, 4, 6, 8, 10, 12,18 (600MHz to 1000MHz) 14MHz to 18MHz M-Divide 34, 36, 38, 40, 42 44, 48, 50, 52, 54 56, 60, 62, 66, 70, 72 600MHz to 1000MHz 9x 39 QB5 B EN 38 /QB5 3 37 QB6 36 /QB6 3-Bit Divider C 2, 4, 6, 8, 10, 12,18 (MSB) M3 13 M2 14 35 QB7 C EN 34 /QB7 M1 15 33 QB8 (LSB) M0 16 3 2x 32 /QB8 31 VCCOB 18 19 20 21 22 23 24 25 26 27 28 29 /QC1 QC1 /QC0 QC0 VCCOC FSEL_C2 FSEL_C1 FSEL_C0 (LSB) GND FSEL_B2 FSEL_B1 FSEL_B0 (LSB) GND M9999-010808 [email protected] or (408) 955-1690 17 8 30 VCCOB Precision Edge® SY89531L Micrel, Inc. FUNCTIONAL DESCRIPTION At the core of the SY89531L clock synthesizer is a precision PLL driven by 14MHz to 18MHz series resonant crystal. For users who wish to supply a TTL or LVPECL clock input, please use the SY89536L. The PLL output is sent to three banks of outputs. Each bank has its own programmable frequency divider, and the design is optimized to provide very low skew between banks, and very low jitter. ExtVCO Input Interface The flexible ExtVCO inputs are designed to accept any differential or single-ended input signal within 300mV above VCC and 300mV below ground. Do not leave unused ExtVCO inputs floating. Tie either the true or complement inputs to ground, but not both. A logic zero is achieved by connecting the complement input to ground with the true input floating. For a TTL input, see “Input Interface for ExtVCO Pins” section, Figures 5a through 5h. Input Levels LVDS, CML and HSTL differential signals may be connected directly to the ExtVCO inputs. Depending on the actual worst case voltage seen, the minimum input voltage swing varies. PLL Programming and Operation IMPORTANT: If the internal VCO will be used, VCO_SEL must be tied LOW, and ExtVCO pins can be left unconnected. The internal VCO range is 600MHz to 1000MHz, and the feedback ratio is selectable via the MSEL divider control (M3:0 pins). The VCO_SEL pin must be tied low. The feedback ratio can be changed without powering the chip down. The PLL output is fed to three banks of outputs: Bank A, Bank B, and Bank C. Banks A and C each have two differential LVPECL output pairs. Bank B has nine differential HSTL output pairs. Each bank has a separate frequency divider circuit that can be reprogrammed on the fly. The FSEL_x0:2 (where x is A, B, or C) pins control the divider value. The FSEL divider can be programmed in ratios from 2 to 18, and the outputs of Banks A, B, and C can be synchronized after programming by pulsing the OUT_SYNC pin HIGH-LOWHIGH. Setting a value of 000 for FSEL is an output disable forcing the Q outputs to be LOW and the /Q outputs to be HIGH. Doing so will decrease power consumption by approximately 5mA per bank. To determine the correct settings for the SY89531L follow these steps: 1. Refer to the “Suggested Selections for Specific Customer Applications” section for common applications, as well as the formula used to compute the output frequency. 2. Determine the desired output frequency, such as 66MHz. 3. Choose a crystal frequency between 14MHz and 18MHz. In this example, we choose 18MHz for the crystal frequency. This results in an input/output ratio of 66/18. 4. Refer to the “Feedback Divide Select” table and the “Post-Divide Frequency Select” table to find values for MSEL and FSEL such that MSEL/FSEL equals the same 66/18 ratio. In this example, values of MSEL=44 and FSEL=12 work. 5. Make sure that XTAL (the crystal frequency) multiplied by MSEL is between 600MHz and 1000MHz. The user may need to experiment with different crystal frequencies to satisfy these requirements. M9999-010808 [email protected] or (408) 955-1690 VCC R2 990Ω R2 990Ω EXTVCO R1 825Ω /EXTVCO R1 825Ω GND Figure 1. Simplified Input Structure 9 Precision Edge® SY89531L Micrel, Inc. Crystal Input and Oscillator Interface External Loop Filter Considerations The SY89531L features a fully integrated on-board oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design, and thus, a series-resonant crystal is preferred, but not required. A parallel-resonant crystal can be used with the SY89531L with only a minor error in the desired frequency. A parallelresonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified; a few hundred ppm translates to kHz inaccuracies. In a general computer application this level of inaccuracy is immaterial. As the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the SY89531L as possible to avoid any board level parasitics. In addition, trace lengths should be matched. Figure 2 shows how to interface with a crystal. Table 1 illustrates the crystal specifications. Certain crystals may require a 10pF capacitor across XTAL1 and XTAL2 for proper operation. This is normally not required, but it is recommended that provisions be made for it. The SY89531L features an external PLL loop filter that allows the user to tailor the PLL’s behavior to their application and operating environment. We recommend using ceramic capacitors with NPO or X7R dielectric, as they have verylow effective series resistance. For applications that require ultra-low cycle-to-cycle jitter, use the components shown in Figure 3. The PLL loop bandwidth is a function of feedback divider ratio, and the external loop filter allows the user to compensate. For instance, the PLL’s loop bandwidth can be decreased by using a smaller resistor in the loop filter. This results in less noise from the PLL input, but potentially more noise from the VCO. Refer to “AC Electrical Characteristics” for target PLL loop bandwidth. The designer should take care to keep the loop filter components on the same side of the board and as close as possible to the SY89531L’s LOOP_REF and LOOP_FILTER pins. To insure minimal noise pick up on the loop filter, it is desirable to cut away the ground plane directly underneath the loop filter component pads and traces. However, the benefit may not be significant in all applications and one must be careful to not alter the characteristic impedance of nearby traces. 330Ω 0.2µF SY89531L XTAL 16.666MHz XTAL2 (Pin 26, SOIC) 470pF Loop Filter XTAL1 (Pin 25, SOIC) Loop Reference Figure 3. External Loop Filter Connection Optional Quartz Crystal Selection: (1) Raltron Series Resonant: AS-16.666-S-SMD-T-MI (2) Raltron Parallel Resonant: AS-16.666-18-SMD-T-MI Figure 2. Crystal Interface Output Frequency: 14MHz-18MHz Mode of Oscillation: Fundamental Min Typ Max Unit Frequency Tolerance @25°C — ±30 ±50 ppm Frequency Stability over 0°C to 70°C — ±50 ±100 ppm Operating Temperature Range –20 — +70 °C Storage Temperature Range –55 — +125 °C Aging (per yr/first 3 yrs) — — ±5 ppm Load Capacitance — 18 (or series) — pF Equivalent Series Resistance (ESR) — — 50 Ω Drive Level — 100 — µW Table 1. Quartz Crystal Oscillator Specifications M9999-010808 [email protected] or (408) 955-1690 10 Precision Edge® SY89531L Micrel, Inc. Power Supply Filtering Techniques output in the same manner as the normal output that is begin used. Unused output pairs can be left floating. Unused output banks can be switched off by tying the appropriate FSEL pins to ground. Unused output pairs that are in a bank that is disabled can be left floating, regardless of output driver type. LVPECL operation: • Typical voltage swing is 700mVPP to 800mVPP into 50Ω. • Common mode voltage is VCC–1.3V, typical. • 100Ω termination across the output pair is NOT recommended for LVPECL. HSTL operation (Bank B): • Typical voltage swing is 250mVPP to 450mVPP into effective 50Ω. As with any high-speed integrated circuit, power supply filtering is very important. At a minimum, VCCA, VCC_Logic, and all VCCO pins should be individually connected using a via to the power supply plane, and separate bypass capacitors should be used for each pin. To achieve optimal jitter performance, each power supply pin should use separate instances of the circuit shown in Figure 4. “Power Supply” side Ferrite Bead* “Device” side VCC Pins 22µF 1µF 0.01µF *For VCC_Analog,VCC_TTL, VCC1, use ferrite bead = 200mA, 0.45Ω DC, Murata P/N BLM21A1025 Thermal Considerations This part has an exposed die pad for enhanced heat dissipation. We strongly recommend soldering the exposed pad to a ground plane. Where this is not possible, we recommend maintaining at least 500lfpm air flow. For additional information on exposed-pad characteristics and implementation details, see Amkor Technology’s writeup at www.amkor.com. *For VCC_OUT use ferrite bead = 3A, 0.025Ω DC, Murata, P/N BLM31P005 *Component size: 0805 Figure 4. Power Supply Filtering Output Logic Characteristics See “Output Termination Recommendations” for illustrations. In cases where single-ended output is desired, the designer should terminate the unused complimentary POST-DIVIDE FREQUENCY SELECT TABLE (FSEL) FSEL_A2(1) (MSB) FSEL_A1(1) FSEL_A0(1) (LSB) Output Divider 0 0 0 Output Disable Function, all outputs: Q = LOW, /Q = HIGH 0 0 1 VCO ÷ 2 0 1 0 VCO ÷ 4 0 1 1 VCO ÷ 6 1 0 0 VCO ÷ 8 1 0 1 VCO ÷ 10 1 1 0 VCO ÷ 12 1 1 1 VCO ÷ 18 Note 1. Same dividers apply to FSEL_B (0:2) and FSEL_C (0:2). M9999-010808 [email protected] or (408) 955-1690 11 Precision Edge® SY89531L Micrel, Inc. FEEDBACK DIVIDE SELECT TABLE (MSEL) Note 1. M3 M2 M1 M0 VCO Frequency(1) 0 0 0 0 Ref × 34 0 0 0 1 Ref × 36 0 0 1 0 Ref × 38 0 0 1 1 Ref × 40 0 1 0 0 Ref × 42 0 1 0 1 Ref × 44 0 1 1 0 Ref × 48 0 1 1 1 Ref × 50 1 0 0 0 Ref × 52 1 0 0 1 Ref × 54 1 0 1 0 Ref × 56 1 0 1 1 Ref × 60 1 1 0 0 Ref × 62 1 1 0 1 Ref × 66 1 1 1 0 Ref × 70 1 1 1 1 Ref × 72 Ref = Crystal Frequency. SUGGESTED SELECTIONS FOR SPECIFIC CUSTOMER APPLICATIONS(Notes 1, 2) Protocol Rate (MHz) FSEL (Post Divider) MSEL (Feedback Div.) XTAL (MHz) FOUT PCI 33 18 36 16.67 33 Fast Ethernet 100 6 40 15 100 1/8 FC 133 6 52 15.36 133 ESCON 200 4 50 16 200 FOUT = (XTAL × MSEL) FSEL Note 1. 600MHz < (XTAL x MSEL) < 1000MHz. Note 2. Where two settings provide the user with the identical desired frequency, the setting with the higher input reference frequency (and lower feedback divider) will usually have lower output jitter. However, the reference input frequency, as well as the VCO frequency, must be kept within their respective ranges. M9999-010808 [email protected] or (408) 955-1690 12 Precision Edge® SY89531L Micrel, Inc. INPUT INTERFACE FOR EXTVCO PINS VCC ≥ VCC(DRIVER) VCC(DRIVER) VCC ≥ VCC(DRIVER) VCC(DRIVER) TTL LVTTL EXTVCO EXTVCO /EXTVCO 1% CML SY89531L 102Ω 1% /EXTVCO SY89531L Figure 5b. CML DC-Coupled Figure 5a. 3.3V “TTL” VCC ≥ VCC(DRIVER) VCC(DRIVER) EXTVCO 2.3V to 2.7V 3.0V to 3.6V PECL /EXTVCO 2.5V LVTTL SY89531L EXTVCO 50Ω 1% 50Ω 1% /EXTVCO SY89531L 1% VCC—2V Figure 5c. 2.5V “LVTTL” Figure 5d. 3.3V LVPECL DC-Coupled VCC VCC(DRIVER) VCC EXTVCO CML EXTVCO 102Ω 1% /EXTVCO HSTL 3.92kΩ 1% /EXTVCO 50Ω 50Ω SY89531L SY89531L Figure 5f. CML AC-Coupled (Short Trace Lengths) Figure 5e. HSTL M9999-010808 [email protected] or (408) 955-1690 3.92kΩ 1% 13 Precision Edge® SY89531L Micrel, Inc. VCC VCC(DRIVER) 82Ω 1% 82Ω 1% VCC EXTVCO CML VCC /EXTVCO 130Ω 1% 130Ω 1% SY89531L EXTVCO LVDS 100Ω 1% /EXTVCO SY89531L Figure 5h. LVDS Figure 5g. CML AC-Coupled (Long Trace Lengths) M9999-010808 [email protected] or (408) 955-1690 14 Precision Edge® SY89531L Micrel, Inc. OUTPUT TERMINATION RECOMMENDATIONS +3.3V +3.3V ZO = 50Ω R1 130Ω R1 130Ω R2 82Ω R2 82Ω +3.3V ZO = 50Ω “Source” “Destination” Vt = VCC –2V Figure 6. PECL Parallel Termination Thevenin Equivalent (Note 1) +3.3V +3.3V ZO = 50Ω ZO = 50Ω 50Ω 50Ω “Source” “Destination” 50Ω Rb C1 (optional) 0.01µF Figure 7. LVPECL Three-Resistor “Y-Termination” (Notes 1, 2, 3) +3.3V +3.3V ZO = 50Ω 50Ω ZO = 50Ω 50Ω Source Destination Figure 8. HSTL Differential Termination (Note 1) Note 1. Place termination resistors as close to destination inputs as possible. Note 2. PECL Y-termination is a power-saving alternative to Thevenin termination. Note 3. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46Ω to 50Ω. M9999-010808 [email protected] or (408) 955-1690 15 Precision Edge® SY89531L Micrel, Inc. 64-PIN EPAD-TQFP (DIE UP) (H64-1) +0.05 –0.05 +0.002 –0.002 +0.05 –0.05 +0.012 –0.012 +0.03 –0.03 +0.012 –0.012 +0.15 –0.15 +0.006 –0.006 +0.05 –0.05 +0.002 –0.002 Rev. 02 Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 64-Pin EPAD-TQFP Package Package Notes: Note 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form. Note 2. Exposed pads must be soldered to a ground for proper thermal management. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. M9999-010808 [email protected] or (408) 955-1690 16