TEA1553T GreenChip II SMPS control IC Rev. 01 — 3 July 2007 Product data sheet 1. General description The GreenChip II is the second generation of green Switched Mode Power Supply (SMPS) controller ICs operating directly from the rectified universal mains. A high level of integration leads to a cost effective power supply with a very low number of external components. The special built-in green functions allow optimum efficiency at all power levels. This applies to quasi-resonant operation at high power levels, as well as fixed frequency operation with valley switching at medium power levels. At low power (standby) levels, the system operates at reduced frequency and with valley detection. The proprietary high voltage BCD800 process makes direct start-up possible from the rectified universal mains voltage in an effective and green way. A second low voltage BICMOS IC is used for accurate, high speed protection functions and control. Highly efficient, reliable supplies can easily be designed using the GreenChip II controller. 2. Features 2.1 Distinctive features n Universal mains supply operation (70 V AC to 276 V AC) n High level of integration, giving a very low external component count 2.2 Green features n n n n n Valley/zero voltage switching for minimum switching losses Frequency reduction at low power standby for improved system efficiency (< 1 W) On-chip start-up current source Efficient quasi-resonant operation at high power levels Cycle skipping mode at very low loads; input power < 300 mW at no-load operation for a typical adapter application n Standby indication pin to indicate low output power consumption 2.3 Protection features n Safe restart mode for system fault conditions n Continuous mode protection by means of demagnetization detection (zero switch-on current) n Accurate and adjustable versatile Overvoltage Protection (OVP) (latched) n Short winding protection n Undervoltage protection (foldback during overload) TEA1553T NXP Semiconductors GreenChip II SMPS control IC n n n n n n Overtemperature Protection (OTP) (latched) Low and adjustable Overcurrent Protection (OCP) trip level General purpose LOCK input for external protection Mains voltage-dependent operation-enabling level Soft (re)start Advanced Overpower Protection (OPP) functions 3. Applications Besides typical application areas, i.e. adapters and chargers, the device can be used in all applications that demand an efficient and cost effective solution up to 250 W. 4. Ordering information Table 1. Ordering information Type number TEA1553T Package Name Description Version SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 2 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC 5. Block diagram TEA1553T VCC 9 SUPPLY MANAGEMENT INTERNAL UVLO SUPPLY GND 11 S1 START VALLEY 16 DEM LOGIC + 80 mV 4 6, 7 HVS CLAMP Vmains(oper)(en) VOLTAGE CONTROLLED OSCILLATORS STDBY 8 DRAIN START UP CURRENT SOURCE FREQUENCY CONTROL OVERVOLTAGE PROTECTION 300 Ω UP/DOWN COUNTERS IVCOADJ 2 OVPFCAP 5.6 V VCOADJ 1 DRIVER LOGIC 5 DRIVER Istartup(soft) Iprot(CTRL) CTRL 14 −1 LEB POWER-ON RESET 0.5 V S Q S2 BLANK UVLO R Q + MAXIMUM ON-TIME PROTECTION 0.88 V OVERPOWER PROTECTION CSTART MINIMUM FREQ. ENABLING AND TIMING 15 300 Ω IAOP ADVANCED OVERPOWER PROTECTION ENABLE/DISABLE 3 ISENSE 5.6 V 0.5 V S3 LOCK LOCK DETECT 13 300 Ω 12 VCC5V S Q 5.6 V 5 V/1 mA (MAX) 2.5 V VCC < 4.5 V R Q OVERTEMPERATURE PROTECTION 014aaa004 Fig 1. Block diagram of TEA1553T TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 3 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC 6. Pinning information 6.1 Pinning VCO ADJ 1 16 DEM OVPFCAP 2 15 CSTART ISENSE 3 14 CTRL STDBY 4 13 LOCK TEA1553T DRIVER 5 12 VCC5V HVS 6 11 GND HVS 7 10 n.c. DRAIN 8 9 VCC 014aaa000 Fig 2. Pin configuration for TEA1553T 6.2 Pin description Table 2. Pin description Symbol Pin Description VCOADJ 1 Voltage Controlled Oscillator (VCO) adjustment input OVPFCAP 2 OVP filter timing capacitor ISENSE 3 programmable current sense input STDBY 4 standby control output DRIVER 5 gate driver output HVS 6 high voltage safety spacer, not connected HVS 7 high voltage safety spacer, not connected DRAIN 8 drain of external MOS switch, input for start-up current and valley sensing VCC 9 supply voltage n.c. 10 not connected GND 11 ground VCC5V 12 5 V output LOCK 13 LOCK input (“general purpose input for switching off the IC”). CTRL 14 control input CSTART 15 IPEAK reduction timing capacitor DEM 16 input from auxiliary winding for demagnetization timing, OVP and OPP TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 4 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC 7. Functional description The TEA1553T is a controller for a compact flyback converter, with the IC situated on the primary side. An auxiliary winding of the transformer provides demagnetization detection and powers the IC after start-up. V MAINS OUTPUT TEA1553T 9 VCC 10 n.c. 11 12 13 14 15 16 GND VCC5V DRAIN HVS 7 HVS 6 DRIVER LOCK STDBY CTRL ISENSE CSTART OVPFCAP DEM 8 VCOADJ 5 POWER MOSFET 4 3 2 RSENSE 1 RDEM 014aaa001 (1) If a 600 V MOSFET is used, the DRAIN connection can be made directly to the Vin; a center-tap from the transformer is not necessary. Fig 3. Basic application The TEA1553T operates in multi modes, see Figure 4. TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 5 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC f 125 kHz VCO FIXED quasi-resonant 25 kHz POWER 014aaa002 Fig 4. Multi mode operation The next converter stroke is started only after demagnetization of the transformer current (zero current switching), while the drain voltage has reached the lowest voltage to prevent switching losses (green function). The primary resonant circuit of primary inductance and drain capacitor ensures this quasi-resonant operation. The design can be optimized in such a way that zero voltage switching can be achieved over almost the whole of the universal mains range. To prevent very high frequency operation at lower loads, the quasi-resonant operation changes smoothly in fixed frequency Pulse Width Modulation (PWM) control. At low power levels, the frequency is controlled via the Voltage Controlled Oscillator (VCO), down to a minimum of about 25 kHz. At very low power levels (standby), a cycle skipping mode will be activated. 7.1 Start-up, mains enabling operation level and undervoltage lock-out Initially, the IC is self-supplying from the rectified mains voltage via pin DRAIN. Supply capacitor CVCC is charged by the internal start-up current source to a level of about 4 V or higher, depending on the drain voltage. Once the drain voltage exceeds Vmains(oper)(en) (mains-dependent operation-enabling voltage), the start-up current source will continue charging capacitor CVCC (switch S1 will be opened); see Figure 1. The IC will activate the power converter as soon as the voltage on pin VCC passes the Vstartup level. The IC supply is taken over by the auxiliary winding as soon as the output voltage reaches its intended level and the IC supply from the mains voltage is subsequently stopped for high efficiency operation (green function). The moment the voltage on pin VCC drops below the Vth(UVLO) (undervoltage lock-out) level, the IC stops switching and enters a safe restart from the rectified mains voltage. Inhibiting the auxiliary supply by external means causes the converter to operate in a stable, well defined burst mode. (See Figure 14 and Figure 15). 7.2 Supply management All (internal) reference voltages are derived from a temperature compensated, on-chip band gap circuit. TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 6 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC 7.3 Current mode control Current mode control is used for its good line regulation behavior. The on-time, is controlled by the internally inverted control pin voltage, which is compared with the primary current information. The primary current is sensed across an external resistor. The driver output is latched in the logic, preventing multiple switch-on. The internal control voltage is inversely proportional to the external control pin voltage, with an offset of 1.5 V. This means that a voltage range from 1 to 1.5 V on pin CTRL will result in an internal control voltage range from 0.5 V to 0 V (a high external control voltage results in a small duty cycle). 7.4 Oscillator The maximum fixed frequency of the oscillator is set by an internal current source and capacitor. The maximum frequency is reduced once the control voltage enters the VCO control window. It then changes linearly with the control voltage until the minimum frequency is reached (see Figure 5 and Figure 6). Vsense(max) 0.52 V 1V (TYP) 1.5 V (TYP) VCTRL 014aaa003 Fig 5. The Vsense(max) voltage as a function of VCTRL f 125 kHz 25 kHz VCO2 LEVEL VCO1 LEVEL Vsense(max) 014aaa005 Fig 6. The VCO frequency as a function of Vsense (max) TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 7 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC 7.5 VCO adjust The VCOADJ pin can be used to set the VCO operation point. As soon as the peak voltage on the sense resistor is controlled below half the voltage on the VCOADJ pin (VCO1 level), frequency reduction will start. (The actual peak voltage on Rsense will be somewhat higher due to switch-off delay, see Figure 8.) The frequency reduction will stop about 50 mV lower (VCO2 level), when the minimum frequency is reached. A current of typically 10 µA flows out of the VCOADJ pin, enabling the VCO operation point to be set with a single resistor. When a more low-ohmic connection is desired (e.g. due to noise), a voltage divider can be made from the VCC5V pin (see Figure 7). 1.5 V − VCTRL CURRENT COMPARATOR CTRL DRIVER DRIVER ISENSE VCC5V ×2 5V Vx V VCOADJ I OSCILLATOR 014aaa006 Fig 7. Implementation of STDBY and cycle skipping functionality TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 8 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC fs (kHz) fmax dV4 dV3 fmin dV2 dV1 Vx (V) VCOADJ STDBY (V) 5 0 Vx (V) CYCLE SKIPPING “1” “0” Vx (V) 014aaa007 (1) The voltage levels dV1, dV2, dV3 and dV4 are fixed in the IC to 50 mV (typ.), 18 mV (typ.), 40 mV (typ.) and 15 mV (typ.) respectively. The level at which the VCO mode of operation starts/ends can be externally controlled with the VCOADJ pin. Fig 8. Signal diagram for STDBY and cycle skipping functionality 7.6 Cycle skipping At very low power levels, a cycle skipping mode will be activated. A high control voltage will reduce the switching frequency to a minimum of 25 kHz. If the voltage on the control pin is raised even more, switch-on of the external power MOSFET will be inhibited until the voltage on the control pin has dropped to a lower value again (see Figure 8). For system accuracy, the absolute voltage on the control pin is not used to trigger the cycle skipping mode. Instead, a signal derived from the internal VCO will be used. If the no-load requirement of the system is such that the output voltage can be regulated to its intended level at a switching frequency of 25 kHz or above, the cycle skipping mode will not be activated. 7.7 STDBY output The STDBY output pin can be used to drive an external NPN or FET, VSTDBY = 5 V, in order to switch off a Power Factor Correction (PFC) circuit. The STDBY output is activated by the internal VCO: as soon as the VCO has reduced the switching frequency to almost the minimum frequency of 25 kHz, the STDBY output will be activated (see Figure 8). The STDBY output will go low again as soon as the VCO allows a switching frequency close to the maximum frequency of 125 kHz. TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 9 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC 7.8 Demagnetization The system will be in discontinuous conduction mode all the time. The oscillator will not start a new primary stroke until the secondary stroke has ended. Demagnetization features a cycle-by-cycle output short-circuit protection by immediately lowering the frequency (longer off-time), thereby reducing the power level. Demagnetization recognition is suppressed during the first tsup(xfmr_ring) time. This suppression may be necessary in applications where the transformer has a large leakage inductance and at low output voltages/start-up. 7.9 Overvoltage protection An OVP mode is implemented in the GreenChip series. For the TEA1553T, this works by sensing the auxiliary voltage via the current flowing into pin DEM during the secondary stroke. The auxiliary winding voltage is a well-defined replica of the output voltage. Any voltage spikes are averaged by an internal filter. Pin OVPFCAP is used to program the OVP function as follows: 1. Pin grounded: OVP is disabled. 2. Pin at 5 V (e.g. connected to pin 12, the VCC5V pin): the internal OVP circuit is enabled. 3. A capacitor is connected from the pin to the ground: this capacitor is used to set the number of OVP events that can occur before the logic determines that an actual OVP condition exists. The minimum timing is the internal OVP timing. In the last case, the number of OVP events can be set by an external capacitor connected to pin OVPFCAP: I ch ( OVPFCAP ) × t p ( OVPFCAP ) C OVP = n × ---------------------------------------------------------------------V OVPFCAP Where n is the number of OVP counts which are allowed to occur before an actual OVP state is detected. If the output voltage exceeds the OVP trip level, an internal counter starts counting subsequent OVP events. The counter has been added to prevent incorrect OVP detections which could occur during ESD / lightning events. If the output voltage exceeds the OVP trip level a few times, and then does not exceed it in the next cycle, the internal counter will count down twice as fast as it counted up. However, when typically 10 cycles of subsequent OVP events are detected, the IC assumes a true OVP state exists and the OVP circuit switches the MOSFET off. Next, the controller waits until the Vth(UVLO) level is reached on pin VCC, and then capacitor CVCC is recharged to the Vstartup level. Operation only recommences when the VCC voltage drops below a level of about 4.5 V, in practice this only occurs when the mains input voltage has been disconnected for a short period of time The output voltage at which the OVP function trips, Vtrip(OVPFCAP), can be set by the demagnetization resistor, RDEM: TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 10 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC NS V trip ( OVPFCAP ) = ----------- × ( I ovp × R DEM + V CL ( pos ) ) N aux Where Ns is the number of secondary turns and Naux is the number of auxiliary turns of the transformer. Current Iovp is internally trimmed. The value of the demagnetization resistor, RDEM, can be adjusted to the turns ratio of the transformer, thus making an accurate OVP possible. 7.10 Valley switching (See Figure 9.) A new cycle starts when the power switch is switched on. After the ‘on-time’ (which is determined by the ‘sense’ voltage and the internal control voltage), the switch is opened and the secondary stroke starts. After the secondary stroke, the drain 1 voltage shows an oscillation with a frequency of approximately ----------------------------------------------------(2 × π × ( L p × Cd ) ) where Lp is the primary self inductance of the transformer and Cd is the capacitance on the drain node. As soon as the oscillator voltage is high again and the secondary stroke has ended, the circuit waits for the lowest drain voltage before starting a new primary stroke. This method is called valley detection. Figure 9 shows the drain voltage together with the valley signal, the signal indicating the secondary stroke and the oscillator signal. In an optimum design, the reflected secondary voltage on the primary side will force the drain voltage to zero. Thus, zero voltage switching is possible, preventing large capacitive 1 2 losses P = --- × C × V × f , and allowing high frequency operation, which results in small 2 and cost effective inductors. TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 11 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC primary stroke secondary stroke secondary ringing drain valley secondary stroke (2) (1) oscillator 014aaa027 (1) Start of new cycle at lowest drain voltage. (2) Start of new cycle in a classical PWM system at high drain voltage. Fig 9. Signals for valley switching 7.11 Overcurrent protection The cycle-by-cycle peak drain current limit circuit uses the external source resistor to measure the current accurately. This allows optimum size of the transformer core to be determined (cost issue). The circuit is activated after the leading edge blanking time, tleb. The OCP protection circuit limits the ‘sense’ voltage to an internal level. 7.12 Overpower protection During the primary stroke, the rectified mains input voltage is measured by sensing the current drawn from pin DEM. This current is dependent on the mains voltage, according to the following formula: V aux N × V mains I DEM ≈ -------------- ≈ --------------------------R DEM R DEM N aux Where: N = ----------Np The current information is used to adjust the peak drain current, which is measured via pin ISENSE. The internal compensation is such that a maximum output power can be achieved that is almost mains independent. TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 12 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC The OPP curve is given in Figure 10. Vsense(max) 0.52 V (TYP) 0.30 V (TYP) −500 µA (TYP) −120 µA (TYP) IDEM 014aaa009 Fig 10. OPP correction curve 7.13 Advanced overpower timing via pin CSTART Overload conditions might lower the switching frequency below 20 kHz, since demagnetization prevents next cycle occurrence before the transformer current reaches zero (demagnetization protection). To prevent audible noise, an extra timer of typically 25 kHz is added. When the timer is activated (the frequency is typically below 25 kHz), a current (IAOP) of approximately 10 µA is injected into the external soft-start resistor and capacitor. The current that is being injected is dependent on the VSENSE voltage and the duty cycle, see also Figure 11 and Figure 12. IAOP (µA) 10 δ ~ 50% 7.5 δ ~ 0% 5 0.5 VSENSE(V) 014aaa010 Fig 11. IAOP as a function of VSENSE The current injection results in a decrease of the primary peak current and a higher frequency. The injection is only possible when the voltage on the control pin is below 0.5 V and the CSTART voltage is above 2.5 V. The current injection is disabled when VCTRL > 0.5 V (that is, in normal operation and also in frequency reduction mode), during start-up (CSTART timing) and when VSENSE > 0.5 V. TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 13 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC IAOP 0.5 V FAOP DRIVER RSS ISENSE 100 kΩ CSS VOCP Rsense GATE (δ) 014aaa011 Fig 12. Advanced overpower current injection The charging current, Iopp(adv), will flow as long as the voltage on pin ISENSE is below approximately 0.5 V. If it exceeds this value, the current source will start to limit the current Iopp(adv). 7.14 Minimum and maximum ‘on-time’ The minimum ‘on-time’ of the SMPS is determined by the Leading Edge Blanking (LEB) time. The IC limits the maximum ‘on-time’ to 50 µs. When the system requires an ‘on-time’ longer than 50 µs, a fault condition is assumed (e.g. Ci has been removed), the IC will stop switching and enter the safe restart mode. 7.15 Short winding protection After the leading edge blanking time, the short winding protection circuit is also activated. If the ‘sense’ voltage exceeds the short winding protection voltage, Vswp, the converter will stop switching. Once VCC drops below the Vth(UVLO) level, capacitor CVCC will be recharged and the supply will restart again. This cycle will be repeated until the short circuit is removed (safe restart mode). The short winding protection will also protect in case of a secondary diode short circuit. 7.16 LOCK input Pin 13 is a general purpose (high impedance) input pin, which can be used to switch off the IC. As soon as the voltage on this pin is raised above 2.5 V, switching will stop immediately. The voltage on the VCC pin will cycle between Vstartup and Vth(UVLO), but the IC will not start switching again until the latch function is reset. The latch is reset as soon as VCC drops below 4.5 V (typical value). The internal OVP and OTP will also trigger this latch (see Figure 3). The detection level of this input is related to the VCC5V pin voltage in the following way: 0.5 × VVCC5V ± 4 %. An internal Zener clamp of 5.6 V will protect this pin from excessive voltages. No internal filtering is done on this input. TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 14 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC 7.17 Overtemperature protection An accurate temperature protection is provided in the circuit. When the junction temperature exceeds the thermal shutdown temperature, the IC will stop switching. When VCC drops to Vth(UVLO), capacitor CVCC will be recharged to the Vstartup level, however the IC will not start switching again. Subsequently, VCC will drop again to the Vth(UVLO) level, and so on. Operation only recommences when the VCC voltage drops below a level of about 4.5 V, in practice this only occurs when the mains input voltage has been disconnected for a short period of time. 7.18 5 V output Pin 12 can be used for the supply of external circuitry. The maximum output current must be limited to 1 mA. If higher peak currents are required, an external RC combination should limit the current drawn from this pin to 1 mA maximum. The 5 V output voltage will be available as soon as the start-up voltage is reached. As the high voltage supply cannot supply the VCC5V pin during start-up or shutdown, during latched shutdown (via pin 13 or other latched protection such as OVP or OTP), the voltage is switched to zero. 7.19 Open/not connected CTRL pin protection If the CTRL pin is open/not connected, a fault condition is assumed and the converter will stop switching. Operation will recommence as soon as the fault condition is removed. 7.20 Soft start-up (pin ISENSE) To prevent transformer rattle during hiccup, the transformer peak current through the sense resistor, IDM, is slowly increased by the soft start function. This can be achieved by inserting a resistor and a capacitor between pin ISENSE (pin 3) and the sense resistor, Rsense. An internal current source charges the capacitor to V = Istartup(soft) × Rss, with a maximum of about 0.5 V. The start level and the time constant of the increasing primary current level can be adjusted externally by changing the values of Rss and Css. V sense ( max ) – ( I startup ( soft ) × R ss ) I DM = --------------------------------------------------------------------------------R sense τ = R ss × C ss The charging current Istartup(soft) will flow as long as the voltage on pin ISENSE is below approximately 0.5 V. If the voltage on pin ISENSE exceeds 0.5 V, the soft start current source will start limiting the current Istartup(soft). At the Vstartup level, the Istartup(soft) current source is completely switched off (see Figure 13). Since the soft start current Istartup(soft) is subtracted from pin VCC charging current, the RSS value will affect the VCC charging current level by a maximum of 60 µA (typical value). TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 15 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC Istartup(soft) 0.5 V startup DRIVER ISENSE overcurrent protection voltage RSS CSS Rsense 014aaa012 Fig 13. Soft start-up 7.21 Driver The driver circuit to the gate of the power MOSFET has a current sourcing capability of typically 170 mA and a current sink capability of typically 700 mA. This permits fast turning on and off of the power MOSFET for efficient operation. A low driver source current has been chosen to limit the ∆V/∆t at switch-on. This reduces the Electromagnetic Interference (EMI) and also limits the current spikes across Rsense. TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 16 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC 8. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are measured with respect to ground (pin 11); positive currents flow into the chip; pin VCC may not be current driven. The voltage ratings are valid provided other ratings are not violated; current ratings are valid provided the maximum power rating is not violated. Symbol Parameter Conditions Min Max Unit voltage on input voltage; continuous pin VCOADJ −0.4 +5 V Voltages VVCOADJ VOVPFCAP voltage on pin OVPFCAP continuous −0.4 +7 V VISENSE voltage on pin ISENSE current limited −0.4 - V VDRAIN voltage on pin DRAIN −0.4 +650 V VCC supply voltage continuous −0.4 +20 V VLOCK voltage on pin LOCK continuous −0.4 +7 V VCTRL voltage on pin CTRL −0.4 +5 V VCSTART voltage on pin CSTART −0.4 +7 V VDEM voltage on pin DEM current limited −0.4 - V IISENSE current on pin ISENSE input current −1 +10 mA ISTDBY current on pin STDBY −1 - mA IDRIVER current on d < 10 % pin DRIVER −0.8 +2 A IDRAIN current on pin DRAIN - +5 mA IO(VCC5V) output current on pin VCC5V −1 0 mA ICTRL current on pin CTRL - +5 mA IDEM current on pin DEM −1.25 +1.25 mA - 0.7 W −55 +150 °C Currents General Ptot total power dissipation Tstg storage temperature Tamb < 70 °C TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 17 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are measured with respect to ground (pin 11); positive currents flow into the chip; pin VCC may not be current driven. The voltage ratings are valid provided other ratings are not violated; current ratings are valid provided the maximum power rating is not violated. Symbol Parameter Tj junction temperature Conditions Min Max Unit −20 +145 °C ESD VESD electrostatic class 1 discharge voltage human body model pins 1 to 7 and pins 9 to 16 [1] - 2000 V pin 8 (DRAIN) [1] - 1500 V [2] - 200 V machine model [1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. [2] Equivalent to discharging a 200 pF capacitor through a 0.75 µH coil and a 10 Ω resistor. 9. Thermal characteristics Table 4. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in free air 110 K/W 10. Characteristics Table 5. Characteristics Tamb = 25 °C; VCC = 15 V; all voltages are measured with respect to ground (pin 11); currents are positive when flowing into the IC, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 1.0 1.2 1.4 mA - 100 300 µA Start-up current source (pin 8) IDRAIN current on pin DRAIN input current; VCC = 0 V; VI on pin DRAIN > 100 V with auxiliary supply; VI on pin DRAIN > 100 V VBR breakdown voltage 650 - - V Vmains(oper)(en) mains-dependent operation-enabling voltage 60 - 100 V VCC management (pin 9) Vstartup start-up voltage 10.3 11 11.7 V Vth(UVLO) undervoltage lockout threshold voltage 8.1 8.7 9.3 V Vhys hysteresis voltage 2.0 2.3 2.6 V Vstartup - Vth(UVLO) TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 18 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC Table 5. Characteristics …continued Tamb = 25 °C; VCC = 15 V; all voltages are measured with respect to ground (pin 11); currents are positive when flowing into the IC, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Ich(high) high charging current VI on pin DRAIN > 100 V; VCC < 3 V −1.2 −1 −0.8 mA Ich(low) low charging current VI on pin DRAIN > 100 V; 3 V < VCC < Vth(UVLO) −1.2 −0.75 −0.45 mA Irestart restart current VI on pin DRAIN > 100 V; Vth(UVLO) < VCC < Vstartup −650 −550 −450 µA ICC(oper) operating supply current no load on pin DRIVER 1.1 1.3 1.5 mA Demagnetization management (pin 16) VDEM voltage on pin DEM VCL(neg) negative clamp voltage 50 80 110 mV −0.5 −0.25 −0.05 V VCL(pos) positive clamp voltage voltage on pin DEM, II on pin DEM = 1 mA 0.5 0.7 0.9 V tsup(xfmr_ring) transformer ringing suppression time 1.1 1.5 1.9 µs voltage on pin DEM, II on pin DEM = −500 µA Pulse width modulator ton(min) minimum on-time - tleb - ns ton(max) maximum on-time 40 50 60 µs Oscillator fosc(low) low oscillator frequency VI on pin CTRL > 1.5 V 20 25 30 kHz fosc(high) high oscillator frequency VI on pin CTRL < 1 V 100 125 150 kHz VVCO(start) start VCO voltage peak voltage at pin ISENSE, where frequency reduction starts. See Figure 6 and Figure 8 - VCO1 - mV VVCO(max) maximum VCO voltage peak voltage at pin ISENSE, where the frequency is equal to fosc(low) - VCO1 − 50 - mV Duty cycle control (pin 14) Vmin(δmax) minimum voltage (maximum duty cycle) - 1.0 - V Vmax(δmin) maximum voltage (minimum duty cycle) - 1.5 - V ICTRL current on pin CTRL input current, VI on pin CTRL = 1.5 V −1 [1] −0.8 −0.5 µA VO(VCC5V) output voltage on pin VCC5V current on pin VCC5V = −1 mA 4.75 5.0 5.25 V IO(VCC5V) output current on pin VCC5V −1.0 - - mA 5 V output (pin 12) LOCK input (pin 13) TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 19 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC Table 5. Characteristics …continued Tamb = 25 °C; VCC = 15 V; all voltages are measured with respect to ground (pin 11); currents are positive when flowing into the IC, unless otherwise specified. Symbol Parameter Vtrip Conditions Min Typ Max Unit trip voltage 2.37 2.5 2.63 V VVCC(latch)(reset) latch reset voltage on Vtrip < 2.3 V pin VCC - 4.5 - V VLOCK/VVCC5V voltage on pin LOCK to voltage on pin VCC5V ratio −4 - +4 % Vtrip = 0.5 × VO( VCC5V) Advanced overpower timing via pin CSTART (pin 15) Ich(CSTART) charge current on pin CSTART −11.5 −10 −8.5 µA Vtrip(CSTART) trip voltage on pin CSTART 2.37 2.5 2.63 V Iopp(adv) advanced over-power VI on pin SENSE < 0.1 V protection current −11.5 −10 −8.5 µA fact(opp)(adv) advanced over-power VI on pin CTRL < 0.5 V protection activation and frequency VI on pin CSTART > 2.5 V 20 25 33 kHz −11.5 −10 −8.5 µA VCOadj input (pin 1) IVCOADJ current on pin VCOADJ Valley switch (pin 8) (∆V/∆t)vrec valley recognition voltage change with time −85 - +85 V/µs td(vrec-swon) valley recognition to switch-on delay time - 150 [1] - ns Current and short winding protection (pin 3) Vsense(max) maximum sense voltage ∆V/∆t = 0.1 V/µs 0.48 0.52 0.56 V tPD propagation delay ∆V/∆t = 0.5 V/µs - 140 185 ns Vswp short-winding protection voltage 0.83 0.88 0.96 V tleb leading edge blanking time 300 370 440 ns Istartup(soft) soft startup current 45 60 75 µA VI on pin SENSE < 0.5 V Overvoltage protection (pin 16 and pin 2) Iovp over-voltage protection current [2] 279 300 321 µA Ich(OVPFCAP) charge current on pin VI on pin OVPFCAP = 1 V OVPFCAP [3] −36 −32 −28 µA Idch(OVPFCAP) discharge current on pin OVPFCAP [3] 52 60 68 µA Vtrip(OVPFCAP) trip voltage on pin OVPFCAP 2.37 2.5 2.63 V tp(OVPFCAP) pulse duration on pin OVPFCAP 2.3 2.8 3.4 µs VI on pin OVPFCAP = 1 V TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 20 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC Table 5. Characteristics …continued Tamb = 25 °C; VCC = 15 V; all voltages are measured with respect to ground (pin 11); currents are positive when flowing into the IC, unless otherwise specified. Symbol QOVPFCAP Parameter charge on pin OVPFCAP Conditions Min Typ Max Unit charge delivered [4] −103 −90 −77 pC charge subtracted [5] 145 170 195 pC [6] - −120 - µA [7] - −500 - µA 4.75 5.0 5.25 V Overpower protection (pin 16) Iopp(DEM) over-power protection current on pin DEM Iopp(red)(DEM) reduced over-power protection current on pin DEM VISENSE < 0.3 V STDBY output (pin 4) VO(STDBY) output voltage on pin STDBY Isource(STDBY) source current on pin STDBY pin STDBY source current, VSTDBY = 1.5 V −25 −22 −20 µA Isink(STDBY) sink current on pin STDBY pin STDBY sink current, VI on pin STDBY = 1.5 V 2 - - mA Isource(DRIVER) source current on pin DRIVER pin DRIVER source current, VCC = 9.5 V; VI on pin DRIVER = 2 V - −170 −88 mA Isink(DRIVER) sink current on pin DRIVER pin DRIVER sink current, VCC = 9.5 V; VI on pin DRIVER = 2 V - 300 - mA VCC = 9.5 V; VI on pin DRIVER = 9.5 V 400 700 - mA VCC = 12 V - 11.5 12 V Driver (pin 5) Vo(max) maximum output voltage Temperature protection Tpl(max) maximum protection level temperature 130 140 150 °C Tpl(hys) protection level hysteresis temperature - 8 [1] - °C [1] Guaranteed by design. [2] Set by the demagnetization resistor, RDEM; see Section 7.9 “Overvoltage protection”. [3] Set by the OVPFCAP capacitor; see Section 7.9 “Overvoltage protection”. [4] Value equal to the product of the OVPFCAP current pulse width and the OVP filter timing charge current. [5] Value equal to the product of the OVPFCAP current pulse width and the OVP filter timing discharge current. [6] Set by the demagnetization resistor, RDEM; see Section 7.12 “Overpower protection”. [7] Maximum source voltage is limited to 0.3 V. TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 21 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC 11. Application information A converter using the TEA1553T consists of an input filter, a transformer with a third winding (auxiliary), and an output stage with a feedback circuit. Capacitor CVCC (at pin 9) buffers the supply voltage of the IC, which is powered via the high voltage rectified mains during start-up and via the auxiliary winding during operation. A sense resistor converts the primary current into a voltage at pin ISENSE (pin 3). The value of this sense resistor defines the maximum primary peak current. V MAINS OUTPUT PFC TEA1553T 9 VCC 10 n.c. 11 12 Θ 13 14 15 16 GND VCC5V LOCK CTRL DRAIN HVS 7 HVS 6 DRIVER STDBY ISENSE CSTART OVPFCAP DEM 8 VCOADJ POWER MOSFET 5 4 CSS 3 2 RS2 RSS RSENSE 1 RDEM 014aaa013 (1) The LOCK pin is used in this example for an additional external overtemperature protection. If this pin is not used, it must be tied to ground. Fig 14. Application diagram of TEA1553T with controlled PFC TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 22 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC VIN VDRAIN VO VCC VDRIVER Vmains(oper(en) VCC5V start-up sequence normal operation ovp normal operation output short-circuit 014aaa014 Fig 15. Typical waveforms TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 23 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT109-1 (SO16) TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 24 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC 13. Revision history Table 6. Revision history Document ID Release date Data sheet status Change notice Supersedes TEA1553T_1 20070703 Product data sheet - - TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 25 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 14.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GreenChip — is a trademark of NXP B.V. 15. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] TEA1553T_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 3 July 2007 26 of 27 TEA1553T NXP Semiconductors GreenChip II SMPS control IC 16. Contents 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Distinctive features . . . . . . . . . . . . . . . . . . . . . . 1 Green features . . . . . . . . . . . . . . . . . . . . . . . . . 1 Protection features . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Start-up, mains enabling operation level and undervoltage lock-out . . . . . . . . . . . . . . . . . . . . 6 Supply management. . . . . . . . . . . . . . . . . . . . . 6 Current mode control . . . . . . . . . . . . . . . . . . . . 7 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCO adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Cycle skipping. . . . . . . . . . . . . . . . . . . . . . . . . . 9 STDBY output. . . . . . . . . . . . . . . . . . . . . . . . . . 9 Demagnetization. . . . . . . . . . . . . . . . . . . . . . . 10 Overvoltage protection . . . . . . . . . . . . . . . . . . 10 Valley switching. . . . . . . . . . . . . . . . . . . . . . . . 11 Overcurrent protection . . . . . . . . . . . . . . . . . . 12 Overpower protection . . . . . . . . . . . . . . . . . . . 12 Advanced overpower timing via pin CSTART . 13 Minimum and maximum ‘on-time’ . . . . . . . . . . 14 Short winding protection . . . . . . . . . . . . . . . . . 14 LOCK input . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Overtemperature protection . . . . . . . . . . . . . . 15 5 V output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Open/not connected CTRL pin protection . . . 15 Soft start-up (pin ISENSE) . . . . . . . . . . . . . . . 15 Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 Thermal characteristics. . . . . . . . . . . . . . . . . . 18 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application information. . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 15 16 Contact information . . . . . . . . . . . . . . . . . . . . 26 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 July 2007 Document identifier: TEA1553T_1