K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM Document Title 2Mx36 & 4Mx18-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. Sep. 30. 2002 Advance 0.1 1. Delete the speed bins (FT : 7.5ns, 8.5ns / PP : 200MHz) Oct. 8. 2002 Preliminary 0.2 1. Change to the New JTAG scan order. Feb. 25, 2003 Preliminary 0.3 1. Add the comment about Vdd/Vddq wide by note on page 13. Mar. 10, 2003 Preliminary 0.4 1. Delete the 119 BGA package type. Aug. 18, 2004 Preliminary 0.5 1. Delete the 1.8V and 3.3V Vdd voltage level ( Change the part number to K7N6436(18)45M from K7N6436(18)31M ) Oct. 20, 2004 Preliminary Rev. No. The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM 64Mb NtRAM (Pipelined) Ordering Information Mode VDD Speed FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) 4Mx18 K7N641845M-Q(F)C25/16 Pipelined 2.5V 250/167MHz 2Mx36 K7N643645M-Q(F)C25/16 Pipelined 2.5V 250/167MHz Org. Part Number -2- PKG Temp C Q:100TQFP (Commercial F:165FBGA Temp.Range) Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM 2Mx36 & 4Mx18-Bit Pipelined NtRAMTM FEATURES GENERAL DESCRIPTION • 2.5V ±5% Power Supply. • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • Three Chip Enable for simple depth expansion with no data contention . • A interleaved burst or a linear burst mode. • Asynchronous output enable control. • Power Down mode. • TTL-Level Three-State Outputs. • 100-TQFP-1420A. • 165FBGA(11x15 ball aray) with body size of 15mmx17mm. The K7N643645M and K7N641845M are 75,497,472-bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The K7N643645M and K7N641845M are implemented with SAMSUNG′s high performance CMOS technology and is available in 100pin TQFP and 165FBGA packages. Multiple power and ground pins minimize ground bounce. FAST ACCESS TIMES PARAMETER Symbol -25 -16 Unit tCYC 4.0 6.0 ns Clock Access Time tCD 2.6 3.5 ns Output Enable Access Time tOE 2.6 3.5 ns Cycle Time LOGIC BLOCK DIAGRAM LBO A [0:20]or A [0:21] CKE ADDRESS REGISTER A2~A20 or A2~A21 CONTROL LOGIC CLK BURST ADDRESS COUNTER A0~A1 ADV WE BWx (x=a,b,c,d or a,b) CONTROL REGISTER CS1 CS2 CS2 WRITE ADDRESS REGISTER K A′0~A′1 WRITE ADDRESS REGISTER 2Mx36, 4Mx18 MEMORY ARRAY K DATA-IN REGISTER K DATA-IN REGISTER CONTROL LOGIC K OUTPUT REGISTER BUFFER OE ZZ 36 or 18 DQa0 ~ DQd7 or DQa0 ~ DQb8 DQPa ~ DQPd NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung. -3- Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM VDD VSS CLK WE CKE OE ADV A18 A17 A8 A9 89 88 87 86 85 84 83 82 81 BWb 90 BWc 94 91 BWd 95 BWa CS2 96 CS2 CS1 97 92 A7 98 93 A6 99 100 Pin TQFP (20mm x 14mm) 40 41 42 43 44 45 46 47 48 49 50 VSS A20 A19 A10 A11 A12 A13 A14 A15 A16 39 N.C. VDD 38 N.C. 35 A2 37 34 A3 A0 33 A4 36 32 A1 31 K7N643645M(2Mx36) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 VDD VDD VDD VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS VDD VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa PIN NAME SYMBOL PIN NAME A0 - A20 Address Inputs ADV WE CLK CKE CS1 CS2 CS2 BWx(x=a,b,c,d) OE ZZ LBO Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control TQFP PIN NO. SYMBOL 32,33,34,35,36,37,42, 43,44,45,46,47,48,49, 50,81,82,83,84,99, 100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 PIN NAME TQFP PIN NO. VDD VSS Power Supply(2.5V) Ground 14,15,16,41,65,66,91 17,40,67,90 N.C. No Connect 38,39 DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 VDDQ Output Power Supply 4,11,20,27,54,61,70,77 (2.5V) Output Ground 5,10,21,26,55,60,71,76 VSSQ Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -4- Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM VDD VSS CLK WE CKE OE ADV A19 A18 A8 A9 91 90 89 88 87 86 85 84 83 82 81 BWb 94 BWa N.C. 95 CS2 CS2 N.C. 92 CS1 97 93 A7 98 96 A6 99 100 Pin TQFP (20mm x 14mm) 50 A17 46 A13 49 45 A12 A16 44 A11 48 43 A20 A15 42 A21 47 41 A14 40 VSS 39 N.C. VDD 38 N.C. 35 A2 37 34 A3 36 33 A4 A1 32 A0 31 K7N641845M(4Mx18) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb8 DQb7 VSSQ VDDQ DQb6 DQb5 VDD VDD VDD VSS DQb4 DQb3 VDDQ VSSQ DQb2 DQb1 DQb0 N.C. VSSQ VDDQ N.C. N.C. N.C. 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 N.C. N.C. VDDQ VSSQ N.C. DQa0 DQa1 DQa2 VSSQ VDDQ DQa3 DQa4 VSS VDD VDD ZZ DQa5 DQa6 VDDQ VSSQ DQa7 DQa8 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C. PIN NAME SYMBOL PIN NAME A0 - A21 Address Inputs ADV WE CLK CKE CS1 CS2 CS2 BWx(x=a,b) OE ZZ LBO Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control TQFP PIN NO. SYMBOL 32,33,34,35,36,37,42, 43,44,45,46,47,48,49, 50,80,81,82,83,84,99, 100 85 88 89 87 98 97 92 93,94 86 64 31 PIN NAME TQFP PIN NO. VDD VSS Power Supply(2.5V) Ground 14,15,16,41,65,66,91 17,40,67,90 N.C. No Connect 1,2,3,6,7,25,28,29,30, 38,39,51,52,53,56,57, 75,78,79,95,96 DQa0~a8 DQb0~b8 Data Inputs/Outputs Data Inputs/Outputs 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24 VDDQ Output Power Supply 4,11,20,27,54,61,70,77 (2.5V) Output Ground 5,10,21,26,55,60,71,76 VSSQ NOTE : A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -5- Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM 165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW) K7N643645M(2Mx36) 1 2 3 4 5 6 7 8 9 10 11 A NC** A CS1 BWc BWb CS2 CKE ADV A A NC B NC A CS2 BWd BWa CLK WE OE A A NC** C DQPc NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPb D DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb E DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb F DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb G DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb H NC VDD NC VDD VSS VSS VSS VDD NC NC ZZ J DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa K DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa L DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa M DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa N DQPd NC VDDQ VSS NC NC NC VSS VDDQ NC DQPa P NC A A A TDI A1* TDO A A A NC R LBO A A A TMS A0* TCK A A A A Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. ** Checked NoConnect(NC) pins are resered for higher density address, i.e. 11B for 128Mb and 1A for 256Mb. PIN NAME SYMBOL PIN NAME A Address Inputs A0,A1 ADV WE CLK CKE CS1 CS2 CS2 BWx (x=a,b,c,d) Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs OE ZZ LBO Output Enable Power Sleep Mode Burst Mode Control TCK TMS TDI TDO JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output SYMBOL PIN NAME VDD VSS Power Supply Ground N.C. No Connect DQa DQb DQc DQd DQPa~Pd Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs VDDQ Output Power Supply -6- Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM 165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW) K7N641845M(4Mx18) 1 2 3 4 5 6 7 8 9 10 11 A NC** A CS1 BWb NC CS2 CKE ADV A A A B NC A CS2 NC BWa CLK WE OE A A NC** C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPa D NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa E NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa F NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa G NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa H NC VDD NC VDD VSS VSS VSS VDD NC NC ZZ J DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC K DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC L DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC M DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC N DQPb NC VDDQ VSS NC NC NC VSS VDDQ NC NC P NC A A A TDI A1* TDO A A A NC R LBO A A A TMS A0* TCK A A A A Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. ** Checked NoConnect(NC) pins are resered for higher density address, i.e. 11B for 128Mb and 1A for 256Mb. PIN NAME SYMBOL PIN NAME A Address Inputs A0,A1 ADV WE CLK CKE CS1 CS2 CS2 BWx (x=a,b) Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs OE ZZ LBO Output Enable Power Sleep Mode Burst Mode Control TCK TMS TDI TDO JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output SYMBOL PIN NAME VDD VSS Power Supply Ground N.C. No Connect DQa DQb DQPa, Pb Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs VDDQ Output Power Supply -7- Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM FUNCTION DESCRIPTION The K7N643645M and K7N641845M are NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2) are active . Output Enable(OE) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must be driven low for the device to drive out the requested data. Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipelined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time. BURST SEQUENCE TABLE LBO PIN HIGH First Address Fourth Address (Interleaved Burst, LBO=High) Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 BQ TABLE LBO PIN A1 1 1 0 0 A0 1 0 1 0 (Linear Burst, LBO=Low) LOW First Address Fourth Address Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 1 1 0 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0 Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed. -8- Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM STATE DIAGRAM FOR NtRAMTM WRITE READ READ BEGIN READ BEGIN WRITE DS RE AD IT WR DESELECT W R IT E D EA R BURST DS BURST READ BURST WRITE COMMAND DS READ WRI TE ST BUR DS DS BURST E BUR ST D REA DS WRITE BURST ACTION DESELECT BEGIN READ WRITE BEGIN WRITE BURST BEGIN READ BEGIN WRITE CONTINUE DESELECT Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) -9- Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS1 CS2 CS2 ADV WE BWx OE CKE CLK ADDRESS ACCESSED OPERATION H X X L X X X L ↑ N/A Not Selected X L X L X X X L ↑ N/A Not Selected X X H L X X X L ↑ N/A Not Selected X X X H X X X L ↑ N/A Not Selected Continue L H L L H X L L ↑ External Address Begin Burst Read Cycle X X X H X X L L ↑ Next Address Continue Burst Read Cycle L H L L H X H L ↑ External Address NOP/Dummy Read X X X H X X H L ↑ Next Address Dummy Read L H L L L L X L ↑ External Address Begin Burst Write Cycle X X X H X L X L ↑ Next Address Continue Burst Write Cycle L H L L L H X L ↑ N/A NOP/Write Abort X X X H X H X L ↑ Next Address Write Abort X X X X X X X H ↑ Current Address Ignore Clock Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by (↑). 3. A continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE(x36) WE BWa BWb BWc BWd OPERATION H X X X X READ L L H H H WRITE BYTE a L H L H H WRITE BYTE b L H H L H WRITE BYTE c L H H H L WRITE BYTE d L L L L L WRITE ALL BYTEs L H H H H WRITE ABORT/NOP Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). WRITE TRUTH TABLE(x18) WE BWa BWb OPERATION H X X READ L L H WRITE BYTE a L H L WRITE BYTE b L L L WRITE ALL BYTEs L H H WRITE ABORT/NOP Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). - 10 - Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM ASYNCHRONOUS TRUTH TABLE OPERATION ZZ OE I/O STATUS Sleep Mode H X High-Z Read L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z Notes 1. X means "Don′t Care". 2. Sleep Mode means power Sleep Mode of which stand-by current does not depend on cycle time. 3. Deselected means power Sleep Mode of which stand-by current depends on cycle time. ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on VDD Supply Relative to VSS VDD -0.3 to 3.6 V Voltage on Any Other Pin Relative to VSS VIN -0.3 to VDD+0.3 V Power Dissipation Storage Temperature PD 1.6 W TSTG -65 to 150 °C Operating Temperature TOPR 0 to 70 °C Storage Temperature Range Under Bias TBIAS -10 to 85 °C *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS(0°C ≤ TA ≤ 70°C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT VDD 2.375 2.5 2.625 V VDDQ 2.375 2.5 2.625 V VSS 0 0 0 V *Note : VDD and VDDQ must be supplied with identical vlotage levels. CAPACITANCE*(TA=25°C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL TEST CONDITION TYP MAX UNIT CIN VIN=0V - TBD pF COUT VOUT=0V - TBD pF *Note : Sampled not 100% tested. - 11 - Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM DC ELECTRICAL CHARACTERISTICS(VDD=2.5V ±5%, TA=0°C to +70°C) PARAMETER SYMBOL Input Leakage Current(except ZZ) IIL VDD=Max ; VIN=VSS to VDD Output Leakage Current IOL Output Disabled, Operating Current ICC ISB TEST CONDITIONS ISB1 ISB2 MAX UNIT -2 +2 µA µA -2 +2 VDD=Max IOUT=0mA -25 - TBD Cycle Time ≥ tCYC Min -16 - TBD Device deselected, IOUT=0mA, -25 - TBD -16 - TBD - TBD mA - TBD mA ZZ≤VIL, f=Max, All Inputs≤0.2V or ≥ VDD-0.2V Standby Current MIN Device deselected, IOUT=0mA, ZZ≤0.2V, f=0, All Inputs=fixed (VDD-0.2V or 0.2V) Device deselected, IOUT=0mA, ZZ≥VDD-0.2V, f=Max, All Inputs≤VIL or ≥VIH mA NOTES 1,2 mA Output Low Voltage VOL IOL=1.0mA - 0.4 V Output High Voltage VOH IOH=-1.0mA 2.0 - V Input Low Voltage VIL -0.3* 0.7 V Input High Voltage VIH 1.7 VDD+0.3** V 3 Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V VIH VSS VSS-0.4V VSS-0.8V 20% tCYC(MIN) TEST CONDITIONS (TA=0 to 70°C, VDD=2.5V ±5%, unless otherwise specified) PARAMETER Input Pulse Level Input Rise and Fall Time(Measured at 20% to 80%) Input and Output Timing Reference Levels Output Load VALUE 0 to 2.5V 1.0V/ns VDDQ/2 See Fig. 1 Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) +2.5V Output Load(A) Dout RL=50Ω VL=VDDQ/2 Zo=50Ω Dout 1667Ω 30pF* 1538Ω 5pF* * Including Scope and Jig Capacitance Fig. 1 - 12 - Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM AC TIMING CHARACTERISTICS (VDD=2.5V ±5%, TA=0 to 70°C) PARAMETER SYMBOL -25 -16 MIN MAX MIN MAX UNIT Cycle Time tCYC 4.0 - 6.0 - ns Clock Access Time tCD - 2.6 - 3.5 ns Output Enable to Data Valid tOE - 2.6 - 3.5 ns Clock High to Output Low-Z tLZC 1.5 - 1.5 - ns Output Hold from Clock High tOH 1.5 - 1.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 2.6 - 3.0 ns Clock High to Output High-Z tHZC - 2.6 - 3.0 ns Clock High Pulse Width tCH 1.7 - 2.2 - ns Clock Low Pulse Width tCL 1.7 - 2.2 - ns Address Setup to Clock High tAS 1.2 - 1.5 - ns CKE Setup to Clock High tCES 1.2 - 1.5 - ns Data Setup to Clock High tDS 1.2 - 1.5 - ns Write Setup to Clock High (WE, BWX) tWS 1.2 - 1.5 - ns Address Advance Setup to Clock High tADVS 1.2 - 1.5 - ns Chip Select Setup to Clock High tCSS 1.2 - 1.5 - ns Address Hold from Clock High tAH 0.3 - 0.5 - ns CKE Hold from Clock High tCEH 0.3 - 0.5 - ns Data Hold from Clock High tDH 0.3 - 0.5 - ns Write Hold from Clock High (WE, BWX) tWH 0.3 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.3 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.3 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 4. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC. The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions (0°C,2.625V) than tHZC, which is a Max. parameter(worst case at 70°C,2.375V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. - 13 - Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SLEEP MODE is dictated by the length of time the ZZ is in a High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP MODE. SLEEP MODE ELECTRICAL CHARACTERISTICS DESCRIPTION CONDITIONS SYMBOL ZZ ≥ VIH Current during SLEEP MODE MIN ISB2 MAX TBD ZZ active to input ignored tPDS 2 ZZ inactive to input sampled tPUS 2 ZZ active to SLEEP current tZZI ZZ inactive to exit SLEEP current tRZZI UNITS mA cycle cycle 2 cycle 0 SLEEP MODE WAVEFORM K tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z DON′T CARE - 14 - Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected. JTAG Block Diagram JTAG Instruction Coding IR2 IR1 IR0 SRAM CORE TDI BYPASS Reg. TDO Identification Reg. Instruction Reg. Control Signals TMS TCK TAP Controller TDO Output Notes 0 0 0 EXTEST Instruction Boundary Scan Register 1 0 0 1 IDCODE Identification Register 3 0 1 0 SAMPLE-Z Boundary Scan Register 2 0 1 1 BYPASS Bypass Register 4 1 0 0 SAMPLE Boundary Scan Register 5 1 0 1 RESERVED Do Not Use 6 1 1 0 BYPASS Bypass Register 4 1 1 1 BYPASS Bypass Register 4 NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. This instruction is not IEEE 1149.1 compliant. 2. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 3. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 5. SAMPLE instruction dose not places DQs in Hi-Z. 6. This instruction is reserved for future use. TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test Idle 1 1 Select DR 0 Exit2 DR 1 1 Update DR 0 - 15 - 1 Capture IR 0 0 Shift IR 1 1 Exit1 DR 0 Pause DR 1 Select IR 0 1 Capture DR 0 Shift DR 1 1 1 0 0 0 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM SCAN INFORMATION (165 FBGA ) SCAN REGISTER DEFINITION Part Instruction Register Bypass Register ID Register Boundary Scan 2Mx36 3 bits 1 bits 32 bits 89 bits 4Mx18 3 bits 1 bits 32 bits 89 bits ID REGISTER DEFINITION Part Revision Number (31:28) Part Configuration (27:18) Vendor Definition (17:12) Samsung JEDEC Code (11: 1) Start Bit(0) 2Mx36 0000 01001 00100 XXXXXX 00001001110 1 4Mx18 0000 01010 00011 XXXXXX 00001001110 1 BOUNDARY SCAN EXIT ORDER BIT PIN ID BIT PIN ID BIT PIN ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 6N 7N 10N 11P 8P 8R 9R 9P 10P 10R 11R 11H 11N 11M 11L 11K 11J 10M 10L 10K 10J 9H 10H 11G 11F 11E 11D 10G 10F 10E 10D 11C 11A 11B 10A 10B 9A 9B 10C 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 8A 8B 7A 7B 6B 6A 5B 5A 4A 4B 3B 3A 2A 2B 2C 1B 1A 1C 1D 1E 1F 1G 2D 2E 2F 2G 1H 3H 1J 1K 1L 1M 2J 2K 2L 2M 1N 2N 1P 79 80 81 82 83 84 85 86 87 88 89 1R 2R 3P 3R 2P 4R 4P 5N 6P 6R Internal BIT PIN ID Note: 1. NC and Vss pins included in the scan exit order are read as "X" ( i.e. don′t care). - 16 - Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM JTAG DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Power Supply Voltage VDD 2.375 2.5 2.625 V Input High Level VIH 1.7 - VDD+0.3 V Input Low Level VIL -0.3 - 0.7 V Output High Voltage VOH 2.0 - - V Output Low Voltage VOL - - 0.4 V Note NOTE : The input level of SRAM pin is to follow the SRAM DC specification. JTAG AC TEST CONDITIONS Symbol Min Unit Input High/Low Level Parameter VIH/VIL 2.5/0 V Input Rise/Fall Time TR/TF 1.0/1.0 ns VDDQ/2 V Input and Output Timing Reference Level Note JTAG AC Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tCHCH 50 - ns TCK High Pulse Width tCHCL 20 - ns TCK Low Pulse Width tCLCH 20 - ns TMS Input Setup Time tMVCH 5 - ns TMS Input Hold Time tCHMX 5 - ns TDI Input Setup Time tDVCH 5 - ns TDI Input Hold Time tCHDX 5 - ns SRAM Input Setup Time tSVCH 5 - ns SRAM Input Hold Time tCHSX 5 - ns Clock Low to Output Valid tCLQV 0 10 ns Note JTAG TIMING DIAGRAM TCK tCHCH tCHCL tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLCH TMS TDI PI (SRAM) tCLQV TDO - 17 - Oct. 2004 Rev 0.5 K7N643645M K7N641845M TIMING WAVEFORM OF READ CYCLE tCH tCL Clock tCYC tCES tCEH CKE tAS tAH A1 Address A2 tWS tWH tCSS tCSH tADVS tADVH A3 WRITE ADV OE tOE tHZOE tLZOE Data Out Q1-1 tCD tOH Q2-1 tHZC Q2-2 Oct. 2004 Rev 0.5 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4 Don′t Care Undefined Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM - 18 - CS K7N643645M K7N641845M TIMING WAVEFORM OF WRTE CYCLE tCH tCL Clock tCYC tCES tCEH CKE Address A2 A1 A3 WRITE ADV OE tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 tDH D3-2 D3-3 D3-4 tHZOE Data Out Q0-3 Q0-4 Oct. 2004 Rev 0.5 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Don′t Care Undefined Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM - 19 - CS K7N643645M K7N641845M TIMING WAVEFORM OF SINGLE READ/WRITE tCH tCL Clock tCYC tCES tCEH CKE Address A1 A2 A3 A4 Q1 Q3 A5 A6 A8 A7 A9 WRITE ADV OE tOE tLZOE Data Out Q6 Q7 tDH tDS Data In Q4 D2 Oct. 2004 Rev 0.5 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L D5 Don′t Care Undefined Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM - 20 - CS K7N643645M K7N641845M TIMING WAVEFORM OF CKE OPERATION tCL tCH Clock tCES tCEH tCYC CKE Address A1 A2 A3 A4 A5 A6 WRITE ADV OE tCD tLZC Data Out tHZC Q1 Q3 tDH tDS Data In Q4 D2 Oct. 2004 Rev 0.5 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Don′t Care Undefined Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM - 21 - CS K7N643645M K7N641845M TIMING WAVEFORM OF CS OPERATION tCH tCL Clock tCYC tCEH tCES CKE Address A1 A2 A3 A4 A5 WRITE ADV OE tHZC tOE tLZOE Data Out Q1 tCD tLZC Q4 Q2 tDS tDH Data In D3 Oct. 2004 Rev 0.5 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L D5 Don′t Care Undefined Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM - 22 - CS K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM PACKAGE DIMENSIONS 100-TQFP-1420A Units ; millimeters/Inches 0~8° 22.00 ±0.30 0.10 0.127 +- 0.05 20.00 ±0.20 16.00 ±0.30 14.00 ±0.20 0.10 MAX (0.83) 0.50 ±0.10 #1 0.65 (0.58) 0.30 ±0.10 0.10 MAX 1.40 ±0.10 1.60 MAX 0.50 ±0.10 - 23 - 0.05 MIN Oct. 2004 Rev 0.5 K7N643645M K7N641845M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAMTM 165 FBGA PACKAGE DIMENSIONS 15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array A B Top View C Side View D A F E G B Bottom View ∅H E Symbol Value Units Note Symbol Value Units A 17 ± 0.1 mm E 1.0 mm B 15 ± 0.1 mm F 14.0 mm C 1.3 ± 0.1 mm G 10.0 mm D 0.35 ± 0.05 mm H 0.50 ± 0.05 mm - 24 - Note Oct. 2004 Rev 0.5