Ordering number : EN7777A LA6572 Monolithic Linear IC 5-CH Driver for Mini Disc and Compact Disk Applications (BTL : 5CH) Overview The LA6572 power amplifier 5-channel (BTL) built-in. Features • Power amplifier 5-channel (BTL) built-in. • IO max 1A. • Level shift circuit built-in. • Three channels (2-1-1) of MUTE circuit (output ON/OFF) incorporated. Only CH5 normally ON. (Operative independently for each of MUTE1: CH1, 2, MUTE2: CH3, MUTE3: CH4. Inoperative for 3.3REG). • 3.3V power supply (3.3VREG) incorporated (PNP transistor connected externally). • With 3.3V power supply (3.3VREG) ON/OFF function (EN-REG) (Operative for 3.3VREG only (inoperative for BTL AMP). (3.3VREG: OFF with EN-REG: L, 3.3VREG: ON with EN-REG : H). • Operative for the fixed internal VREF (1.65V: TYP) for 5CH only. • Overheat protection circuit (thermal shutdown) built-in. Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Power supply voltage VCC max Maximum output current IO max Conditions Each output for channel 1 to 5. Ratings Unit 14 V 1 A Maximum input voltage VINB max 13 V MUTE pin voltage VMUTE 13 V Allowable operation Pd max Independent IC Mounted on a specified board * 0.8 W 2 Operating temperature Topr -30 to +85 °C Storage temperature Tstg -55 to +150 °C * Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 11007 TI IM B8-5621 No.7777-1/9 LA6572 Allowable Operating Range at Ta = 25°C Parameter Symbol Power supply Voltage Conditions Ratings VCC Unit 4.5 to 13 V Electrical Characteristics at Ta = 25°C, VCC1 = VCC2 = 8V, VREF = 1.65V, unless especially specified. Parameter Symbol Ratings Conditions min typ Unit max All Blocks No-load current drain ON ICC-ON All outputs ON *1 30 50 mA No-load current drain OFF ICC-OFF All outputs OFF *1 10 20 mA VREF input voltage range VREF-IN 0.5 VREF-OUT output voltage VREF-OUT 1.6 1.65 VREF-OUT output current I-VREF-OUT 2 5 VREF changeover voltage H VREF-SW-H External VREF selected (VREF-SW: H) VREF changeover voltage L VREF-SW-L Internal VREF selected (VREF-SW: L) Thermal shutdown temperature TSD Design guarantee value * VCC-1.5 V 1.7 V mA 3.5 V 1.5 V 200 °C -50 50 mV 0 VCC-1.5 150 175 BTL AMP (CH1 to CH5) Output offset voltage VOFF Voltage difference between outputs for BTL AMP, each channel. *2 Input voltage range VIN Input voltage range for input for OP-AMP. Output voltage VO Each voltage between VO+ and VO- when Closed-circuit voltage gain VG RL = 8Ω. *2 Input and output gain. Input OP-AMP: BUFFER Slew rate SR AMP Independent Multiply 2 between outputs. MUTE ON voltage VMUTE-ON Each MUTE *3 MUTE OFF voltage VMUTE-OFF Each MUTE *3 5.7 6.5 3.6 4 V V 4.4 deg 0.5 V/µs 2 V 0.5 V Input Amp Block Input voltage range VIN-OP Output offset voltage VOFF-OP Output current (SINK) SINK-OP Output current (SOURCE) SOURCE-OP 0 VCC-1.5 -10 10 V mV 2 *4 mA 300 500 3.18 3.3 5 10 µA Power Supply Block (PNP Transistor: 2SB632K-Use) 3.3V power supply output VOUT IO = 200mA REG-IN SINK current REG-IN-SINK Base current to external PNP Line regulation ∆VOLN 6V ≤ VCC ≤ 12V, IO = 200mA Load regulation ∆VOLD 5mA ≤ IO ≤ 200mA 3.3V power supply ON voltage REG-ON EN voltage at which 3.3V power is turned ON. *5 3.3V power supply OFF voltage REG-OFF EN voltage at which 3.3V power is turned OFF. *5 3.42 V 20 150 mV 50 200 mV 0.5 V mA 2 V *. This is design target value and is not measured. *1. Current dissipation that is a sum of VCC1 and VCC2 at no load. *2. Input AMP is a BUFFER AMP. VIN5+ of CH5 is connected to VREF-OUT (CH5) (internal VREF). *3. Voltage difference between both ends of load (8Ω). Output saturated. *4. The source of input OP-AMP is a constant current. As the 11kΩ resistance to the next stage is a load, pay due attention when setting the input OP-AMP gain. *5. Output ON with MUTE : “H”, output OFF with MUTE : “L” (HI impedance) No.7777-2/9 LA6572 Package Dimensions unit : mm (typ) 3251 17.8 (6.2) 19 (4.9) 7.9 10.5 36 1 2.0 0.3 0.65 18 0.8 0.25 0.1 2.45max (2.25) (0.5) 2.7 SANYO : HSOP36R(375mil) Pd max - Ta Allowable power dissipation, Pd max - W 3.0 Mounted on a Specified board : 114.3mm×76.1mm×1.6mm, glass epoxy 2.5 Mounted on a specified board 2.0 1.5 1.0 1.04 Independent IC 0.8 0.5 0 --40 --30 --20 0.42 0 20 40 60 Ambient temperature, Ta - °C 80 85 100 ILA00922 No.7777-3/9 LA6572 Pin Description Pin Name Pin Name Pin No. Input VIN1+ VIN1- 17 VIN1 VIN2+ 15 VIN2VIN2 19 VIN3+ VIN3- 23 VIN3 VIN4- 21 VIN4+ VIN4 30 VIN5+ VIN5- 32 VIN5 34 VO1+ VO1- 12 VO2+ VO2- 10 VO3+ VO3- 8 VO4+ VO4- 6 VO5+ VO5- 5 Output MUTE Equivalent Circuit Diagram Description Each input pin VIN*- 16 VIN* VCC* 20 18 22 VIN*+ 29 31 S-GND 33 Each output VCC* 13 11 VO* 9 7 RF 4 MUTE1 1 MUTE2 2 MUTE3 36 Turns ON/OFF the output for VCC* MUTE1 : CH1, 2, MUTE2 : CH3 and MUTE3 : CH4. Each MUTE operates independently. MUTE* 100kΩ MUTE : H output ON MUTE : L output OFF 100kΩ The output has a HI S-GND impedance when OFF EN-VREG EN-VREG 24 3.3VREG ON/OFF pin. EN-REG ”H” : ON EN-REG ”L” : OFF EN-REG 100kΩ 100kΩ S-GND No.7777-4/9 LA6572 Relation of MUTE and Power (VCC*) CH1 MUTE1 VCC1 CH2 MUTE2 CH3 MUTE3 CH4 VCC2 CH5 * Connect VCC1 and VCC2 externally (to reduce the effects of voltage drop in the internal metal wiring). * MUTE operates independently for each CH. Relation of Each Channel and VREF CH1 CH2 CH3 External VREF CH4 Internal VREF (1.65V : TYP) CH5 * CH1 through CH4 operate for external VREF. CH5 operates for internal VREF (1.65V (TYP) : fixed). EN-REG (3.3 VREG) Operation EN-REG voltage 3.3V power supply state H ON L OFF 3.3VREG : ON 3.3VREG : OFF EN-VREG 0.5V 2V Outline of Input and Output 22kΩ 11kΩ VIN* VIN- - VIN+- + Level shift 11kΩ 11kΩ + VREF-IN VO*+ 22kΩ 11kΩ - VREF-OUT + VO*- + + + No.7777-5/9 LA6572 Block Diagram MUTE1 1 MUTE1 CH1, 2 MUTE2 2 MUTE2 CH3 Thermal Shutdown CH4 MUTE3 Each MUTE operative independently 36 MUTE3 35 S-GND 34 VIN5 33 VIN5- 32 VIN5+ 31 VIN4 30 VIN4- 29 VIN4+ 28 VREF-IN FR FR 27 VREF-OUT(CH5) 26 REG-IN 25 REG-OUT 24 EN-REG 23 VIN3+ 22 VIN3- 21 VIN3 20 VIN2+ 19 VIN2- for a corresponding CH. “H” : Output ON 3 VO5- 4 “L” : Output OFF Power supply Level Shift VCC2 CH3, 4, 5 VO5+ 5 VO4+ 6 Level Shift CH5 CH4 VO4- 7 22kΩ 11kΩ - - + + 22kΩ 11kΩ - 8 CH3 VO3- + Level Shift VO3+ + 9 + + - FR FR VO2+ 10 + Level Shift 1.65V(TYP) CH2 11 VO1+ 12 + Level Shift VO2- CH1 VO1- 13 VCC1 14 3.3VREG - EN-REG : “H” :3.3VREG, ON “L” :3.3VREG, OFF CH1, 2 22kΩ 11kΩ Power supply - VIN1 15 VIN1- 16 17 22kΩ + 11kΩ + 22kΩ 11kΩ - VIN2 18 - + VIN1+ + + + - No.7777-6/9 LA6572 Pin Description Pin No. Pin Name 1 MUTE1 Description 2 MUTE2 3 VCC2 Power supply for CH3, 4, and 5. Short-circuited with VCC1. 4 VO5- Output pin (-) for channel 5 5 VO5+ Output pin (+) for channel 5 6 VO4+ Output pin (+) for channel 4 7 VO4- Output pin (-) for channel 4 8 VO3+ Output pin (+) for channel 3 9 VO3- Output pin (-) for channel 3 10 VO2+ Output pin (+) for channel 2 11 VO2- Output pin (-) for channel 2 12 VO1+ Output pin (+) for channel 1 13 VO1- Output pin (-) for channel 1 14 VCC1 Power supply for CH1, 2. Short-circuited with VCC2. 15 VIN1 Input pin for channel 1, input AMP output 16 VIN1- Input pin (-) for channel 1 17 VIN1+ Input pin (+) for channel 1 18 VIN2 Input pin for channel 2, input AMP output 19 VIN2- Input pin (-) for channel 2 20 VIN2+ Input pin (+) for channel 2 21 VIN3 Input pin for channel 3, input AMP output 22 VIN3- Input pin (-) for channel 3 23 VIN3+ Input pin (+) for channel 1 24 EN-REG 25 REG-OUT 26 REG-IN 27 VREF-OUT(CH5) 28 VREF-IN 29 VIN4+ Input pin (+) for channel 4 30 VIN4- Input pin (-) for channel 4 31 VIN4 Input pin for channel 4, input AMP output 32 VIN5+ Input pin (+) for channel 5 33 VIN5- Input pin (-) for channel 5 34 VIN5 Input pin for channel 5, input AMP output 35 S-GND Signal system GND 36 MUTE3 CH4 output ON/OFF CH1 and 2 output ON/OFF CH3 output ON/OFF 3.3V ON/OFF pin that operates with 3.3VREG. EN: H→3.3VREG:ON, EN: L→3.3VREG:OFF Collector of PNP transistor connected to output 3.3VREG. PNP transistor base connected VREF-AMP (CH5 output (TYP: 1.65V)) Reference voltage applied pin * Center frame (FR) becomes GND for the power system (P-GND). Set this to the minimum potential together with S-GND. No.7777-7/9 LA6572 Sample Application Circuit EN-REG LOADING MUTE3 1 MUTE1 MUTE3 36 2 MUTE2 S-GND 35 3 VCC2 VIN5 34 4 VO5- VIN5- 33 5 VO5+ VIN5+ 32 6 VO4+ VIN4 31 7 VO4- VIN4- 30 8 VO3+ VIN4+ 29 9 VO3- VREF-IN 28 MUTE2 SLED MOTOR M 2.2Ω 0.1µF SPINDLE MOTOR M 2.2Ω 0.1µF LOADING MOTOR M 2.2Ω 0.1µF MUTE1 FR VO2+ VREF-OUT(CH5) 27 11 VO2- REG-IN 26 12 VO1+ REG-OUT 25 13 VO1- EN-REG 24 14 VCC1 VIN3+ 23 15 VIN1 VIN3- 22 16 VIN1- VIN3 21 17 VIN1+ VIN2+ 20 18 VIN2 VIN2- 19 FOCUS COIL VCC 2.2Ω 0.1µF TRACKING COIL 10 2.2Ω 0.1µF FR VCC 3.3VREG VREF SPINDLE SLED TRACKING FOCUS Add a capacitor + resistor between outputs or between the output and GND as a countermeasure against oscillation of the output. No.7777-8/9 LA6572 Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 2007. Specifications and information herein are subject to change without notice. PS No.7777-9/9