Ordering number : ENA1499 Bi-CMOS LSI For CCD LV56081GP Charge Pump Power Supply Overview The LV56081GP is charge pump power supply for CCD. Functions • The charge pump boosts the +3.3V input by multiplying with +6, then by -3 to regulate the voltage to the specified level. • The output voltage is +15V, -5.5V necessary for CCD. • Soft start function incorporated, which reduces the inrush current at start of charge pump. • Short-circuit protection function incorporated. • Four types of operating frequency selectable. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Maximum supply voltage VDD max Allowable power dissipation Pd max Operating temperature Storage temperature Conditions Ratings Unit 3.5 V 0.8 W Topr -20 to +80 °C Tstg -40 to +125 °C with specified substrate *1 *1 : Specified substrate : 40mm × 50mm × 0.8mm, glass epoxy board Allowable Operating Ratings at Ta = 25°C, PGND = 0V Parameter Symbol Ratings Conditions min Supply voltage VDD Input CLK frequency CKIN 3.0 SEL=H *2 typ Unit max 3.3 3.45 0.1 8 V MHz Input High voltage VINH EN pin 0.7VDD VDD V Input Low voltage VINL EN pin -0.1 0.4 V *2 : Note that the charge pump frequency should be adjusted with S0/S1 so that it becomes 2MHz or less. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 61009 MS 20061207-S00003 No.A1499-1/7 LV56081GP Electrical Characteristics at Ta = 25°C, VDD = 3.3V, SGND = 0V, PGND = 0V,IH=20mA, IL=5mA, S0=H, S1=L, Unless otherwise specified Parameter Symbol Ratings Conditions min Circuit current dissipation IDD1 EN = L 15 30 µA EN = H no load 17 25 mA 20 mA IH ave VDD = 3.0V VL output load current IL ave VDD = 3.0V Reference voltage VREF VDD = 3.0 to 3.45V, design guarantee -8 mA 1.305 Ta = -20°C to +80°C, design guarantee Output voltage at OFF max IDD2 VH output load current Output voltage accuracy Unit typ V 1.239 1.37 V V VH 14.55 15 15.35 VL -5.65 -5.5 -5.25 -50 0 +50 VOFF After capacitive discharge VH holding time Toff VLoff → VHoff Protection circuit masking time Tmask VH load regulation ∆VH Load 1mA → 20mA VL load regulation ∆VL Load 0.5mA → 8mA Input pin current Iin Pins EN, S0, S1, SEL and CLK VH monitoring voltage VTvlon Power efficiency Peff Inrush current Irush Oscillation frequency f clk V mV 5 ms 18 ms 30 mV 50 12.6 mV 17.5 µA 22.5 8 CP+Regulator (VH+VL) V 70 1.5 % 2 600 mA 2.5 MHz Note : The design specification items are design guarantees and are not measured. Package Dimensions unit : mm (typ) 3322A Pd max -- Ta TOP VIEW SIDE VIEW BOTTOM VIEW (0.13) (0.125) 3.5 0.4 3.5 (C0.17) 24 2 1 0.5 (0.5) 0.8 SIDE VIEW Specified board: 40×50×0.8mm3 glass epoxy board. 0.8 0.6 0.4 0.36 0.2 0 -20 (0.035) 0.25 Allowable power dissipation, Pd max -- W 1.0 0 20 40 60 80 100 Ambient temperature, Ta -- °C SANYO : VCT24(3.5X3.5) No.A1499-2/7 LV56081GP TEST VL C33 VL C32 C31A PGND1 C31B Pin Assignment 24 23 22 21 20 19 17 C12A EN 3 16 C11A SGND 4 15 PVDD SVDD 5 14 C12B CLK 6 13 PGND 8 9 10 11 12 C11B 7 NC 2 C21A S1 VH C22 18 VM C13 VH C23 1 SEL S0 Top view Pin Function Pin No. Name Mode 1 S0 Charge pump frequency changeover pin 2 S1 Charge pump frequency changeover pin 3 EN System enable pin (Hi active) 4 SGND Small signal system GND pin 5 SVDD Small signal system VDD pin 6 CLK External CLK input pin 7 SEL CLK selector pin (L: built-in CLK, H: external CLK) 8 VH C23 VH (+15V) regulator output pin 9 VH C22 Boost voltage output (+6VDD) 10 C21A Boost capacitor connection pin (on the load transfer side) 11 NC 12 C11B Boost capacitor connection pin (driver side) 13 PGND +3-fold boost power GND pin 14 C12B Boost capacitor connection pin (driver side) 15 PVDD Power system VDD pin 16 C11A Boost capacitor connection pin (load transfer side) 17 C12A Boost capacitor connection pin (load transfer side) 18 VM C13 Boost voltage output (+3VDD) 19 C31B +2-fold and -1-fold boost capacitor connection pin (driver side) 20 PGND1 +2-fold and -1-fold boost power GND pin 21 C31A -1-fold boost capacitor connection pin (load transfer side) 22 VL C32 Boost voltage output (-3VDD) 23 VL C33 VL (-5.5V) regulator output pin 24 TEST Test pin (OPEN or GND short-circuited) No.A1499-3/7 LV56081GP Block Diagram 10µF /VDD VDD 3.3V 15 PVDD 14 SVDD 5 +3 times step up circuit 1µF /VDD 4 TSD PGND PGND1 To A bandgap voltage reference 12 16 C12B C11B 1µF /VDD 1µF /2VDD C11A 17 +3VDD 20 C12A 2.2µF /3VDD 18 VM C13 A C31B 19 0.22µF /3VDD C31A 1µF /3VDD PGND 13 VL C32 VL C33 21 22 23 1µF -1 times step up circuit -3VDD VL Reg +2 times step up circuit timing generator +6VDD sequence generator VH Reg 10 9 1µF /3VDD C21A 2.2µF /6VDD VH C22 2.2µF 8 VH C23 VH=+15V VL=-7.5V 2bitMUX 1 S0 EN 3 2 S1 2MHz oscillator divider TEST 24 MUX 6 7 SEL Lo : internal CLK Hi : external CLK CLK No.A1499-4/7 LV56081GP Short-circuit Protection VH and VL output pins incorporate the short-circuit protection function. When the output pins are short-circuited to allow the large current to flow, IC is latched OFF to interrupt output. To reset from the interrupted state, set the EN pin to L, then reset it again to H. Frequency Selection The charge pump operating frequency can be changed with S0 and S1 logics. For light load, the reactive load can be reduced by lowering the operating frequency. SEL logic also enables synchronous operation with external CLK. The charge pump is operated with the frequency equivalent to 1/2 of input CLK. (The IC internal oscillator is used for the sequence, so that it is normally ON regardless of SEL. For minimum 9.4ms after startup with the EN signal set to H, the IC internal clock is used to operate the charge pump with 1 MHz regardless of the input of SEL, S0, and S1 pins. After the 9.4ms(min) period, the charge pump frequency is changed over according to the state of SEL, S0, and S1 pins. The changeover frequency is set as shown in the table right. S0 CP operating frequency S1 SEL=L SEL=H L L 1MHz 1/2 CLK H L 500kHz 1/4 CLK L H 250kHz 1/8 CLK H H 125kHz 1/16 CLK SEL L IC internal oscillator H Synchronous operation with external CLK Internal Equivalent Circuit S0 pin S1 pin S1 S0 SEL pin clk clk/2 clk/4 clk/8 SEL D Q Q CLK pin B D Q D Q Q Q Q 2-input multiplexer VH regulator start signal L ⇒ H in 9.4ms (min) after EN = H Charge pump clock 4-input multiplexer D Q Y A Internal 1MHz Y Truth Table SEL Y L A H B Truth Table S0 S1 Y L L clk H L clk/2 L H clk/4 H H clk/8 External signal input pin Internal signal No.A1499-5/7 LV56081GP External clock signal startup sequence Set EN = H by setting VDD at 3V or more Stop at EN = L or over-current protection Never set VDD at 3V or less till the sequence is over (7.5ms after EN = L). VDD EN Charge pump (C23) Regulator (C23) S0 Frequency selection Do not attempt change the signal after 9.4ms from EN = H Frequency selection Do not attempt change the signal after 9.4ms from EN = H Frequency selection S1 Frequency selection Do not attempt change the signal after 9.4ms from EN = H Frequency selection Do not attempt change the signal after 9.4ms from EN = H Frequency selection SEL External clock selected Do not attempt change the signal after 9.4ms from EN = H External clock selected Do not attempt change the signal after 9.4ms from EN = H External clock selected SEL=L (Internal clock) * Internal 1MHz * CP clock 1MHz * CP clock 500kHz * CP clock 250kHz * CP clock 125kHz CLK SEL=H (External clock) * CP clock 1/2φ * CP clock 1/4φ * CP clock 1/8φ * CP clock 1/16φ Internal clock start at 1MHz 9.4ms (min) Steady operation Stop sequence 7.5ms (max) Internal clock start at 1MHz 9.4ms (min) Steady operation Stop sequence 7.5ms (max) * IC internal signal EN Pin and VDD Though the sequence operation is made at startup, startup is not effectuated if the internal circuit has not been reset. To reset the internal circuit, it is necessary to keep the EN pin at L till VDD becomes 3V or more. Note that operation with VDD and EN pin short-circuited cannot be made. Since the sequence operation is incorporated for stop of operation, the charge pump remains active till 7.5ms (max) passes after setting the EN pin to L. During this period, VDD must be kept at 3V or more to allow the internal sequence logic to operate correctly. No.A1499-6/7 LV56081GP Rise/fall Sequence EN 600mA max IDD VREF +6VDD +3VDD Charge pump output -3VDD VH VTvlon REG output VL 5.5ms 2ms 2ms 3.3ms 6.1ms * Toff 18.9ms *The VL startup time at VH ≥ 10V and after elapse of 6.1ms is the reference time for CLK = 2MHz. SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2009. Specifications and information herein are subject to change without notice. PS No.A1499-7/7