SEMTECH SC172

SC172
2A EcoSpeedTM Synchronous Step-Down
Regulator with Optional Ultrasonic Power Save
POWER MANAGEMENT
Features
Description

The SC172 is an integrated, synchronous 2A EcoSpeedTM
step-down regulator, which incorporates Semtech’s
advanced, patented adaptive on-time architecture to
achieve best-in-class performance in dynamic point-ofload applications. The input voltage range is 3V to 5.5V
with a programmable output voltage from 0.75V up to
95% x VIN. The device features low-RDS(ON) internal switches and optional PSAVE mode for high efficiency across
the output load range.
VIN: 3V to 5.5V
VOUT: 0.75V to 95% x VIN
 IOUT: Up to 2A
 Low RDS(ON) Switches
Up to 95% Peak Efficiency
 High Output Accuracy
 Small Ceramic Capacitors
 Power Good Pin (Open-Drain)
 Patented Adaptive On-Time Control:
Excellent Transient Response
Programmable Pseudo-fixed Frequency
 Fault Protection Features:
Cycle-by-Cycle Current Limit
Short Circuit Protection
Over and Under Output Voltage Protection
Over-Temperature
 Internal Soft start
 Ultrasonic Power Save
 Smart Power Save
 Ultra-Small Lead-Free 3x3mm, 10-Pin MLPD Package
 Fully WEEE and RoHS Compliant

Adaptive on-time control provides programmable pseudo-fixed frequency operation and excellent transient
performance. The switching frequency can be set from
200kHz to 1MHz - allowing the designer to reduce external LC filtering and minimize light load (standby) losses.
Disabling PSAVE operation reduces output voltage ripple
at light load for ceramic output capacitors.
Additional features include cycle-by-cycle current limit,
soft start, input UVLO and output OV protection, and
over temperature protection. The open-drain PGOOD
pin provides output status. Standby current is less than
10μA when disabled.
Applications





Networking Equipment, Embedded Systems
Medical Equipment, Office Automation
Instrumentation, Portable Systems
Consumer Devices (DTV, Set-top Box, ... )
5V POL Converters
The device is available in a low profile, thermally enhanced MLPD-3x3mm 10-pin package.
Typical Application Circuit
3 to 5.5V
VIN
BST
LX
SC172
VDD
FB
PGOOD
Enable /
Power Save
EN/PSV
PGND
October 11 , 2010
VOUT = 0.75V to 95% VIN
Power Good
TON
AGND
© 2010 Semtech Corporation
SC172
Pin Configuration
Ordering Information
BST
VDD
VIN
AGND
LX
TON
PGND
EN/PSV
PGOOD
FB
Device
Top Mark
Package(2)
SC172MLTRT(1)
172
MLPD-10 3x3
SC172EVB
Evaluation Board
Notes:
1) Available in tape and reel packaging only. A reel contains 3000
devices.
2) Available in lead-free packaging only. WEEE compliant and Halogen
free. This component and all homogenous sub-components are RoHS
compliant.
10 Pin MLPD
θJA= 40°C/W.
Marking Information
TOP MARKING
172
yyww
xxxx
yyww = Date Code(Example: 0952)
xxxx = Semtech Lot Number(Example: 3901)
© 2010 Semtech Corporation
SC172
Absolute Maximum Ratings
Recommended Operating Conditions
LX to GND(3)……………………… - 0.3(DC) to +6.0V(DC) Max
VIN to PGND, EN/PSV to AGND ………………… -0.3 to +6.0V
VIN to VDD…………………………………………………+0.3V
BST to LX ………………………………………… -0.3 to +6.0V
BST to PGND……………………………………
-0.3 to +12V
VDD to AGND, VOUT to AGND………………… -0.3V to +6.0V
FB, PGOOD, TON …………………………… -0.3 to VDD + 0.3V
AGND to PGND………………………………… -0.3 to +0.3V
Peak IR Reflow Temperature ……………….…………… 260°C
ESD Protection Level (2)………………………………………2kV
Supply Input Voltage……………………………… 3V to 5.5V
Maximum Continuous Output Current …………………… 2A
Thermal Information
Storage Temperature …………………………… -60 to +150°C
Maximum Junction Temperature ……………………… 150°C
Operating Junction Temperature ……………… -40 to +125°C
Thermal Resistance, Junction to Ambient(1) ………… 40°C/W
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NOTES(1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
(2) Tested according to JEDEC standard JESD22-A114-B
(3) Due to parasitic board inductance, the transient LX pin voltage at the point of measurement may appear larger than that which exists on
silicon. The device is designed to tolerate the short duration transient voltages that will appear on the LX pin due to the deadtime diode
conduction, for inductor currents up to the current limit setting of the device. See application section for details.
Electrical Characteristics
Unless specified: VIN =5V, TA=+25°C for Typ, -40°C to +85°C for Min and Max, TJ < 125°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
5.5
V
2.98
V
Input Supplies
VIN, VDD Input Voltage
VDD UVLO Threshold
3
Rising UVLO V TH
VDD UVLO Hysteresis
VIN, VDD Supply Current
2.75
2.85
100
200
EN/PSV= 0V
5
IOUT=0A, PSAVE, fSW=25kHz(1)
744
Forced Continuous Conduction Mode
EN floating, IOUT=0A , Not Switching
1000
mV
15
μA
Controller
FB On-Time Threshold
Frequency Programming Range
FB Input Bias Current
© 2010 Semtech Corporation
0.7425
0.75
0.7575
V
See RTON Calculation
200
1000
kHz
FB=VDD or 0V
-1
+1
μA
SC172
Electrical Characteristics (continued)
Unless specified: VIN =5V, TA=+25°C for Typ, -40°C to +85°C for Min and Max, TJ < 125°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Continuous Mode
VIN=5V, VOUT=3V, RTON=66.7kΩ
0.9
1
1.1
μs
Timing
On-Time
Minimum On-Time(1)
80
ns
Minimum Off-Time(1)
250
ns
Delay from PWM Switching to Output
Regulation
850
μs
LX - PGND
0
mV
25
kHz
Soft start
Soft start Time(1)
Ultrasonic Power Save
Zero-Crossing Detector Threshold
Ultrasonic Power Save Frequency
Power Good
Power Good Signal Threshold High
116
120
124
Power Good Signal Threshold Low
86
90
93
Power Good Threshold
%VOUT
VDD=3V
1
VDD=5V
2
PGOOD Delay Time(1)
ms
Noise Immunity Delay Time
5
Leakage
Power Good On-Resistance
µs
1
µA
10
20
Ω
Fault Protection
Output Under-Voltage Fault
FB with Respect to REF,
8 Consecutive Clocks
-30
-25
-20
%
Output Over-Voltage Fault
FB with Respect to REF
+16
+20
+24
%
Smart PowerSave
Protection Threshold
FB with Respect to REF
+7
+10
+13
%
OV, UV Fault Noise Immunity Delay
Over-Temperature Shutdown
© 2010 Semtech Corporation
OT Latched
5
μs
150
°C
SC172
Electrical Characteristics (continued)
Unless specified: VIN =5V, TA=+25°C for Typ, -40°C to +85°C for Min and Max, TJ < 125°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Enable/Power Save
Output Enabled
1
V
Output Disabled
EN/PSV Input Bias Current
EN/PSV = VDD or 0V
Power Save Enabled
Forced Continuous Conduction Mode
0.5
0.4
V
8.0
μA
60
EN/PSV floating
39
%VDD
41
44
%VDD
40
75
Ω
Gate Drivers
BST Switch On resistance
Internal Power MOSFETs
Valley Current Limit, VDD=5V
2.5
3.2
Valley Current Limit, VDD=3V
2
2.4
Current Limit
LX Leakage Current
A
VIN=5.5V, LX=0V, High Side
1
10
High Side
95
150
Low Side
75
120
Switch Resistance
Non-overlap time (1)
µA
mΩ
30
ns
Note:
(1) Typical value from EVB, not ATE tested.
© 2010 Semtech Corporation
SC172
Pin Descriptions (MLPD-10)
Pin #
Pin Name
1
BST
Bootstrap pin. A capacitor is connected between BST to LX to develop the floating voltage for the
high-side gate drive.
2
VIN
Power input supply voltage.
3
LX
Switching (Phase) node.
4
PGND
5
PGOOD
6
FB
Feedback input for switching regulator. Connect to an external resistor divider from the output to
program the output voltage.
7
EN/PSV
Tri-state pin. Enable input for switching regulator. Pull EN/PSV high to enable the part with power
save mode enabled. Connect EN/PSV to AGND to disable the switching regulator. Leave EN/PSV
floating to enable the IC in forced continuous conduction mode.
8
TON
9
AGND
10
VDD
Input power for internal control circuit. Needs 1mF decoupling capacitor from this pin to AGND.
PAD
Thermal pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally.
© 2010 Semtech Corporation
Pin Function
Power ground.
Open-drain Power Good indicator. High impedance indicates power is good. An external pull-up
resistor is required.
On-time set input. Set the on-time by a series resistor to AGND.
Analog Ground.
SC172
Block Diagram
10
VDD
9
AGND
Reference
EN
7
5
PGOOD
6
8
TON
VDD
VIN
2
On-Time
Generator
LX
Gate Drive
Control
3
VDD
PGND
4
Zero-Cross
Valley
Current Limit
© 2010 Semtech Corporation
BST
Control
Soft
Start
FB
1
R
SC172
Typical Characteristics
Output Voltage vs Output Current
Efficiency vs Output Current
3.350
100.0
Output Voltage (V)
Efficiency (%)
95.0
90.0
85.0
Vin=5V, Vo=3.3V,
LOUT: DS86C-B992AS-2R0N,
80.0
COUT=22mFx2
RTON = 90.9kOhm
Red: PSAVE Mode
Blue: Forced Continuous PWM Mode
75.0
70.0
3.344
RTON = 90.9kOhm
3.338
3.332
Blue: Forced Continuous PWM Mode
Red: PSAVE Mode
3.320
0
0.5
1
1.5
0
2
Output Current (A)
95.0
1.224
90.0
1.223
Output Voltage (V)
Efficiency (%)
85.0
80.0
Vin=5V, Vo=1.2V,
LOUT: DS86C-B992AS-2R0N
COUT=22mF+0.1mF
65.0
RTON = 24.9kOhm
Red: PSAVE Mode
Blue: Forced Continuous PWM Mode
60.0
1
1.5
2
Output Current (A)
Vin=5V, Vo=1.21V,
LOUT: DS86C-B992AS-2R0N
COUT=22mF+0.1mF
1.222
RTON = 24.9kOhm
Red: PSAVE Mode
Blue: Forced Continuous PWM
Mode
1.221
1.220
1.219
1.218
1.217
55.0
1.216
50.0
0
0.5
1
1.5
Output Current (A)
0
2
0.5
1
1.5
Output Current (A)
2
Output Voltage vs Output Current
Efficiency vs Output Current
1.225
95.0
Vo=1.21V, RTON =24.9kOhm
90.0
1.223
Output Voltage (V)
85.0
Efficiency (%)
0.5
Output Voltage vs Output Current
Efficiency vs Output Current
70.0
COUT=22mFx2
3.326
65.0
75.0
Vin=5V, Vo=3.3V,
LOUT: DS86C-B992AS-2R0N
80.0
75.0
Vo=1.2V, RTON = 24.9kOhm
70.0
COUT:22mF+0.1mF
Forced Continuous Mode
Red:Vin = 3.5V
Green: Vin = 4.0V
Blue: Vin = 5.0V
LOUT: DS86C-B992AS-2R0N
65.0
60.0
COUT:22mF+0.1mF
LOUT: DS86C-B992AS-2R0N,
Forced Continuous Mode
Black: Vin = 3.5V
1.220
1.218
1.215
Black: Vin = 3.5V
Red: Vin = 4V
Blue: Vin = 5.0V
1.213
55.0
1.210
50.0
0
0.5
1
1.5
Output Current (A)
© 2010 Semtech Corporation
2
0
0.5
1
1.5
Output Current (A)
2
SC172
Typical Characteristics
OCP Valley Threshold vs Ambient Temperature
Start up waveform ( VIN=5V, VOUT=1.2V, IOUT=2A,
Channel 1: 500mV/Div, Channel 4: 1A/Div, Time: 0.5ms/Div )
OCP Valley threshold (A)
3.5
3.2
V DD =5V
2.9
2.6
V DD =3V
2.3
2.0
-40
-20
0
20
40
60
80
Temperature (Degree C)
100 120
Load Transient Test (VIN=5V, VOUT=1.2V, IOUT= 0A to 2A,
IVIN Input Current In Shutdown vs Temperature
I VIN Input Current In Shutdown ( µA)
1.6
Forced Continuous Conduction Mode, LOUT =1.3µH,
COUT =2x22µF, Channel 1: 50mV/Div, Channel
2:5V/Div,Channel 4: 1A/Div, Time:10µs/Div)
1.4
1.2
V IN =5V
1.0
Black: VLX=GND
Blue: VLX=VIN
0.8
0.6
0.4
0.2
0.0
-40
-15
10
35
60
85
110
135
Temperature (°C)
Load Transient Test (VIN=5V, VOUT=1.2V, IOUT= 2A to 0A,
IBST Leakage Current vs Temperature
I BST Leakage Current ( µ A)
-0.0100
-0.0120
Forced Continuous Conduction Mode, LOUT =1.3µH,
COUT =2x22µF, Channel 1: 50mV/Div, Channel
2:5V/Div,Channel 4: 1A/Div, Time:10µs/Div)
VIN =5V
VBST=VIN
-0.0140
-0.0160
-0.0180
-0.0200
-40
-15
10
35
60
85
110 135
Temperature (°C)
© 2010 Semtech Corporation
SC172
Typical Characteristics
Load Transient Test (VIN=5V, VOUT=1.2V, IOUT= 0A to 2A,
PSAVE Mode Enabled, LOUT=1.3µH,COUT =2x22µF,Channel 1:
50mV/Div, Channel 2:5V/Div,Channel 4:1A/Div,Time:10µs/Div)
FB Voltage vs Temperature
0.755
FB Voltage (V)
0.753
0.750
Black:VDD=5.0V
Red: VDD=3.0V
0.748
0.745
-40
-15
10
35
60
85
110
135
Temperature (°C)
Low Side Switch On-State Resistance vs
Temperature
115
Load Transient Test (VIN=5V, VOUT=1.2V, IOUT= 2A to 0A,
PSAVE Mode Enabled, LOUT=1.3µH, COUT =2x22µF, Channel 1:
50mV/Div,Channel 2:5V/Div,Channel 4:1A/Div, Time:10µs/Div)
On-State Resistance (mΩ )
105
95
85
75
Blue: VDD=3.0V
Black: VDD=5.0V
65
55
-40
-15
10
35
60
85
110
135
Temperature (°C)
High Side Switch On-State Resistance vs
Temperature
150
On-State Resistance (mΩ )
140
130
120
110
100
Blue: VDD=3.0V
Black: VDD=5.0V
90
80
-40
-15
10
35
60
85
110
135
Temperature (°C)
© 2010 Semtech Corporation
10
SC172
Applications Information
SC172 Synchronous Buck Converter
The SC172 is a step down synchronous buck dc-dc regulator. The SC172 is capable of 2A operation at very high
efficiency in a tiny 3x3-10 pin package. The programmable operating frequency range of 200kHz – 1MHz enables
the user to optimize the solution for minimum board
space and optimum efficiency.
The adaptive on-time is determined by an internal oneshot timer. When the one-shot is triggered by the output ripple, the device sends a single on-time pulse to the
high-side MOSFET. The pulse period is determined by
VOUT and VIN; the period is proportional to output voltage
and inversely proportional to input voltage. With this
adaptive on-time arrangement, the device automatically
anticipates the on-time needed to regulate VOUT for the
present VIN condition and at the selected frequency.
The advantages of adaptive on-time control are:
•
The buck regulator employs pseudo-fixed frequency
adaptive on-time control. This control scheme allows
fast transient response thereby lowering the size of the
power components used in the system.
•
•
Input Voltage Range
•
The SC172 can operate with an input voltage ranging
from 3V to 5.5V.
•
Psuedo-fixed Frequency Adaptive On-time Control
The PWM control method used by the SC172 is pseudofixed frequency, adaptive on-time, as shown in Figure 1.
The ripple voltage generated at the output capacitor ESR
is used as a PWM ramp signal. This ripple is used to trigger the on-time of the controller.
VIN
CIN
Q1
TON
VFB
L
VLX
FB threshold
VOUT
VLX
Q2
ESR
COUT
+
FB
Figure 1 — PWM Control Method, VOUT Ripple
© 2010 Semtech Corporation
Predictable operating frequency compared to
other variable frequency methods.
Reduced component count by eliminating
the error amplifier and compensation components.
Reduced component count by removing the
need to sense and control inductor current.
Fast transient response — the response time
is controlled by a fast comparator instead of a
typically slow error amplifier.
Reduced output capacitance due to fast transient response
One-Shot Timer and Operating Frequency
The one-shot timer operates as shown in Figure 2. The
FB Comparator output goes high when VFB is less than
the internal 750mV reference. This feeds into the gate
drive and turns on the high-side MOSFET, and also starts
the one-shot timer. The one-shot timer uses an internal
comparator, timing capacitor, and a low pass filter (LPF)
which regenerates VOUT from LX. One comparator input
is connected to the filtered LX voltage, the other input is
connected to the capacitor. When the on-time begins,
the internal capacitor charges from zero volts through a
current which is proportional to VIN. When the capacitor
voltage reaches VOUT, the on-time is completed and the
high-side MOSFET turns off.
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN.
Under steady-state operation conditions, the switching
frequency can be determined from the on-time by the
following equation.
fSW =
VOUT
TON × VIN
11
SC172
Enable and Power-save Inputs
Applications Information (continued)
FB
-
REF
+
VOUT
VIN
VIN
PWM
S
Q
Hi-Side
and
Lo-Side
Gate
Drivers
R
On-Shot Timing
Generator
RTON
VLX
Q2
VOUT
LPF
Q1
L
ESR
COUT
FB
+
Time = K x VOUT/VIN
Figure 2 — On-Time Generation
The SC172 uses an external resistor to set the on-time
which indirectly sets the frequency. The on-time can
be programmed to provide operating frequency from
200kHz to 1MHz using a resistor between the TON pin
and ground. The resistor value is selected by the following equation.
R TON
V
1
= ( OUT ) ⋅
VFB
100pF ⋅ fSW
VOUT Voltage Selection
The switcher output voltage is regulated by comparing
VOUT as seen through a resistor divider at the FB pin to
the internal 750mV reference voltage, see Figure 3.
VOUT
To FB pin
The EN/PSV input is used to enable or disable the switching regulator. When EN/PSV is low (grounded), the switching regulator is off and in its lowest power state. When
off, the output power switches are tri-stated. When EN/
PSV is allowed to float, the pin voltage will float to 41%
of the voltage at VDD. The switching regulator turns on
with power-save disabled and all switching is in forced
continuous mode.
When EN/PSV is high (above 60% of the voltage at VDD),
the switching regulator turns on with ultrasonic powersave enabled. The SC172 ultrasonic power-save operation maintains a minimum switching frequency of 25kHz,
for applications with stringent audio requirements.
Forced Continuous Mode Operation
The SC172 operates in Forced Continuous Mode (FCM)
by floating the EN/PSV pin (see Figure 4). In this mode
one of the power MOSFETs is always on, with no intentional dead time other than to avoid cross-conduction.
This feature results in uniform frequency across the full
load range with the trade-off being poor efficiency at
light loads due to the high-frequency switching of the
MOSFETs.
FB Ripple
Voltage (VFB)
FB threshold
(750mV)
R1
R2
DC Load Current
Inductor
Current
Figure 3 — Output Voltage Selection
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage VOUT is offset by the output ripple according to
the following equation.
VOUT

R  V
= 0.75V ⋅  1 + 1  + RIPPLE
R
2

2 
On-time
(TON)
DH on-time is triggered when
VFB reaches the FB Threshold.
DH
DL
DL drives high when on-time is completed.
DL remains high until VFB falls to the FB threshold.
Figure 4 — Forced Continuous Mode Operation
© 2010 Semtech Corporation
12
SC172
Applications Information (continued)
Ultrasonic Power Save Operation
The SC172 provides ultrasonic power save operation at
light loads, with the minimum operating frequency fixed
at 25kHz. This is accomplished using an internal timer
that monitors the time between consecutive high-side
gate pulses. If the time exceeds 40µs, DL drives high to
turn the low-side MOSFET on. This draws current from
VOUT through the inductor, forcing both VOUT and VFB to
fall. When VFB drops to the 750mV threshold, the next DH
on-time is triggered. After the on-time is completed the
high-side MOSFET is turned off and the low-side MOSFET turns on. The low-side MOSFET remains on until the
inductor current ramps down to zero, at which point the
low-side MOSFET is turned off.
power save enabled, this can force VOUT to slowly rise
and reach the over-voltage threshold, resulting in a hard
shutdown. Smart power save prevents this condition.
When the FB voltage exceeds 10% above nominal (exceeds 825mV), the device immediately disables powersave, and DL drives high to turn on the low-side MOSFET.
This draws current from VOUT through the inductor and
causes VOUT to fall. When VFB drops back to the 750mV trip
point, a normal TON switching cycle begins. This method
prevents a hard OVP shutdown and also cycles energy
from VOUT back to VIN. Figure 6 shows typical waveforms
for the Smart Power Save feature.
VOUT drifts up to due to leakage
current flowing into COUT
Smart Power Save
Threshold (825mV)
VOUT discharges via inductor
and low-side MOSFET
Normal VOUT ripple
FB
threshold
DH and DL off
Because the on-times are forced to occur at intervals
no greater than 40µs, the frequency will not fall below
~25kHz. Figure 5 shows ultrasonic power save operation.
Single DH on-time pulse
after DL turn-off
Low-side
Drive (DL)
minimum fSW ~ 25kHz
FB Ripple
Voltage (VFB)
High-side
Drive (DH)
DL turns on when Smart
PSAVE threshold is reached
FB threshold
(750mV)
(0A)
Inductor
Current
Normal DL pulse after DH
on-time pulse
DL turns off when FB
threshold is reached
Figure 6 — Smart Power Save
Current Limit Protection
On-time
(TON)
DH On-time is triggered when
VFB reaches the FB Threshold
DH
40µs time-out
DL
After the 40µsec time-out, DL drives high if VFB
has not reached the FB threshold.
Figure 5 — Ultrasonic Power Save Operation
Smart Power Save Protection
The device features fixed current limiting, which is accomplished by using the RDS(ON) of the lower MOSFET for
current sensing. While the low-side MOSFET is on, the
inductor current flows through it and creates a voltage
across the RDS(ON). During this time, the voltage across the
MOSFET is negative with respect to ground. During this
time, If this MOSFET voltage drop exceeds the internal
reference voltage, the current limit will activate. The current limit then keeps the low-side MOSFET on and will
not allow another high side on-time, until the current in
the low-side MOSFET reduces enough to drop below the
internal reference voltage once more. This method regulates the inductor valley current at the level shown by ILIM
in Figure 7.
Active loads may leak current from a higher voltage into
the switcher output. Under light load conditions with
© 2010 Semtech Corporation
13
SC172
Power Good Output
Inductor Current
Applications Information (continued)
IPEAK
ILOAD
ILIM
Time
Figure 7 — Valley Current Limit
Setting the valley current limit to a value of ILIM results
in a peak inductor current of ILIM plus the peak-to-peak
ripple current. In this situation, the average (load) current
through the inductor will be ILIM plus one half the peakto-peak ripple current.
Soft start of PWM Regulator
Soft start is achieved in the PWM regulator by using
an internal voltage ramp as the reference for the FB
comparator. The voltage ramp is generated using an
internal charge pump which drives the reference from
zero to 750mV in ~1.8mV increments, using an internal
~500kHz oscillator. When the ramp voltage reaches
750mV, the ramp is ignored and the FB comparator
switches over to a fixed 750mV threshold. During soft start
the output voltage tracks the internal ramp, which limits
the start-up inrush current and provides a controlled soft
start profile for a wide range of applications. Typical soft
start ramp time is 0.85ms.
During soft start the regulator turns off the low-side
MOSFET on any cycle if the inductor current falls to zero.
This prevents negative inductor current, allowing the
device to start into a pre-biased output up to 90% of the
targeted output. This soft start operation is implemented
even if FCM is selected. FCM operation is allowed only
after PGOOD is high.
© 2010 Semtech Corporation
The power good (PGOOD) output is an open-drain output
which requires a pull-up resistor. When the output voltage is 10% below the nominal voltage, PGOOD is pulled
low. It is held low until the output voltage returns to the
nominal voltage. PGOOD is held low during soft start and
activated approximately 1ms after VOUT reaches regulation. The total PGOOD delay is typically 2ms.
PGOOD will transition low if the VFB pin exceeds +20% of
nominal, which is also the over-voltage shutdown threshold (900mV). PGOOD also pulls low if the EN/PSV pin is
low when VDD is present.
Output Over-Voltage Protection
Over-Voltage Protection (OVP) becomes active as soon
as the device is enabled. The threshold is set at 750mV +
20% (900mV). When VFB exceeds the OVP threshold, DL
latches high and the low-side MOSFET is turned on. DL
remains high and the controller remains off, until the EN/
PSV input is toggled or VDD is cycled. There is a 5μs delay
built into the OVP detector to prevent false transitions.
PGOOD is also low after an OVP event.
Output Under-Voltage Protection
When VFB falls to 75% of its nominal voltage (falls to
562.5mV) for eight consecutive clock cycles, the switcher
is shut off and the DH and DL drives are pulled low to turn
off the MOSFETs. The controller stays off until EN/PSV is
toggled or VDD is cycled.
VDD UVLO, and POR
Under-Voltage Lock-Out (UVLO) circuitry inhibits switching and tri-states the power FETs until VDD rises above
2.9V. An internal Power-On Reset (POR) occurs when
VDD exceeds 2.9V, which resets the fault latch and soft
start counter to begin the soft start cycle. The SC172 then
begins a soft start cycle. The PWM will shut off if VDD falls
below 2.7V.
14
SC172
Applications Information (continued)
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor
ripple current must be specified.
The maximum input voltage (VINMAX) is the highest specified input voltage. The minimum input voltage ( VINMIN) is
determined by the lowest input voltage after evaluating
the voltage drops due to connectors, fuses, switches, and
PCB traces.
The following parameters define the design.
•
•
•
•
Nominal output voltage (VOUT)
Static or DC output tolerance
Transient response
Maximum load current (IOUT)
There are two values of load current to evaluate — continuous load current and peak load current. Continuous
load current relates to thermal stresses which drive the
selection of the inductor and input capacitors. Peak load
current determines instantaneous component stresses and
filtering requirements such as inductor saturation, output
capacitors, and design of the current limit circuit.
The following values are used in this design.
VIN = 5V + 10%
VOUT = 1.0V + 4%
fSW = 800kHz
Load = 2A maximum
•
•
•
•
Frequency Selection
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the
power conversion efficiency.
The desired switching frequency is 800kHz which results
from using components selected for optimum size and
cost .
A resistor (RTON) is used to program the on-time (indirectly
setting the frequency) using the following equation un© 2010 Semtech Corporation
der zero load condition.
V
1
R TON = ( OUT ) ⋅
VFB 100pF ⋅ fSW
Since the fSW may increase by about 100kHz per Ampere,
RTON should be programmed at 600kHz under zero load
to achieve 800kHz at full load.
Calculating RTON results in the following solution.
RTON=22.2kW, we use RTON=22.1kW in real application.
Inductor Selection
In order to determine the inductance, the ripple current must first be defined. Low inductor values result in
smaller size but create higher ripple current which can
reduce efficiency. Higher inductor values will reduce the
ripple current/voltage and for a given DC resistance are
more efficient. However, larger inductance translates directly into larger packages and higher cost. Cost, size,
output ripple, and efficiency are all used in the selection
process.
The ripple current will also set the boundary for powersave operation. The switching will typically enter powersave mode when the load current decreases to 1/2 of the
ripple current. For example, if ripple current is 1A then
power-save operation will typically start for loads less
than 0.5A. If ripple current is set at 40% of maximum load
current, then power-save will start for loads less than 20%
of maximum current.
The inductor value is typically selected to provide a ripple current that is between 25% to 50% of the maximum
load current. This provides an optimal trade-off between
cost, efficiency, and transient performance.
During the DH on-time, voltage across the inductor is
(VIN - VOUT). The equation for determining inductance is
shown next.
VOUT
TON =
VINMAX ⋅ fSW
L=
(VIN - VOUT) × TON
IRIPPLE
15
SC172
Applications Information (continued)
Example
In this example, the inductor ripple current is set equal to
50% of the maximum load current. Therefore ripple current will be 50% x 2A or 1A. To find the minimum inductance needed, use the VIN and TON values that correspond
to VINMAX.
TON_VINMAX =
L=
1V
= 227ns
5.5V ⋅ 800kHz
(5.5V - 1V) • 227ns
= 1mH
1A
A larger value of 2µH is selected. This will decrease the
maximum IRIPPLE to 0.511A.
Note that the inductor must be rated for the maximum
DC load current plus 1/2 of the ripple current.
The ripple current under minimum VIN conditions is also
checked using the following equations.
TON_VINMIN =
IRIPPLE =
IRIPPLE_VINMIN =
1V
= 277ns
4.5V × 800kHz
(VIN - VOUT ) × TON
L
(4.5V - 1V) × 277ns
= 0.485A
2mH
Capacitor Selection
The output capacitors are chosen based on required ESR
and capacitance. The maximum ESR requirement is controlled by the output ripple requirement and the DC tolerance. The output voltage has a DC value that is equal
to the valley of the output ripple plus 1/2 of the peakto-peak ripple. Change in the output ripple voltage will
lead to a change in DC voltage at the output.
The design goal is for the output voltage regulation to be
±4% under static conditions. The internal 750mV reference tolerance is 1%. Assuming a 1% tolerance from the
FB resistor divider, this allows 2% tolerance due to VOUT
ripple. Since this 2% error comes from 1/2 of the ripple
voltage, the allowable ripple is 4%, or 40mV for a 1V output.
© 2010 Semtech Corporation
The maximum ripple current of 0.511A creates a ripple
voltage across the ESR. The maximum ESR value allowed
is shown by the following equations.
ESR MAX =
VRIPPLE
=
IRIPPLEMAX
40mV
0.51A
ESRMAX = 78.4 mΩ
The output capacitance is chosen to meet transient requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor current is at the peak, determines the required capacitance.
If the load release is instantaneous (load changes from
maximum to zero in < 1µs), the output capacitor must
absorb all the inductor’s stored energy. This will cause a
peak voltage on the capacitor according to the following
equation.
COUTMIN =
1
× IRIPPLEMAX )2
2
(VPEAK )2 - (VOUT )2
L × (IOUT +
Assuming a peak voltage VPEAK of 1.050V (50mV rise upon
load release), and a 2A load release, the required capacitance is shown by the next equation.
COUT MIN =
1
× 0.511A) 2
2
= 99 mF
(1.05V) 2 - (1.0V) 2
2mH × (2A +
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 750mV reference, the DL
output is high and the low-side MOSFET is on. During this
time, the voltage across the inductor is approximately
-VOUT. This causes a down-slope or falling di/dt in the
inductor. If the load di/dt is not much faster than the
-di/dt in the inductor, then the inductor current will tend
to track the falling load current. This will reduce the
excess inductive energy that must be absorbed by the
output capacitor, therefore a smaller capacitance can be
used.
The following can be used to calculate the needed capacitance for a given dILOAD/dt. Peak inductor current is
shown by the next equation.
16
SC172
Applications Information (continued)
ILPK = 2A +
1
× 0.511A = 2.26A
2
Rate of change of load current is
dI LOAD
0.6A
=
dt
1m s
IMAX = maximum load release = 2A
COUT
C OUT
increase the ESR of the output capacitors. It is also imperative to provide a proper PCB layout as discussed in
the Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a
small (~ 10pF) capacitor across the upper feedback resistor, as shown in Figure 8. This capacitor should be left
unpopulated unless it can be confirmed that doublepulsing exists. Adding the CTOP capacitor will couple
more ripple into FB to help eliminate the problem. An
optional connection on the PCB should be available for
this capacitor.
CTOP
I
I
L × LPK - MAX × dt
VOUT dILOAD
= ILPK ×
2 × ( VPK - VOUT )
2.26A
2A
2mH ×
× 1m s
1V
0.6A
= 2.26A ×
2 × (1.05V - 1V)
C OUT = 13 m F
Note that COUT is much smaller in this example, 13µF
compared to 99µF based upon a worst-case load release. To meet the two design criteria of minimum 13µF
and maximum 78mΩ ESR, select one capacitor rated at
22µF and 15mΩ ESR or less.
It is recommended that an additional small capacitor be
placed in parallel with COUT in order to filter high frequency switching noise.
Stability Considerations
Unstable operation is possible with adaptive on-time
controllers, and usually takes the form of double-pulsing or ESR loop instability.
Double-pulsing occurs due to switching noise seen at
the FB input or because the FB ripple voltage is too low.
This causes the FB comparator to trigger prematurely after the minimum off-time has expired. In extreme cases
the noise can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect operation. This form of instability can usually be avoided by
providing the FB pin with a smooth, clean ripple signal
that is at least 10mVp-p, which may dictate the need to
© 2010 Semtech Corporation
VOUT
To FB pin
R1
R2
Figure 8 — Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR Requirements section. The best method for checking stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
One simple way to solve this problem is to add trace resistance in the high current output path. A side effect of
adding trace resistance is a decrease in load regulation.
ESR Requirements
A minimum ESR is required for two reasons. One reason
is to generate enough output ripple voltage to provide
10mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insufficient ESR. The on-time control regulates the valley of
the output ripple voltage. This ripple voltage is the sum
of the two voltages. One is the ripple generated by the
ESR, the other is the ripple due to capacitive charging
17
SC172
Applications Information (continued)
Output Voltage Dropout
and discharging during the switching cycle. For most applications, the total output ripple voltage is dominated
by the output capacitors, typically SP or POSCAP devices.
For stability the ESR zero of the output capacitor should
be lower than approximately one-third the switching frequency. The formula for minimum ESR is shown by the
following equation.
The output voltage adjustable range for continuousconduction operation is limited by the fixed 320ns (typical) minimum off-time. When working with low input
voltages, the duty-factor limit must be calculated using
worst-case values for on and off times. The duty-factor
limitation is shown by the next equation.
ESR MIN =
3
2 × π × COUT × fSW
DUTY
Using Ceramic Output Capacitors
When applications use ceramic output capacitors, the
ESR is normally too small to meet the previously stated
ESR criteria. In these applications it is necessary to add
a small signal injection network as shown in Figure 9. In
this network RL and CL filter the LX switching waveform to
generate an in-phase ripple voltage comparable to the
ripple seen on higher ESR capacitors. CC is a coupling capacitor used to AC couple the generated ripple onto the
FB pin. Capacitor CFF is required for min COUT applications.
This capacitor introduces a lead/lag into the control with
the maximum phase placed at 1/2 fSW for added stability.
VIN
Q1
L
VLX
CFF
RL
Q2
CC
CL
R1
COUT
R2
Figure 9 — Signal Injection Circuit
The values of RL, CL, CC and CFF are dependent on the conditions of the specific application such as VIN, VOUT, fSW and
IOUT. For switching frequencies ranging from 600kHz to
800kHz, calculations plus experimental test results show
that the following combination of RL=2.5kW, CL=10nF,
CC=68pF and CFF=39pF can be used for many output voltages and loads.
© 2010 Semtech Corporation
TON(MIN)
TON(MIN) TOFF(MAX )
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
System DC Accuracy — VOUT Controller
Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static conditions it trips when the feedback pin is 750mV, +1%.
The on-time pulse from the SC172 in the design example
is calculated to give a pseudo-fixed frequency of 800kHz.
Some frequency variation with line and load is expected.
This variation changes the output ripple voltage. Because adaptive on-time converters regulate to the valley
of the output ripple, ½ of the output ripple appears as a
DC regulation error. For example, if the output ripple is
50mV with VIN = 5 volts, then the measured DC output
will be 25mV above the comparator trip point. If the ripple increases to 30mV with VIN = 5.5V, then the measured
DC output will be 15mV above the comparator trip. The
best way to minimize this effect is to minimize the output
ripple.
To compensate for valley regulation, it may be desirable
to use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of
trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that
at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output
capacitance because the voltage excursions due to load
steps are reduced as seen at the load.
18
SC172
Applications Information (continued)
The use of 1% feedback resistors may result in up to an
additional 1% error. If tighter DC accuracy is required, resistors with lower tolerances should be used.
The output inductor value may change with current. This
will change the output ripple and therefore will have a
minor effect on the DC output voltage. The output ESR
also affects the output ripple and thus has a minor effect
on the DC output voltage.
deadtime diode conduction, as long as the transient voltage on PVIN is less than 6.0V. The time duration of the
transient LX pin voltage is measured on the voltage portion which is either over 6.0V for positive voltage spike
or under -1V for negative voltage spike. The LX voltage
is measured from the LX pin to the PGND pin by using a
probing loop which is as short as possible to minimize or
eliminate the switching noise pick up.
Switching Frequency Variation
The switching frequency will vary depending on line and
load conditions. The line variations are a result of fixed
propagation delays in the on-time one-shot, as well as
unavoidable delays in the power FET switching. As VIN
increases, these factors make the actual DH on-time
slightly longer than the ideal on-time. The net effect is
that frequency tends to fall slightly with increasing input
voltage.
The switching frequency also varies with load current
as a result of the power losses in the MOSFETs and the
inductor. For a conventional PWM constant-frequency
converter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. A adaptive on-time converter
must also compensate for the same losses by increasing
the effective duty cycle (more time is spent drawing energy from VIN as losses increase). The on-time is essentially constant for a given VOUT and VIN combination, to offset
the losses the off-time will tend to reduce slightly as load
increases. The net effect is that switching frequency increases slightly with increasing load.
Switching Node Voltage Spike
Due to parasitic board inductance, the transient LX pin
voltage at the point of measurement may appear larger
than that which exists on silicon. With an input multilayer ceramic capacitor of 10uF placed less than 3mm away
from the PVIN pin, the device is designed and guaranteed
to tolerate the short transient voltages, of maximum
20ns duration, that will appear on the LX pin due to the
© 2010 Semtech Corporation
19
SC172
Layout Guideline
VIN+
R1
VINC5
VO+
11
22
33
L1
C4
C3
44
C2
VO-
55
U1
BST
VDD
VIN
AGND
LX
PGND
PGOOD
R3
C7
C10
SC172
C1
R6
TON
EN/PSV
PAD
C11
FB
10
10
C6
99
8
77
R2
EN/PSV
66
R7
R4
C8
C9
Schematic for layout illustration
Since the SC172 has integrated switches, special consideration should be given to board layout. Let us use the
schematic shown above as an example. The board level
layout is illustrated in the following four layers.
As shown on the top layer layout, U1 is the switching
regulator SC172. C1 and C11 serve as the decoupling capacitor for the buck converter power train. C11, with a
value between 1nF and 10nF, is the high frequency filtering capacitor. It is recommended to put C1 and C11 as
close as possible to the SC172 to get the best decoupling
performance, with C11 closest. C1, with a value of 10uF,
should be placed no more than 3mm away from the VIN
pin. L1 is the output filtering inductor. C2, C3 and C4 are
the output filtering capacitors. C5 is the boostrap capacitor. Pin 10 (VDD) is the input bias power for the internal
circuits. It is recommended to get the power from VIN
through an RC filtering network consisted of R1, C6 and
C10. The value of R1 can be between 3.01W and 10W and
the capacitance of C10 should be above 1mF. C6, with a
value of 1nF, is the high frequency filtering capacitor. The
© 2010 Semtech Corporation
locations of C6 and C10 should be as close as possible to
pins 9 and 10, with C6 closest, to get the best possible
filtering result. R2 is the on-time programming resistor.
R2 should be located as close as possible to pin 8 and it
should return to analog ground. The EN/PSV pin is a tristate pin. Pull EN/PSV high to enable the part with power
save mode enabled. Connect EN/PSV to AGND to disable
the switching regulator. Leave EN/PSV floating to enable
the IC in forced continuous conduction mode.
Since there are two integrated MOSFETs inside the SC172
that will dissipate a lot of power, to help spread the heat
out of the IC more efficiently, there is a thermal pad underneath the SC172 serving as a heat sink. To enlarge the
heat sinking area, a large copper plane under the thermal
pad as shown on the top layer is recommended.
On inner layer 2, a large analog ground plane (AGND) on
the right hand side is connected to the thermal pad underneath the SC172 using vias. Thus the heat generated
inside the SC172 can be spread through the vias to the
20
SC172
inner layers to expand the heat sinking area.
On the bottom layer, the resistor network composed of
R3 and R4 determines the output voltage. C7 is the feed
forward capacitor which helps to stabilize the circuit. R6
in series with C9 is connected to the LX pin (through the
via) to the power ground. C8 is the coupling capacitor
which injects the ramp signal generated on C9 to the FB
pin of the SC172. R7 is the pull up resistor for the PGOOD
pin.
© 2010 Semtech Corporation
21
SC172
VIN+
Top Layer
C5
U1
C6
C11
L1
C10
C1
PGND
C2
R1
AGND
R2
EN/PSV
AGND
C3
C4
VO+
VO
VIN
VIN+
Inner Layer 1
LX
PGND
1
10
2
9
3
8
4
7
5
6
AGND
VO+
© 2010 Semtech Corporation
VO
VIN
22
SC172
VIN+
Inner Layer 2
LX
PGND
1
10
2
9
3
8
4
7
5
6
AGND
VO+
VO
VIN
Bottom Layer
LX
R7
PGND
R6
1
10
2
9
3
8
4
7
5
6
AGND
C9
C8
C7
R4
R3
VO+
© 2010 Semtech Corporation
VO
VIN
23
SC172
Typical Application Circuits
VIN+
R1
5.11Ohm
VIN-
0.1uF/6.3V
1uF/6.3V
C4
VOUT+
L1
2.0uH
VOUT-
0.1uF/6.3V
C501
C101
C1
10uF/6.3V
38p
C10
C6
22uF/6.3v
R6
9.09k
BST
SC172
VDD
VIN
AGND
LX
TON
PGND
R5
2.49k
R4
100k
10uF/6.3V
C5
R3
24.9k
Enable
EN/PSV
PGOOD
FB
FB
C18
68pF
FB
C19
10n
R2
15k
Application Circuit: Buck Converter with 1.2V out and 0 to 2A load current (Vin= 5V)
VIN+
VIN-
R1
5.11Ohm
C101
C1
10uF/6.3V
0.1uF/6.3V
1uF/6.3V
C4
VOUT+
L1
2.0uH
C6
C2
VOUT-
22uF/6.3v
0.1uF/6.3V
C501
22uF/6.3v
38p
C10
R6
51.1k
SC172
BST
VIN
AGND
LX
TON
PGND
R5
10.5k
R4
100k
VDD
PGOOD
10uF/6.3V
C5
EN/PSV
FB
R3
90.9k
Enable
FB
C18
68pF
FB
R2
15k
C19
10n
Application Circuit: Buck Converter with 3.3V out and 0 to 2A load current (Vin=5V)
© 2010 Semtech Corporation
24
SC172
Outline Drawing - MLPD-10 3x3
D
A
DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN NOM MAX MIN NOM MAX
B
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
E
PIN 1
INDICATOR
(LASER MARK)
A
aaa C
D1
0.80
1.00
0.00
0.05
(0.20)
0.20 0.25 0.30
2.90 3.00 3.10
2.20 2.25 2.30
2.90 3.00 3.10
1.45 1.50 1.55
0.50 BSC
0.45 0.50 0.55
10
0.08
0.10
SEATING
PLANE
C
A1
1
.031
.039
.000
.002
(.008)
.008 .010 .012
.114 .118 .122
.087 .089 .091
.114 .118 .122
.057 .059 .061
.020 BSC
.018 .020 .022
10
.003
.004
A2
2
LxN
E/2
E1
N
e
D/2
bxN
bbb
C A B
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS TERMINALS.
© 2010 Semtech Corporation
25
SC172
Land Pattern - MLPD-10 3x3
K
DIMENSIONS
INCHES
MILLIMETERS
DIM
K
(C) H
G
G
(C) H
Y
Y
X
X
DIM
P
P
Z
Z
C
G
H
K
P
X
Y
Z
(.114)
(2.90)
C
DIMENSIONS
G INCHES .083MILLIMETERS 2.10
1.40
H (.112) .055
(2.85)
2.20
K .079 .087
2.00
1.50
0.50
P .059 .020
2.25
0.30
X .089 .012
.020
0.50
.031
0.80
Y
0.30
.012
3.70
Z .033 .146
0.85
.146
3.70
NOTES:
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT
YOUR MANUFACTURING GROUP TO ENSURE YOUR
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S
GUIDELINES
ARE MET.
COMPANY'S MANUFACTURING
MANUFACTURING GUIDELINES
ARE MET.
INTHE
THELAND
LAND
PATTERN
OF EXPOSED
THE EXPOSED
PAD
3. 3.THERMAL
THERMAL VIAS
VIAS IN
PATTERN
OF THE
PAD
SHALLBE
BE CONNECTED
CONNECTED TOTO
A SYSTEM
GROUND
PLANE.
SHALL
A SYSTEM
GROUND
PLANE.
FAILURE TO
TO DO
COMPROMISE
THE THERMAL
AND/ORAND/OR
FAILURE
DOSO
SOMAY
MAY
COMPROMISE
THE THERMAL
FUNCTIONAL PERFORMANCE OF THE DEVICE.
FUNCTIONAL PERFORMANCE OF THE DEVICE.
© 2010 Semtech Corporation
26
SC172
© Semtech 2010
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SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT
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Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise.
Contact Information
Semtech Corporation
Power Mangement Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
© 2010 Semtech Corporation
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