U4050B Speech Circuit with Line-Powered Loudspeaker Amplifier Description The electronic speech circuit U4050B is a linear integrated circuit for use in telephone sets. It replaces the hybrid transformer, sidetone equivalent and ear protection rectifiers. The circuit is line powered and contains all components necessary for amplification of signals and adaptation to the line. An integrated loudspeaker amplifier allows loudhearing operation. Features D Integrated amplifier for loudhearing operation D Anticlipping for loudspeaker amplifier D Supply voltages for all functional blocks of a D D D D subscriber set D D D D D D D DTMF and MUTE inputs Anticlipping in transmit direction Squelch Integrated transistor for short circuiting the line voltage Adjustable DC characteristics D Power down D Operation possible at line currents above 10 mA Adjustable sending and receiving amplification Automatic line loss compensation Symmetrical output of earpiece amplifier Built-in ear protection Benefits Symmetrical input of microphone amplifier D Independent adjustment of transmit gain, receive gain and sidetone suppression Adjustable sidetone suppression independent of sending and receiving amplification D Low number of external components Block Diagram GS MICO TIN ST GR 15 4 2 7 9 RECO1 RECO2 3 1 – DTMF + 8 MIC1 MIC2 + – – SAI + 10 11 LIMSA LEVSQ CSQ 12 13 SAO 17 CLISA NSA 16 MUTE 25 CK 23 VL 19 RDC 24 VC PD U4050B 22 28 18 14 GND IREF SWAMP VM AGA 6 Power supply MUTE CLIM 21 27 REC. ATT. LIMITER 5 GSA AGA TXA SQUELCH 26 SA 20 VD Figure 1. Block diagram Ordering Information Extended Type Number U4050B-AFL U4050B-AFLG3 Rev. A2, 05-Mar-98 Package SO28 SO28 Remarks Taped and reeled 1 (18) 2 (18) CSQ 1m RSQ 100k 20k RDTMF 11 + CSQ 13 LEVSQ 12 MIC2 MIC1 10 DTMF 8 CDTMF 100n GS 9 – CLIM 470n CLIM 5 LIMITER SQUELCH 7 TIN CTIN 100n PD TXA MUTE 16 MUTE MUTE + MICO 12k 300 – + ST PD 25 NSA 15 27k RNW1 RNW2 1k CNW2 22n 4 + 2 + – RR2 390 CGR 2.2 m RECO1 15k RR1 VM 22 RREF 47k IREF 39 RSWAMP SWAMP 28 U4050B Power supply AGA GR GND RNW3 3.3k SAI 18 CM 22 m + VM 14 + CD 1000 m VD 20 RECO2 LIMSA REC. ATT. 3 1 24 19 23 6 27 17 21 26 VC RDC 10 VL RDC 150n CK CK AGA + CLISA 4.7m CSAO 47m + CLISA SAO GSA direkt an Pin 22 SA RGSA 100k RC >60k CC 10m + RAGA 7.5k CIMP 10m RIMP 1k + CL 68n 13V LINE RL 50 With a squelch function, acoustical feedback during loudhearing can be reduced significantly. The generated 93 7815 e DTMF VM RS1 RS2 CNW1 100n Sidetone network U4050B Block Diagram / Application Circuit supply voltage is suitable for a wide range of peripheral circuits. Figure 2. Typical application diagram Rev. A2, 05-Mar-98 U4050B Pin Description Pin 11 Symbol MIC2 12 LEVSQ 13 14 CSQ VM 22 GND 15 16 TIN MUTE 8 21 SAO 17 CLISA 9 20 VD 18 SWAMP 19 RDC 20 VD 21 22 SAO GND 23 24 VL VC 25 PD 26 GSA 27 AGA 28 IREF RECO2 1 28 IREF GR 2 27 AGA RECO1 3 26 GSA ST 4 25 PD CLIM 5 24 VC CK 6 23 VL MICO 7 DTMF GS RDC MIC1 10 19 MIC2 11 18 SWAMP LEVSQ 12 17 CLISA CSQ 13 16 MUTE VM 14 15 TIN 14052 Figure 3. Pinning S028 Pin 1 3 2 Symbol RECO2, RECO1 GR 4 5 ST CLIM 6 7 8 CK MICO DTMF 9 GS 10 MIC1 Rev. A2, 05-Mar-98 Function Symmetrical outputs of receiving amplifier A resistor connected from this pin to VM (AC coupled) sets the receiving amplification at the circuit Input of sidetone amplifier Time constant of anticlipping in transmit patch Input of receiving path Output of microphone preamplifier Input for DTMF signals (ac coupled). In Mute condition a small portion of the signal at this pin is monitored to the receiver output. A resistor from this pin to VM sets the amplification of microphone and DTMF signals. Inverting input of microphone amplifier Function Non-inverting input of microphone amplifier Input for setting the switching level of the squelch circuit Time constant of the squelch function Reference node for microphone, earphone and loudspeaker amplifier. Supply for electret microphone set to VD/2. Input of intermediate transmit stage Active high input to switch the circuit into DTMF condition. Time constant of anticlipping of speaker amplifier. A resistor connected from this pin to ground converts the excess line current into heat in order to prevent the IC from thermal destruction at high line currents A small resistor connected from this pin to VL sets the slope of the characteristic and also affects the line length equalization characteristics and the line current at which the loudspeaker amplifier is switched on. Unregulated supply voltage for peripheral circuits (dialers, microprocessors, etc.). Output current capability and output voltage increase with line current. Output of loudspeaker amplifier. Reference point for DC and AC output signals Line voltage The internal equivalent inductance of the circuit is proportional to the value of the capacitor at this pin. A resistor connected to ground may be used to reduce the line voltage. Active high input for reducing the current consumption of the circuit. Simultaneously VL is shorted by an internal switch. Current input for setting the gain of the speaker amplifier Automatic gain adjustment with line current. A resistor connected from this pin to VL sets the starting point. Maximum gain change is 6 dB. Internal reference current generation 3 (18) U4050B Absolute Maximum Ratings Parameters Line current Line voltage Junction temperature Ambient temperature Storage temperature Total power dissipation (Tamb = 60°C, SO28) Symbol IL VL Tj Tamb Tstg Ptot Value 140 15 150 –25 to +75 –55 to +150 750 Unit mA V °C °C °C mW Symbol RthJA Value 120 Unit K/W Thermal Resistance Parameters Junction ambient SO28 Electrical Characteristics Test conditions unless otherwise specified: f = 1 kHz, 0 dBm = 775 Vrms, IM = 0.3 mA, ID = 2 mA, RC = 130 kΩ, Tamb = 25°C, RGSA = 560 kΩ, ZH = ZM = 68 nF, Pin AGA open Parameters DC characteristics oltage drop DC voltage over circuit Transmission amplifier Adjustment range of transmit gain Transmitting amplification Frequency response Gain change with current Gain deviation CMRR of microphone amplifier Input resistance of MIC amplifier Distortion at line Maximum output voltage Noise at line psophometrically weighted Anticlipping attack time Release time 4 (18) Test Conditions / Pins Symbol see figure 4 IL = 2 mA VL IL = 15 mA VL IL = 19 mA VL IL = 30 mA VL IL = 100 mA VL see figures 5 and 11 IL = 15 mA IL = 15 mA w IL 15 A, CL = 4.7 nF f = 300 to 3400 Hz Pin AGA open IL = 15 to 100 mA Tamb = – 10 to + 60°C IL = 15 mA IL > 15 mA VL = 775 mV2rms IL > 19 mA d < 5% Vmic = 10 m IL > 15 mA GS = 48 dB Vmic = 20 mV C = 470 nF Each 3 dB overdrive Min. 4.8 Typ. 1.9 5.2 5.4 6.0 9.5 Max. 5.6 Unit V V V V V GS 40 48 56 dB GS 47.75 48.25 " 0.5 48.75 dB dB DGS DGS DGS CMRR 60 80 Ri 45 60 ds V1max no 1.8 3 – 80 0.5 9 " 0.5 " 0.5 dB dB dB 80 kΩ 2 % 4.2 –72 dBm dBmp ms ms Rev. A2, 05-Mar-98 U4050B Parameters Gain at low operating current Distortion at low operating current Line loss compensation Mute suppression Receiving amplifier Adjustment range of receiving gain Receiving amplification Amplification of DTMF signal from DTMF IN to RECO 1/2 Frequency response Gain change with current Gain deviation Ear protection differential Output resistance Line loss compensation Output voltage Push pull Single ended Receiving noise psophometrically weighted Gain at low operating current Distortion at low operating current Rev. A2, 05-Mar-98 Test Conditions / Pins Symbol IL = 10 mA, ID = 1 mA RC = 68 kΩ GS Vmic = 1 mV IM = 0 mA IL = 10 mA, IM = 0 mA ID = 1 mA, RC = 68 kΩ ds Vmic = 10 mV IL = 100 mA DGSI RAGA = 7.5 kΩ IL 15 mA GSM Vmute = 1.5 V see figures 6 and 8 IL 15 mA GR differential IL = 15 mA GR differential IF 15 mA GRM Min. 47 –5 w 60 w –8 w Mute active IL > 15 mA, CL = 4.7 nF f = 300 to 3400 Hz IL = 15 to 100 mA Tamb = –10 to + 60°C IL = 15 mA IL 15 mA Vgen = 11 Vrms Each output against GND IL = 100 mA RAGA = 7.5 kΩ IL = 15 mA, d 2% ZH = 68 nF ZH = 450 Ω ZH = 150 Ω ZH = 68 nF GR = 0 dB IL > 15 mA IL = 10 mA ID = 1 mA IM = 0 mA Vgen = 560 mV RC = 68 kΩ IL = 10 mA, ID = 1 mA Vgen = 560 mV RC = 68 kΩ w Typ. –6 Max. Unit 50 dB 6 % –7 dB dB +8 dB –1 – 0.5 0 dB – 15 – 12 –9 dB DGR DGR " 0.5 " 0.5 " 0.5 Vep Ro 2.2 10 Vrms Ω – 7.0 dB DGRF DGRI v – 5.0 – 6.0 0.775 0.6 0.3 ni GR dr dB dB dB Vrms – 83 – 1.5 – 78.5 dBmp + 0.5 dB 5 % 5 (18) U4050B Parameters Speaker amplifier Minimum line current for operation Gain from VL to SAO Output power Output noise Gain devitation Gain change with current Resistor for turning off speaker amplifier Maximum off-state Output voltage Gain change with frequency Attack time Release time Distortion Test Conditions / Pins see figure 7 No ac signal w IL 15 mA Vgen = 10 mV Load resistance RL = 50 Ω d<5% Vgen = 300 mVrms IL > 15 mA IL = 20 mA IL > 15 mA (Input GSA open) IL = 15 mA Tamb = –10 to + 60°C IL = 15 to 100 mA RAGA = 7.5 kΩ IL = 15 to 100 mA IL = 15 mA VL = 0 dBm Pin GSA open IL = 15 mA f = 300 to 3400 Hz 20 dB overdrive Symbol Min. ILmin 10.5 GSA 27.5 PSA PSA 5 6 (18) 29 Max. Unit 15 mA 30.5 dB mW 20 nsa 200 "1 "1.5 DGSA DGSA µV dB dB 2 MW VSAO – 50 dBm DGSA "1 dB 5 ms ms % RGSA 0.8 tr tf IL = 15 mA dSAO Vgen = 300 mV DTMF - amplifier see figure 8 Test conditions: ID = 2 mA, IM = 0.3 mA, RAGA = 7.5 kΩ, mute active Adjustment range of DTMF IL = 15 mA GD gain Load = 600 Ω DTMF amplification IL = 15 mA GD Gain deviation IL = 15 mA GD Tamb = – 10 to 60°C Input resistance Ri Distortion of IL 15 mA d DTMF signal VI = 0 dBm Gain deviation IL = 15 to 100 mA DGD with current RAGA = 7.5 kΩ w Typ. 1.3 1 300 18 26 34 dB 24.5 26 27 0.5 dB dB 20 25 30 2 kΩ % " 0.5 dB " Rev. A2, 05-Mar-98 U4050B Parameters Test Conditions / Pins Supply voltage see figure 4 Test conditions: VMIC = 10 mV; Tamb = –10 to 60°C Output voltage IL = 15 mA ID = 2 mA RC = 68 kΩ IL = 15 mA ID = 2 mA RC = 130 kΩ Supply voltage for an electret microphone Squelch Attenuation of transmit gain Attenuation of speaker amplifier Switching level of squelch Squelch disable MUTE input MUTE input current MUTE input voltage PD input PD input current Input voltage Current consumption Voltage drop at VL Rev. A2, 05-Mar-98 IL = 100 mA ID = 0 mA Tamb = –10 to + 60°C IM = 0.3 mA IL 15 mA RC = 130 kΩ see figure 9 IL 15 mA w Symbol Min. Typ. VD 2.9 V VD 3.1 V VD Max. Unit 6.1 V 3.3 V VM 1.45 DGS 8 10 12 dB DGSA 7.5 10 12.5 dB L Vmico 6.5 10 mV L RSQ 0.5 1 2 MΩ 20 30 µA 0,3 V 0,3 V 20 50 µA – 40 0.3 – 100 V V µA w I w 15 mA R = 18 to 560 kΩ I w 15 mA RSQ = 100 kΩ I w 15 mA L GSA see figure 10 MUTE active IL > 15 mA VMUTE = VD Mute inactive IL > 15 mA Mute active IL > 15 mA see figure 10 PD active IL > 15 mA VPD = VD PD = active PD = inactive VD = VPD = 4.5 V PD = active IL= 15 mA IL = 15 mA PD = active IL=100 mA PD = active IMUTE VMUTE VMUTE 1.5 IPD VPD VPD IDPD 2 VL 1.5 V VL 1.7 V 7 (18) 8 (18) 93 7821 e S9 Vmic 8 CSQ 1m + CSQ 13 RSQ 100k LEVSQ 12 MIC2 11 MIC1 10 DTMF VM GS 9 – CLIM 470n CLIM 5 LIMITER SQUELCH VMUTE 0.3V 16 MUTE MUTE + MICO RS1 12k RS2 300 7 0.3V VPD TXA – + ST 25 NSA 15 39k PD TIN RNW2 2.2k RNW1 CTIN 150n CNW1 220n CNW2 1n 4 GND 2 + – RR2 390 22 RREF 47k IREF SWAMP 39 RSWAMP 28 U4050B 18 3 S14 RECO1 15k RR1 VM Power supply AGA GR RNW4 3.3k + CGR 22m IM 300 m A VM SAI + 20 1 22 m VM CM VD LIMSA RECO2 68n 14 200 ZH ZH VD + 24 VC CSAO 220 m + ID 2mA RDC 10 CK 150n RDC VL 23 19 CK AGA CLISA SAO GSA 6 27 17 21 26 CD 470 m LHV + RC 130k CC 10 m RAGA 7.5k + CLISA 4.7U RGSA 560k CIMP 100 m + RIMP 1k RLAUT 50 RDUM1 1.34M CL 68n 13V VL IL ZL 600 C600 100m U4050B Figure 4. Test circuit for supply voltage DC characteristics Rev. A2, 05-Mar-98 S21 Rev. A2, 05-Mar-98 a b RNW 25k RSQ 100k CSQ 1m b’ RNW 25k + 11 MIC2 CSQ 13 LEVSQ 12 10 MIC1 DTMF 8 VM 9 – CLIM 470n CLIM 5 LIMITER SQUELCH VMUTE 0.3 V DC 16 MUTE MUTE + MICO 12k 300 GS RS1 RS2 7 VPD 0.3 V TXA – + ST DC 25 NSA 15 39k PD TIN RNW2 2.2k RNW1 CTIN 150n CNW1 220n 4 GND 2 + – RR2 390 RECO1 15k RR1 VM 22 RREF 47k IREF 3 39 RSWAMP 18 28 SWAMP U4050B Power supply AGA GR RNW4 3.3k + CGR 22 m VM SAI RECO2 ZH 14 VD LIMSA 200 68n IM 300 m A 22 m + CM + Á Á 93 7816 e S10 S19 a’ ZM 68n Vmic CNW2 1n LHV 470 m CD 20 1 SAO GSA VL RDC VC 23 19 24 ID 2 mA CK 6 RDC 10 RC 130k CC 10 m RLAUT 50 RAGA 7.5k + + CLISA 4.7m S18 + CSAO 220 m CK 150n AGA 27 17 CLISA 21 26 RGSA 560k CIMP 100 m + RIMP 1k CL 68n S17 RDUM1 1.34M 13V Vl, ds, no, Vlm ZL 600 C600 100 m IL U4050B Figure 5. Test circuit for transmit amplifier 9 (18) 10 (18) CSQ 1m RSQ 100k 93 7817 e S10 68n ZM + 11 10 CSQ 13 LEVSQ 12 MIC2 MIC1 DTMF 8 VM 9 – CLIM 470n CLIM 5 LIMITER SQUELCH VMUTE 0.3 V 16 MUTE MUTE + MICO 12k 300 GS RS1 RS2 7 VPD 0.3 V TXA PD TIN – + 25 NSA 15 39k ST RNW2 2.2k RNW1 CTIN 150n CNW1 220n CNW2 1n 4 GND 2 + – S13 b a RR2 390 VM 39k RR1 15k RR1 22 RREF 47k 39 RSWAMP c b a 3 IM 300 mA VM SAI RECO2 + + CD 470 m CM 22 m VD LIMSA 14 200 ZH 68n Vh,Vep,dr,ni RECO1 S14 28 18 IREF SWAMP U4050B Power supply AGA GR RNW4 3.3k + CGR 22 m 20 1 24 RDC 10 CK 150n VC RDC VL 23 19 CK AGA ZH 150 + CSAO 220 m CLISA SAO GSA 6 27 17 21 ID 2 mA LHV 26 10 m CH + RC 130k CC 10 m RDUM1 1.34M CIMP 100 m + RIMP 1k RLAUT 50 RAGA 7.5k S18 + CLISA 4.7 m RGSA 560k Vhs CL 68n 13 V Vl IL ZL 600 C600 100 m Vgen U4050B Figure 6. Test circuit for receiving amplifier Rev. A2, 05-Mar-98 Rev. A2, 05-Mar-98 CSQ 1m RSQ 100k 93 7818 e S9 S10 68n ZM + CSQ 13 LEVSQ 12 MIC2 11 MIC1 10 DTMF 8 VM 9 – 470n CLIM CLIM 5 LIMITER SQUELCH VMUTE 0.3 V 16 MUTE MUTE + MICO 12k 300 GS RS1 RS2 7 VPD 0.3 V – + ST 25 NSA 15 39k PD TIN RNW2 2.2k RNW1 CTIN 150n TXA 220n CNW1 CNW2 1n 4 GND 2 + – RR2 390 RECO1 15k RR1 VM 22 RREF 47k IREF SWAMP RSWAMP 39 28 U4050B Power supply AGA GR RNW4 3.3k + CGR 22 m 18 3 S14 IM 300 m A 14 + 22 m 470 m CM CD + VD LIMSA RECO2 ZH 68n 200 VM SAI b a Vh 20 1 LHV S16 VC ID 2 mA 24 RDC 10 VL 23 19 b + RC 130k CC 10 m RDC S18 RLAUT 50 CIMP 100 m + RIMP 1k S17 RDUM1 1.34M Vsao,nsa,dsao RAGA 7.5k RGSA 560k CLISA 4.7 m + CSAO 220 m + CK CK 150n AGA CLISA SAO GSA 6 27 17 21 26 a RGSA 15k CL 68n 13V Vl IL ZL 600 100 m C600 Vgen U4050B Figure 7. Test circuit for speaker amplifier 11 (18) 12 (18) 68n CSQ 1m RSQ 100k 680n + CDTMF 93 7819 e S10 a ZM S11 b RZDTMF 10k Vdtmf CSQ 13 LEVSQ 12 MIC2 11 MIC1 10 DTMF 8 GS 9 – 470n CLIM CLIM 5 LIMITER SQUELCH VMUTE 1.5 V 16 MUTE MUTE + MICO 7 VPD 0.3 V TXA ST – + 25 NSA 15 PD TIN 4 GND 2 + – RECO1 22 RREF 47k IREF SWAMP RSWAMP 47 28 U4050B Power supply AGA GR 15k CTIN 150n 12k 300 RR2 390 RR1 RNW4 3.3k + CGR 22 m RS1 39k RNW1 RNW2 2.2k VM RS2 CNW1 220n CNW2 1n 18 3 S14 IM 300 mA + 14 22 m 470 m CM CD + VD LIMSA RECO2 ZH 68n 200 VM SAI b a Vh 20 1 LHV ID 2 mA VC RDC 19 24 VL RDC 10 150n + CSAO 220 m CK CK AGA CLISA SAO GSA 23 6 27 17 21 26 + RC 130k CC 10 m + CLISA 4.7 m RGSA 560k RAGA 7.5k RLAUT 50 CIMP 100 m RIMP 1k RDUM1 1.34M CL 68n Vl,dd 13 V IL ZL 600 C600 100 m U4050B Figure 8. Test circuit for DTMF amplifier Rev. A2, 05-Mar-98 Rev. A2, 05-Mar-98 Vmic VCSQ 1.5 V CSQ 1m + 11 10 S20 CSQ 13 LEVSQ 12 93 7822 e RSQ 100k MIC2 MIC1 DTMF 8 VM GS 9 470n CLIM CLIM 5 LIMITER SQUELCH VMUTE 0.3 V DC 16 MUTE MUTE + – MICO RS1 12k RS2 300 Vmico 7 VPD 0.3 V TXA – + ST DC 25 NSA 15 39k PD TIN RNW2 2.2k RNW1 CTIN 150n CNW1 220n CNW2 1n 4 GND 2 + – RR2 390 22 RREF 47k IREF SWAMP RSWAMP 39 28 U4050B RECO1 15k RR1 VM Poer supply AGA GR RNW4 3.3k + CGR 22 m 18 3 IM 300 mA VM SAI + 22 m 470 m CM CD + VD LIMSA RECO2 ZH 14 200 68n 20 1 LHV SAO GSA ID 2 mA 24 19 23 VC RDC VL CK 6 RDC 10 + + RIMP 1k 100 m CIMP + Vsao RLAUT 50 RAGA 7.5k RC 130k CC 10 m + CLISA 4.7 m RGSA 560k CSAO 220 m CK 150n AGA 27 17 CLISA 21 26 RDUM1 1.34M 68n CL 13V Vl IL ZL 600 C600 100 m Vgen U4050B Figure 9. Test circuit for squelch 13 (18) 14 (18) Vmic 93 7823 e S10 11 CSQ + 1m CSQ 13 RSQ 100k LEVSQ 12 MIC2 MIC1 10 DTMF 8 VM 9 – CLIM 470n CLIM 5 LIMITER SQUELCH VMUTE 16 MUTE MUTE + MICO 12k 300 GS RS1 RS2 TXA VPD – + ST 25 IPD NSA 15 39k PD TIN IMUTE 7 RNW2 2.2k RNW1 CTIN 150n CNW1 220n CNW2 1n 4 GND 2 + – RR2 390 RECO1 15k RR1 VM 22 RREF 47k IREF 39 RSWAMP SWAMP 28 U4050B Power supply AGA GR RNW4 3.3k + CGR 22 m 18 3 IM 300 mA VM SAI RECO2 CM 22 m + + VD LIMSA 14 200 ZH 68n 20 1 CD 470 m IDPD LHV 24 RDC 10 CK 150n VC VD RDC VL 23 19 CK AGA CLISA CSAO 220 m + SAO GSA 6 27 17 21 26 + RC 130k CC 10 m S18 + CLISA 4.7 m RGSA 560k RAGA 7.5k CIMP + 100 m RIMP 1k RLAUT 50 68n CL S17 RDUM1 1.34M ZL 600 13V IL VL C600 100 m + U4050B Figure 10. Test circuit for MUTE and PD test Rev. A2, 05-Mar-98 Rev. A2, 05-Mar-98 b a S19 ZM 68n a 93 7824 e S10 b Vmic,Vcm 12 13 RSQ 100k LEVSQ CSQ + 11 MIC2 CSQ 1m 10 DTMF 8 MIC1 1m CMIC VM – CLIM 470n CLIM 5 LIMITER SQUELCH 16 MUTE VMUTE 0.3 V MUTE + MICO 7 VPD 0.3 V TXA 15 PD TIN ST 4 25 NSA – + GND 2 + – RECO1 22 RREF 47k IREF SWAMP RSWAMP 39 28 U4050B Power supply AGA GR 15k 12k 300 9 RR1 RR2 390 VM RS1 RNW4 3.3k + CGR 22 m RS2 GS 39K RNW2 2.2k RNW1 CTIN 150n CNW1 220n CNW2 1n 18 3 IM 300 mA VM SAI RECO2 + 22 m 470 m CM CD + VD LIMSA 14 200 ZH 68n 20 1 LHV ID 2 mA 24 19 VL 23 VC RDC RDC 10 CK CK 150n AGA CLISA CSAO 220 m + SAO GSA 6 27 17 21 26 RC 130k 100 m CIMP + CL 68n S17 RDUM1 1.34M RIMP 1k RLAUT 50 RAGA 7.5k CC + 10 m S18 + CLISA 4.7 m RGSA 560k 13V Vl,Vlcm IL ZL 600 C600 100 m U4050B Figure 11. Test circuit for transmit amplifier (CMRR) 15 (18) U4050B Typical Curves 94 7832 e S max. curve RC = 130 k : RC = 68 k (min. curve) Cond.: ID = 0 mA Figure 12. DC characteristics 94 7833 e Figure 13. AGA characteristics 16 (18) Rev. A2, 05-Mar-98 U4050B Package Information Package SO28 Dimensions in mm 9.15 8.65 18.05 17.80 7.5 7.3 2.35 28 0.25 0.25 0.10 0.4 1.27 10.50 10.20 16.51 15 technical drawings according to DIN specifications 13033 1 Rev. A2, 05-Mar-98 14 17 (18) U4050B Ozone Depleting Substances Policy Statement It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423 18 (18) Rev. A2, 05-Mar-98