ATMEL ATA5749

Features
•
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•
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Fully Integrated Fractional-N PLL
ASK and Closed Loop FSK Modulation
Output Power Up to +12.5dBm from 300MHz to 450MHz
Current Consumption is Scaled by Output Power Programming
Fast Crystal Oscillator Start-up Time of Typically 200µs
Low Current Consumption of Typically 7.3mA at 5.5dBm
Only One 13.0000MHz Crystal for 314.1MHz to 329.5MHz and 424.5MHz to 439.9MHz
Operation
Single Ended RF Power Amplifier Output
Many Software Programmable Options Using SPI:
– Output Power from –0.5dBm to +12.5dBm
– RF Frequency from 300MHz to 450MHz with Different Crystals
– FSK Deviation with 396Hz Resolution
– CLK Output Frequency 3.25MHz or 1.625MHz
Data Rate Up to 40kbit/s (Manchester)
4KV HBM ESD Protection Including XTO
Operating Temperature Range of –40°C to +125°C
Supply Voltage Range of 1.9V to 3.6V
TSSOP10 Package
Fractional-N
PLL Transmitter
IC
Atmel ATA5749
Benefits
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Robust Crystal Oscillator with Fast Start Up and High Reliability
Lower Inventory Costs and Reduced Part Number Proliferation
Longer Battery Lifetime
Supports Multi-channel Operation
Wide Tolerance Crystal Possible with PLL Software Compensation
1. Description
The Atmel® ATA5749 is a fractional-N-PLL transmitter IC for 300MHz to 450MHz
operation and is especially targeted for Tire Pressure Sensor Gauges, Remote
Keyless Entry, and Passive Entry and other automotive applications. It operates at
data rates up to 40kbit/s Manchester for ASK and FSK with a typical 5.5dBm output
power at 7.3mA. Transmitter parameters such as output power, output frequency,
FSK deviation, and current consumption can be programmed using the SPI interface.
This fully integrated PLL transmitter IC simplifies RF board design and results in very
low material costs.
9128E–RKE–09/10
Figure 1-1.
Block Diagram
CLK
1
Atmel ATA5749
CLK_DRV
1
XTO_RDY
Power
up/down
10
EN
XTO Signal
4 or 8
Fractional-N-PLL
CLK_ON
DIV_CNTRL
FSK_mod
SDIN_TXDIN
2
FSEP[0:7]
SCK
9
GND
8
VS
7
XTO1
6
XTO2
FREQ[0:14]
3
Digital
Control
433_N315
and
Registers ASK_mod
Frac.
Div.
PFD
PWR[0:3]
CP
ANT2
4
LP
XTO
(FOX)
ANT1
2
5
PA
VCO
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ATA5749
2. Pin Configuration
Figure 2-1.
TSSOP10 Package Pinout
CLK
1
SDIN_TXDIN
2
10
EN
9
GND
8
VS
Atmel
Table 2-1.
ATA5749
SCK
3
ANT2
4
7
XTO1
ANT1
5
6
XTO2
Pin Description
Pin
Symbol
Function
1
CLK
2
SDIN_TXDIN
3
SCK
Serial bus clock input
4
ANT2
Antenna interface
5
ANT1
Antenna interface
6
XTO2
Crystal/CLOAD2 connection
7
XTO1
8
VS
Supply input
9
GND
Supply GND
10
EN
Enable input
CLK output
Serial bus data input and TX data input
Crystal/CLOAD1 connection
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3. Functional Description
3.1
Fractional-N PLL
The Atmel® ATA5749 block diagram is shown in Figure 1-1 on page 2. The operation of the PLL
is determined by the contents of a 32-bit configuration register. The 15-bit value FREQ is used
with the 1-bit 434_N315 flag to determine the RF carrier frequency. This results in a user-selectable frequency step size of 793Hz (with 13.000MHz crystal). With this level of resolution, it is
possible to compensate for crystal tolerance by adjusting the value of FREQ accordingly. This
enables the use of lower cost crystals without compromising final accuracy. In addition, software
programming of RF carrier frequency allows this device to be used in some multi-channel
applications.
Modulation type is selected with the 1-bit ASK_NFSK flag. FSK modulation is achieved by modifying the divider block in the feedback loop. The benefit to this approach is that performancereducing RF spurs (common in applications that create FSK by “pulling” the load capacitance in
the crystal oscillator circuit) are completely eliminated. The 8-bit value FSEP establishes the
FSK frequency deviation. It is possible to obtain FSK frequency deviations from ±396Hz to
±101kHz in steps of ±396Hz.
The PLL lock time is 1280/(external crystal frequency) and amounts to 98.46µs when using a
13.0000MHz crystal. When added to the crystal oscillator start-up time, a very fast time-to-transmit is possible (typically 300µs). This feature extends battery life in applications like Tire
Pressure Monitoring Systems, where the message length is often shorter than 10ms and the
time “wasted” during start-up and settling time becomes more significant.
3.2
Selecting the RF Carrier Frequency
The fractional divider can be programmed to generate an RF output frequency fRF according to
the formulas shown in Table 3-1. Note that in the case of fRF ASK, the FSEP/2 value is rounded
down to the next integer value if FSEP is an odd number.
Table 3-1.
RF Output Parameter Formulas
RF Output Parameter
S434_N315 = LOW
S434_N315 = HIGH
fRF_FSK_LOW
(24 + (FREQ + 0.5)/16384) × fXTO
(32.5 + (FREQ + 0.5)/16384) × fXTO
fRF_FSK_HIGH
(24 + (FREQ + FSEP + 0.5)/16384)
× fXTO
(32.5 + (FREQ + FSEP + 0.5)/16384)
× fXTO
fDEV__FSK
FSEP/32768 × fXTO
FSEP/32768 × fXTO
fRF ASK
(24 + (FREQ + FSEP/2 + 0.5)/16384)
× fXTO
(32.5 + (FREQ + FSEP/2 + 0.5)/16384)
× fXTO
FSEP can take on the values of 1 to 255. Using a 13.000MHz crystal, the range of frequency
deviation fDEV_FSK is programmable from ±396Hz to ±101.16kHz in steps of ±396Hz. For example, with FSEP = 100 the output frequency is FSK modulated with fDEV_FSK = ±39.6kHz.
FREQ can take values in the range of values 2500 and 22000. Using a 13.0000MHz crystal, the
output frequency f RF can be programmed to 315MHz by setting FREQ[0:14] = 3730,
FSEP[0:7] = 100 and S434_N315 = 0. By setting FREQ[0:14] = 14342, FSEP[0:7] = 100 and
S434_N315 = 1, 433.92MHz can be realized.
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The PA is enabled when the PLL is locked and the configuration register programming is completed. Upon enabling PA at FSK-mode, the RF output power will be switched on. At ASK mode,
the input signal must be additionally set high for RF at output pins. The output power is user programmable from –0.5dBm to +12.5dBm in steps of approximately 1dB. Changing the output
power requirements, you also modify the current consumption. This gives the user the option to
optimize system performance (RF link budget versus battery life). The PA is implemented as a
Class-C amplifier, which uses an open-collector output to deliver a current pulse that is nearly
independent from supply voltage and temperature. The working principle is shown in Figure 3-1.
Figure 3-1.
Class C Power Amplifier Output
VANT1
VS
IANT2
IPulse = (PWR[0:3])
VS
VANT1
L1
Power Meter
ANT1
C2
5
IANT2
50Ω
ZLOPT
ANT2
4
The peak value of this current pulse IPulse is calibrated during Atmel® ATA5749 production to
about ±20%, which corresponds to about 1.5dB variation in output power for a given power setting under typical conditions. The actual value of IPulse can be programmed with the 4-bit value in
PWR. This allows the user to scale both the output power and current consumption to optimal
levels.
ASK modulation is achieved by using the SDIN_TXDIN signal where a HIGH on this pin corresponds to RF carrier “ON” and a LOW corresponds to RF “OFF”. FSK uses the same signal path
but HIGH switch on the upper FSK-frequency.
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3.3
Crystal Oscillator
The crystal oscillator (XTO) is an amplitude-regulated Pierce oscillator. It has fixed function and
is not programmable. The oscillator is enabled when the EN is “set”. After the oscillator’s output
amplitude reaches an acceptable level, the XTO_RDY flag is “set”. The CLK-pin becomes active
if CLK_ON is set. The PLL receives its reference frequency.
Typically, this process takes about 200µs when using a small sized crystal with a motional
capacitance of 4fF. This start-up time strongly depends on the motional capacitance of the
crystal and is lower with higher motional capacitance.
The high negative starting impedance of RXTO12_START > 1500Ω is important to minimize the
failure rate due to the “sleeping crystal” phenomena (more common among very small sized
3.2mm × 2.5mm crystals).
3.4
Clock Driver
The clock driver block shown in Figure 1-1 on page 2 is programmed using the CLK_ONLY,
CLK_ON, and DIV_CNTRL bits in the configuration register. When CLK_ONLY is “clear”, normal
operation is selected and the fractional-N PLL is operating. When CLK_ON is “set”, the CLK
output is enabled. The crystal clock divider ratio can be set to divide by four when DIV_CNTRL is
“set” and divide by eight when DIV_CNTRL is “clear”. With a 13.0000MHz crystal, this yields an
output of 3.25MHz or 1.625MHz, respectively. When CLK_ON is “clear”, no clock is available at
CLK and the transmitter has less current consumption.
The CLK signal can be used to clock a microcontroller. It is CMOS compatible and can drive up
to 20pF of load capacitance at 1.625MHz and up to 10pF at 3.25MHz. When the device is in
power-down mode, the CLK output stays low. Upon power up, CLK output remains low until the
amplitude detector of the crystal oscillator detects sufficient amplitude and XTO_RDY and
CLK_ON are “set”. After this takes place, CLK output becomes active. The CLK output is
synchronized with the XTO_RDY signal so that the first period of the CLK output is always a full
period (no CLK output spike at activation).
To lower overall current consumption, it is possible to power down the entire chip except for the
crystal oscillator block. This can be achieved when the CLK_ONLY is “set”.
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4. Application
4.1
Typical Application
Figure 4-1.
Typical Application Circuit
IO1
Microcontroller
CLK
CLK
1
Atmel ATA5749
CLK_DRV
1
XTO_RDY
Power
up/down
10
EN
XTO Signal
4 or 8
IO2
Fractional-N-PLL
DIV_CNTRL
CLK_ON
FSK_mod
IO3
2
9
FREQ[0:14]
SDIN_TXDIN
SCK
FSEP[0:7]
3
Digital
Control
433_N315
and
Registers ASK_mod
GND
Frac.
Div.
C6
8
PFD
VS
PWR[0:3]
VS
CP
C3
ANT2
4
7
C4
XTO1
Loop
antenna
LP
XTAL
XTO
(FOX)
ANT1
5
PA
6
VCO
XTO2
C5
C2
L1
C1
VS
Figure 4-1 shows the typical application circuit. For C6, the supply-voltage blocking capacitor,
value of 68nF X7R is recommended. C2 and C3 are NPO capacitors used to match the loop
antenna impedance to the power amplifier optimum load impedance. They are based on the
PCB trace antenna and are ≤ 20pF NPO capacitors. C1 (typically 1nF X7R) is needed for the
supply blocking of the PA. In combination with L1 (200nH to 300nH), they prevent the power
amplifier from coupling to the supply voltage and disturbing PLL operation. They should be
placed close to pin 5. L1 also provides a low resistive path to VS to deliver the DC current to
ANT1.
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The PCB loop antenna should not exceed a trace width of 1.5mm otherwise the Q-factor of the
loop antenna is too high. C4 and C5 should be selected so that the XTO runs on the load resonance frequency of the crystal. A crystal with a load capacitance of 9pF is recommended for
proper start-up behavior and low current consumption. When determining values for C4 and C5,
a parasitic capacitance of 3pF should be included. With value of 15pF for C4 and C5, an effective load capacitance of 9pF can be achieved e.g. 9pF = (15pF + 3pF)/2. The supply VS is
typically delivered from a single Li-Cell.
4.1.1
Antenna Impedance Matching
The maximum output power is achieved by using load impedances according to Table 4-1 and
Table 4-2 on page 9 and the output power. The load impedance ZLOPT is defined as the impedance seen from the Atmel® ATA5749 ANT1, ANT2 into the matching network. This is not the
output impedance of the IC but essentially the peak voltage divided by the peak current with
some additional parasitic effects (Cpar). Table 4-1 and Table 4-2 on page 9 do not contain information pertaining to C3 in Figure 4-2, which is an option for better matching at low power steps.
Figure 4-2 is the circuit that was used to obtain the typical output power measurements in Figure 4-3 on page 10 and typical current consumption in Figure 4-4 on page 10. Table 4-1 and
Table 4-2 on page 9 provide recommended values and performance info at various output
power levels. For reference, ZLOPT is defined as the impedance seen from the ATA5749 ANT1,
ANT2 into the matching network.
Figure 4-2.
Output Power Measurement Circuit
ZLOPT
ANT2
4
Power Meter
ANT1
C2
PA
5
50Ω
C3
L1
C1
VS
8
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ATA5749
The used parts at Table 4-1 and Table 4-2 are:
Inductors: high Q COILCRAFT 0805CS; Capacitors: AVX ACCU-P 0402
Table 4-1.
Measured PA Matching at 315MHz (CLK_ON = “LOW”) at Typ. Samples
PWR
Register
Desired
Power (dBm)
L1
(nH)
C1
(pF)
C2
(pF)
RLOPT
(Ω)
ZLOPT
(Ω)
Cpar
(pF)
Actual Power
(dBm)
3
–0.5
110
1.2
1.6
2950
110 + 540j
0.9
–0.37
4
1.0
100
1.5
1.6
1940
150 + 520j
0.9
1.12
5
2.5
100
1.5
1.6
1550
190 + 520j
0.9
2.11
6
3.5
100
1.5
1.6
1250
220 + 480j
0.9
3.23
7
4.5
82
1.8
1.6
1000
240 + 430j
0.9
4.38
8
5.5
82
2.2
1.6
730
280 + 360j
0.9
5.42
9
6.5
68
2.7
1.6
580
290 + 300j
0.9
7.14
10
7.5
68
2.7
1.6
460
290 + 290j
0.9
8.22
11
8.5
68
3.3
1.6
350
280 + 225j
0.9
8.63
12
9.5
56
3.6
1.6
320
250 + 150j
0.9
9.79
13
10.5
47
4.7
1.6
250
215 + 85j
0.9
10.52
14
11.5
47
5.6
1.6
190
180 + 50j
0.9
11.67
15
12.5
47
5.6
1.6
160
160 + 45j
0.9
13
Table 4-2.
Measured PA Matching at 433.92MHz (CLK_ON = “LOW”) at Typ. Samples
PWR
Register
Desired
Power (dBm)
L1
(nH)
C1
(pF)
C2
(pF)
RLOPT
(Ω)
ZLOPT
(Ω)
Cpar
(pF)
Actual Power
(dBm)
3
–0.5
68
0,9
1.5
2800
60 + 400j
0.9
–0.62
4
1.0
56
2.7 + 2.2
1.5
1850
90 + 390j
0.9
1.3
5
2.5
56
1.2
1.5
1450
110 + 380j
0.9
2.73
6
3.5
47
1.8
5.6
1150
130 + 370j
0.9
3.03
7
4.5
47
1.6
5.6
950
150 + 350j
0.9
4.63
8
5.5
47
1.8
5.6
680
180 + 300j
0.9
6.18
9
6.5
43
2.2
1
560
200 + 270j
0.9
6.66
10
7.5
36
2.4
1
450
210 + 230j
0.9
7.91
11
8.5
33
3
1
340
200 + 170j
0.9
8.68
12
9.5
36
2.7
1
310
195 + 150j
0.9
9.8
13
10.5
36
3.6
1
230
175 + 100j
0.9
10.49
14
11.5
27
4.7
1
180
150 + 70j
0.9
11.6
15
12.5
27
4.7
1
150
130 + 50j
0.9
12.5
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Figure 4-3.
Typical Measured Output Power
15
315MHz
VS = 3.6V, PWR[0:15] = 15]
433MHz
13
VS = 3.0V, PWR[0:15] = 15
Pmeas [dBm]
11
9
VS = 1.9V, PWR[0:15] = 15
7
VS = 3.6V, PWR[0:15] = 8
5
VS = 3.0V, PWR[0:15] = 8
3
VS = 1.9V, PWR[0:15] = 8
1
-40
27
85
125
Temperature [°C]
Figure 4-4.
Typical Current Consumption I at Port VS
23
VS = 3.6V, P WR[0:15] = 15
21
315MHz
433MHz
19
VS = 3.0V, P WR[0:15] = 15
VS = 1.9V, P WR[0:15] = 15
Ivs [mA]
17
15
13
11
VS = 3.6V, P WR[0:15] = 8
VS = 3.0V, P WR[0:15] = 8
9
7
VS = 1.9V, P WR[0:15] = 8
5
-40
27
85
125
Temperature [˚C]
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5. Pulling of Frequency due to ASK Modulation (PA Switching)
The switching effect on VCO frequency in ASK Mode is very low if a correct PCB layout and
decoupling is used. Therefore, power ramping is not needed to achieve a clean spectrum (see
Figure 5-1).
Figure 5-1.
Typical RF Spectrum of 40kHz ASK Modulation at Pout = 12.5dBm
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6. Configuration Register
6.1
General Description
The user must program all 32 bits of the configuration register upon power up (EN = HIGH) or
whenever changes to operating parameters are desired. The configuration register bit assignments and descriptions can be found in Table 6-1 and Table 6-2.
Table 6-1.
Organization of the Control Register
MSB
31
CLK_
ONLY
30
29
28
27
26
25
24
23
22
21
S434_ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ
N315
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
20
FREQ
[5]
19
FREQ
[4]
18
17
16
FREQ FREQ FREQ
[3]
[2]
[1]
Frequency Adjust = FREQ[0..14]
FREQ[0] + 2 × FREQ[1] + 4 × FREQ[2] + ... + FREQ[14] × 16384 = 0..32767
LSB
15
FREQ
[0]
14
FSEP
[7]
13
FSEP
[6]
12
FSEP
[5]
11
FSEP
[4]
10
FSEP
[3]
9
FSEP
[2]
8
FSEP
[1]
7
6
5
FSEP DIV_
PWR
[0]
CNTRL
[3]
FSK Shift = FSEP[0..7]
FSEP[0] + ... + FSEP[7] × 128 = 0..255
Table 6-2.
Name
3
PWR
[1]
2
PWR
[0]
1
ASK_
NFSK
0
CLK_
ON
Output Power = PWR[0..3]
PWR[0] + .. + PWR[3] × 8 = 0..15
Control Register Functional Descriptions
Bit No.
Size
CLK_ONLY
31
1
Activates/deactivates CLK_ONLY Mode
Low = Normal Mode
High = Clock Only Mode (Figure 4-1 on page 7)
S434_N315
30
1
VCO band selection
High = 367MHz to 450MHz
Low = 300MHz to 368MHz
FREQ[0:14]
15 ... 29
15
PLL frequency adjust
See Table 6-1 for formula
FSEP[0:7]
7 ... 14
8
FSK deviation adjust
See Table 6-1 for formula
6
1
CLK output divider ratio
Low = fXTO/8
High = fXTO/4
2 ... 5
4
PA output power adjustment
See Table 4-1 and Table 4-2 on page 9
ASK_NFSK
1
1
Modulation type
Low = FSK
High = ASK
CLK_ON
0
1
CLK_DRV port control
HIGH = CLK port is ON
LOW = CLK port is OFF
DIV_CNTRL
PWR[0:3]
12
4
PWR
[2]
Remarks
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6.2
Programming
The configuration register is programmed serially using the SPI bus, starting with the MSB. It
consists of the Enable line (EN), the Data line (SDIN_TXDIN), and the SPI-Bus Clock (SCK).
The SDIN_TXDIN data is loaded on the positive edge of the SCK. The contents of the configuration register become programmed on the negative SCK edge of the last bit (LSB) of the
programming sequence. The timing of this bus is shown in Figure 6-1. Note that the maximum
usable clock speed on the SPI bus is limited to 2MHz.
Figure 6-1.
SPI Bus Timing
EN
TSCK_High
TEN_setup
TSDIN_TXDIN_setup
TSCK_Cycle
TSCK_Low
SCK
TSetup
SDIN_TXDIN
THold
MSB
X
MSB-1
X
At the conclusion of the 32 bit programming sequence, the SDIN_TXDIN line becomes the
modulation input for the RF transmitter. After programming is complete, the SCK signal has no
effect on the device. To disable the transmitter and enter the OFF Mode, EN and SDIN_TXDIN
must be returned to the LOW state. For clarity, several additional timing diagrams are included.
Figure 6-2 shows the situation when the programming terminates faster then the XTO is ready.
Timing Diagram if Register Programming is Faster than ΔTXTO
Figure 6-2.
ΔTXTO
EN (Input)
SDIN_TXDIN
(Input)
32-bit Configuration
SCK (Input)
TX-Data
X
X
X
TPLL
CLK (Output)
PA (Output
Power)
OFF_
Mode
Start_Up_
Mode_1
Start_Up_
Mode_2
TX_
Mode1
FSK;
TX_Mode2
ASK:
TX_Mode1 and
TX_Mode2
OFF_Mode
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Figure 6-3 shows the combination with slow programming and a faster ramp up of XTO. A
diagram of the operating modes is shown in Figure 6-5 on page 16 and a description of which
circuit blocks are active is provided in Table 6-3 on page 15. This also contains the information
needed for the calculation of consumed charge for one operation cycle.
Figure 6-3.
Timing Diagram if Programming is Slower than TXTO
ΔTXTO
EN (Input)
TPLL
SDIN_TXDIN
(Input)
32-bit Configuration
TX-Data
SCK (Input)
X
X
CLK (Output)
PA (Output
Power)
OFF_
Mode
6.3
Start_Up_
Mode_1
Start_Up_
Mode_2
TX_
Mode1
FSK;
TX_Mode2
ASK:
TX_Mode1 and
TX_Mode2
OFF_Mode
Reprogramming without Stopping the Crystal Oscillator
After the configuration register is programmed and RF data transmission is completed, the OFF
mode is normally entered. This stops the crystal oscillator and PLL. If it is desirable to modify the
contents of the configuration register without entering the OFF mode, the Reset_Register_Mode
can be used. To enter the Reset_Register_Mode, the SDIN_TXDIN must be asserted HIGH
while the EN is asserted LOW for at least 10µs Reset_min time. This state is shown in Figure
6-4 on page 15, State Diagram of Operating Modes. In Reset_Register_Mode, the PA and fractional PLL remain OFF but the XTO remains active. This state must stay for minimum 10µs. At
the next step you must rise first EN and SDIN_TXDIN 10µs delayed. While in this mode, the
32 bit configuration register data can be sent on the SPI bus as shown in Figure 6-2 on page 13.
After data transmission, the device can be switched back to OFF_Mode by asserting EN, SCK,
and SDIN_TXDIN to a LOW state. An example of programming from the Reset_Register_Mode
is shown in Figure 6-4 on page 15.
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Figure 6-4.
Timing Diagram when using Reset_Register_Mode
TEN_Reset
TPLL
EN (Input)
TPLL
TSDIN_TXDIN_setup TEN_setup
SDIN_TXDIN
(Input)
32-bit
Configuration
TX_
Data
32-bit
Configuration
TX_
Data
SCK (Input)
CLK (Output)
PA (Output
Power)
Start_Up_ Start_Up_
Mode_1
Mode_2
FSK;
TX_Mode2
Reset_
ConASK:
Register_ figuration_
TX_Mode1 and
Mode
Mode_1
TX_Mode2
TX_Mode1
Table 6-3.
Configuration_
Mode_2
FSK;
TX_Mode2
OFF_
ASK:
Mode
TX_Mode1 and
TX_Mode2
TX_Mode1
Active Circuits as a Function of Operating Mode
Operating Mode
Active Circuit Blocks
OFF_Mode
-none-
Start_Up_Mode_1
Power up/down; XTO; digital control
Start_Up_Mode_2
Power up/down; XTO; digital control; fractional-N-PLL
TX_Mode1
Power up/down; XTO; digital control; fractional-N-PLL; CLK_DRV(1)
TX_Mode2
Power up/down; XTO; digital control; fractional-N-PLL; CLK_DRV(1); PA
Clock_Only_Mode
Power up/down; XTO; digital control; CLK_DRV(1)
Reset_Register_Mode
Power up/down; XTO; digital control; CLK_DRV(1)
Configuration_Mode_1
Power up/down; XTO; digital control; CLK_DRV(1)
Configuration_Mode_2
Power up/down; XTO; digital control; CLK_DRV(1); fractional-N-PLL
Note:
1. Only if activated with CLK_ON = HIGH
15
9128E–RKE–09/10
Figure 6-5.
State Diagram of Operating Modes
OFF_Mode
EN = 'High'
SDIN_TXDIN = 'Low'
EN = 'Low'
SDIN_TXDIN = 'Low'
EN = 'Low'
SDIN_TXDIN = 'Low'
Start-Up_Mode_1
EN = 'Low'
SDIN_TXDIN = 'Low'
CLK_Only = 'Low'
register parity programmed1
CLK_Only = 'Low'
register programmed2
XTO_RDY = 'High'
ASK_NFSK = 'Low' or
(ASK_NFSK = 'High' and
SDIN_TXDIN = 'High')
PLL locked3
TX_Mode_2
EN = 'Low'
SDIN_TXDIN = 'Low'
CLK_Only = 'High'
register programmed2
XTO_RDY = 'High'
Start-Up_Mode_2
TX_Mode_1
Clock_only_Mode
CLK_Only = 'Low'
register programmed2
ASK_NFSK = 'High' and
SDIN_TXDIN = 'Low'
CLK_Only = 'High'
register programmed2
Configuration_Mode_2
CLK_Only = 'Low'
register parity programmed1
EN = 'Low'
SDIN_TXDIN = 'High'
EN = 'Low'
SDIN_TXDIN = 'High'
EN = 'Low'
SDIN_TXDIN = 'High'
Configuration_Mode_1
1 )"register
partly programmed": negative SCK
edge of 32-bit register programming MSB-1
(S433_N315)
EN = 'High'
SDIN_TXDIN = 'Low'
2)
"register programmed'" negative SCK
edge of 32-bit register programming LSB
(CLK_ON)
Reset_Register_Mode
"PLL locked" 1280 XTO cycles (TPLL) after
register programmed and XTO_RDY = 'High'
3)
To transition from one state to another, only the
conditions next to the transition arrows must be
fulfilled. No additional settings are required.
16
ATA5749
9128E–RKE–09/10
ATA5749
7. ESD Protection Circuit
Figure 7-1.
ESD Protection Circuit
VS
ANT1
CLK
SCK
EN
ANT2
XTO2
XTO1
SDIN_TXDIN
GND
8. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Max.
Unit
Supply voltage
VS
–0.3
+4.0
V
Power dissipation
Ptot
100
mW
Tj
150
°C
Junction temperature
Storage temperature
Tstg
–55
+125
°C
Ambient temperature
Tamb1
–40
+125
°C
Ambient temperature in power-down mode for 30 minutes
without damage with VS ≤ 3.2V, VENABLE < 0.25V or
ENABLE is open, VASK < 0.25V, VFSK < 0.25V
Tamb2
175
°C
ESD (Human Body Model ESD S5.1) every pin
excluding pin 5 (ANT1)
HBM
–4
+4
kV
ESD (Human Body Model ESD S5.1) for pin 5 (ANT1)
HBM
–2
+2
kV
ESD (Machine Model JEDEC A115A) every pin
excluding pin 5 (ANT1)
MM
–200
+200
V
ESD (Machine Model JEDEC A115A) for pin 5 (ANT1)
MM
–150
+150
V
ESD – STM 5.3.1-1999 every pin
CDM
750
V
9. Thermal Resistance
Parameters
Thermal resistance, junction ambient
Symbol
Value
Unit
RthJA
170
K/W
17
9128E–RKE–09/10
10. Electrical Characteristics
VS = 1.9V to 3.6V Tamb = –40°C to +125°C, CLK_ON = “High”; DIV_CNTRL = “Low”, CLOAD_CLK = 10pF. fXTO = 13.0000MHz,
fCLK = 1.625MHz unless otherwise specified. If crystal parameters are important values correspond to a crystal with CM = 4.0fF,
C0 = 1.5pF, CLOAD = 9pF and RM ≤ 170Ω. Typical values are given at VS = 3.0V and Tamb = 25°C
No. Parameters
1
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Current Consumption
V(SDIN_TXDIN,SCK,EN) = Low
1.1
Supply current,
OFF_Mode
Tamb ≤ +25°C
Tamb ≤ +85°C
Tamb ≤ +125°C
5, 8
IS_Off_Mode
1
20
265
100
350
7,000
nA
nA
nA
1.2
Supply current,
TX_Mode1
VS ≤ 3.0V
5, 8
IS_TX_Mode1
3.6
4.75
mA
B
1.3
Supply current,
TX_Mode2
VS ≤ 3.0V
PWR[0:3] = 8 (5.5dBm)
5, 8
IS_TX_Mode2
7.3
8.8
mA
B
1.4
Supply current,
CLK_Only_Mode
VS ≤ 3.0V
5, 8
IS_CLK_Only _
480
680
µA
B
A
Mode
1.5
VS ≤ 3.0V
CLK_ON = “Low”
Supply current
+ ΔICLKoff1
I =I
reduction, Clock Driver S S_any_Mode
(can be applied to all modes
off
except Off_Mode, add Typ. to
Typ. and Max. to Max. values)
5, 8
ΔICLKoff1
–250
–300
µA
B
1.6
Supply current
increase, Clock Driver
higher frequency
VS ≤ 3.0V
DIV_CNTRL = “High”
fCLK = 3.24MHz
IS= IS_any__Mode + ΔICLKhigh
(can be applied to all modes
except Off_Mode add Typ. to
Typ. and Max. to Max. values)
5, 8
ΔICLKhigh
150
190
µA
B
1.7
Reset_Register_Mode /
VS ≤ 3.0V
Configuration_Mode_1
5, 8
Register_Mode /
680
µA
B
4.75
mA
B
350
µA
B
+3.0
dBm
B
IS_Reset_
IS_Configuration
_ Mode_1
1.8
Configuration_Mode_2 /
VS ≤ 3.0V
Start_Up_Mode_2
5, 8
IS_Configuration
_Mode_2 /
IS_Start_Up
_Mode_2
1.9
2
2.1
Start_Up_Mode_1
VS ≤ 3.0V
5, 8
VS = 3.0V, Tamb = 25°C
PWR[0:3] = 4
ZLOAD = ZLOPT according to
Table 4-1 on page 9 and
Table 4-2 on page 9
(5)
IS_Start_Up
_Mode_1
Power Amplifier (PA)
Output power 1,
TX_Mode2
POUT_1
–1.0
+1.0
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
18
(Pin Number) in brackets mean they are measured matched to 50Ω according to Figure 4-2 on page 8 with component values
and optimum load impedances according to Table 4-1 and Table 4-2 on page 9
ATA5749
9128E–RKE–09/10
ATA5749
10. Electrical Characteristics (Continued)
VS = 1.9V to 3.6V Tamb = –40°C to +125°C, CLK_ON = “High”; DIV_CNTRL = “Low”, CLOAD_CLK = 10pF. fXTO = 13.0000MHz,
fCLK = 1.625MHz unless otherwise specified. If crystal parameters are important values correspond to a crystal with CM = 4.0fF,
C0 = 1.5pF, CLOAD = 9pF and RM ≤ 170Ω. Typical values are given at VS = 3.0V and Tamb = 25°C
No. Parameters
2.2
Supply current 1,
TX_Mode2
2.3
Output power 2,
TX_Mode2
2.4
Supply current 2,
TX_Mode2
2.5
Output power 3,
TX_Mode2
2.6
Supply current 3,
TX_Mode2
2.7
3
Test Conditions
Pin
Symbol
VS = 3.0V
PWR[0:3] = 4
5, 8
IS_P1
VS = 3.6V
PWR[0:3] = 4
5, 8
IS_P1
VS = 3.0V, Tamb = 25°C
PWR[0:3] = 8
ZLOAD = ZLOPT according to
Table 4-1 on page 9 and
Table 4-2 on page 9
(5)
POUT_2
VS = 3.0V, PWR[0:3] = 8
[typ. 5.5dBm; see 2.3]
5, 8
IS_P2
VS = 3.6V, PWR[0:3] = 8
[typ. 5.5dBm; see 2.3]
5, 8
IS_P2
VS = 3.0V, Tamb = 25°C
PWR[0:3] = 15
ZLOAD = ZLOPT according to
Table 4-1 on page 9 and
Table 4-2 on page 9
(5)
POUT_3
VS = 3.0V
PWR[0:3] = 15
5, 8
IS_P3
VS = 3.6V
PWR[0:3] = 15
5, 8
IS_P3
(5)
ΔPOUT
6, 7
RM_MAX
6, 7
CM
Tamb = –40°C to +125°C
Output Power Variation VS = 1.9V to 3.6V
for full temperature and Pout = POUT_x + ΔPOUT
supply voltage range
(can be applied to all power
levels)
Maximum series
resistance RM of XTAL
after start-up
3.2
Motional capacitance of
Recommended values
XTAL
3.4
4.0
11.0
Typ.
Max.
Unit
Type*
5.4
6.7
mA
B
7.0
mA
A
5.5
7.0
dBm
A
7.3
8.8
mA
B
9.1
mA
A
12.5
14.0
dBm
B
20.2
23.5
mA
A
24.5
mA
A
+1.5
dB
B
170
Ω
D
15
fF
D
mVpp
A
ppm
C
–4.0
Crystal Oscillator (XTO)
3.1
3.3
Min.
Stabilized Amplitude
XTAL
C0 < 2.0pF
C0 < 2.0pF
CM = 4.0fF
RM = 20Ω
CLOAD = 9pF
V(XTO2) – V(XTO1)
V(XTO1)
1.0 < C0 < 2.0pF
RM < 170Ω
Pulling of fXTO versus
temperature and supply CLOAD = 9pF
change
4fF < CM < 10fF
CM < 15fF
2
4.0
6, 7
VppXTO21
VppXTO1
6, 7
ΔfRF
640
320
–3
+3
–5
+5
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
(Pin Number) in brackets mean they are measured matched to 50Ω according to Figure 4-2 on page 8 with component values
and optimum load impedances according to Table 4-1 and Table 4-2 on page 9
19
9128E–RKE–09/10
10. Electrical Characteristics (Continued)
VS = 1.9V to 3.6V Tamb = –40°C to +125°C, CLK_ON = “High”; DIV_CNTRL = “Low”, CLOAD_CLK = 10pF. fXTO = 13.0000MHz,
fCLK = 1.625MHz unless otherwise specified. If crystal parameters are important values correspond to a crystal with CM = 4.0fF,
C0 = 1.5pF, CLOAD = 9pF and RM ≤ 170Ω. Typical values are given at VS = 3.0V and Tamb = 25°C
No. Parameters
Test Conditions
Pin
Symbol
DC voltage after XTAL
amplitude stable
V(XTO2) – V(XTO1)
XTO running
6, 7
VDC_XTO
Negative real part of
XTO impedance at
begin of start-up
This value is important for
crystal oscillator start-up
behavior
C0 < 2.0pF,
8pF < CLOAD < 10pF
FXTAL = 13.000MHz
11.0MHz < FXTAL < 14.8MHz
6, 7
3.7
External Capacitors
C4, C5
Recommended values for proper
start-up and low current
consumption
Quality NPO
CLOAD = (C4 + CXTO1) ×
(C5 + CXTO2) /
(C4 + C5 + CXTO1 + CXTO2)
CLoad_nom = 9pF (inc. PCB)
6, 7
C4
C5
–5%
15
3.8
Pin Capacitance
XTO1 and XTO2
The PCB Capacitance of about
1pF has to be added
6, 7
CXTO1
CXTO2
–15%
–15%
3.9
Crystal oscillator
start-up time
Time between EN = “High” and
XTO_RDY = “High”
C0 < 2.0pF, 4fF < CM < 15fF
C0 < 2.0pF, 2fF < CM < 15fF
RM < 170Ω
11.0MHz < FXTAL < 14.8MHz
6, 7, 1
3.10
Required for stable operation of
Maximum shunt
capacitance C0 of XTAL XTO, CLoad > 7. 5pF
3.11
Oscillator frequency
XTO
3.5
3.6
4
433.92MHz and 315MHz other
frequencies
Min.
Unit
Type*
40
mV
C
–2,200
Ω
B
+5%
pF
D
2
2
+15%
+15%
pF
C
ΔTXTO
0.20
0.32
0.3
0.5
ms
B
6, 7
C0_MAX
1.5
3.0
pF
D
6, 7
fXTO
11.0
14.8
MHz
C
5
fRF
300
367
368
450
MHz
A
98.46
µs
B
1, 5
ΔTPLL
RXTO12_START –1,500
Typ.
Max.
–1,300
13.0000
Fractional-N-PLL
4.1
Frequency range of RF S434_N315 = “LOW”
frequency
S434_N315 = “HIGH”
4.2
Time between
XTO_RDY= “High” and Register
Locking time of the PLL programmed till PLL is locked
fXTO = 13.0000MHz
other fXTO
4.3
PLL loop bandwidth
Unity gain loop frequency of
synthesizer
5
fLoop_PLL
4.4
In Loop phase noise
PLL
25kHz distance to carrier
5
4.5
Out of Loop Phase
noise (VCO)
At 1MHz
At 36MHz
5
⎛ 1280/⎞
⎝ f XTO ⎠
140
280
380
kHz
B
LPLL
–83
–76
dBc/Hz
A
Lat1M
Lat36M
–91
–122
–84
–115
dBc/Hz
dBc/Hz
A
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
20
(Pin Number) in brackets mean they are measured matched to 50Ω according to Figure 4-2 on page 8 with component values
and optimum load impedances according to Table 4-1 and Table 4-2 on page 9
ATA5749
9128E–RKE–09/10
ATA5749
10. Electrical Characteristics (Continued)
VS = 1.9V to 3.6V Tamb = –40°C to +125°C, CLK_ON = “High”; DIV_CNTRL = “Low”, CLOAD_CLK = 10pF. fXTO = 13.0000MHz,
fCLK = 1.625MHz unless otherwise specified. If crystal parameters are important values correspond to a crystal with CM = 4.0fF,
C0 = 1.5pF, CLOAD = 9pF and RM ≤ 170Ω. Typical values are given at VS = 3.0V and Tamb = 25°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
2, 5
FMOD_FSK
2, 5
FMOD_ASK
4.6
FSK modulation
frequency
Duty cycle of the modulation
signal = 50%, (this corresponds
to 40kBit/s Manchester coding
and 80kBit/s NRZ coding)
4.7
ASK modulation
frequency
Duty cycle of the modulation
signal = 50%, (this corresponds
to 40kBit/s Manchester coding
and 80kBit/s NRZ coding)
4.8
Spurious emission
At fRF ±fXTO / 8
At fRF ±fXTO / 4
At fRF ±fXTO
5
Spur
4.9
Spurious emission
DIV_CNTRL = “High”
At fRF ± fXTO / 4
At fRF ± fXTO
5
Spur
4.10 Spurious emission
CLK_ON = “Low”
At f0 ± fXTO
5
Spur
4.11 Fractional Spurious
ASK_NFSK = “High”
TX_Mode_2
FREQ[0:14] = 3730,
FSEP[0:7] = 101
S434_N315 = “Low”
fRF ±3.00MHz
fRF ±6.00MHz
FREQ[0:14] = 14342,
FSEP[0:7] = 101
S434_N315 = “High”
fRF ±3.159MHz
fRF ± 9.840MHz
5
Spur
FSK frequency
4.12
deviation
fXTO = 13.0000MHz
other fXTO
see Table 3-1 on page 4
4.13 Frequency resolution
fXTO = 13.0000MHz
other fXTO
Typ.
Max.
Unit
Type*
0
40
kHz
B
0
40
kHz
B
dBc
B
dBc
B
dBc
B
dBc
B
kHz
A
Hz
A
–47
–47
–60
–47
–58
–60
–50
–50
–50
–50
5
fdev
±0.396
±101.16
⎛ f XTO / ⎞
⎝ 32768⎠
⎛ f XTO / ⎞
⎝ 128.5⎠
793
ΔfPLL
⎛ f XTO / ⎞
⎝ 16384⎠
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
(Pin Number) in brackets mean they are measured matched to 50Ω according to Figure 4-2 on page 8 with component values
and optimum load impedances according to Table 4-1 and Table 4-2 on page 9
21
9128E–RKE–09/10
11. Timing Characteristics (Atmel ATA5749)
VS = 1.9V to 3.6V, Tamb = –40°C to +125°C. Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND
(pin 9). Parameters where crystal relevant parameters are important correspond to a crystal with CM = 4.0fF, C0 = 1.5pF, CLOAD = 9pF
and RM ≤ 170Ω unless otherwise specified.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1.1
EN set-up time to rising
edge of SCK
1, 10
TEN_setup
10
µs
C
1.2
SDIN_TXDIN set-up time
to falling edge of EN
2, 10
TSDIN_TXDIN
125
ns
C
1.3
SDIN_TXDIN set-up time
to rising edge of SCK
2, 3
TSetup
10
ns
C
1.4
SDIN_TXDIN hold time
from rising edge of SCK
2, 3
THold
10
ns
C
_setup
1.5
SCK Cycle time
3
TSCK_Cycle
500
ns
C
1.6
SCK high time period
3
TSCK_High
200
ns
C
1.7
SCK low time period
3
TSCK_Low
200
ns
C
1.8
EN low time period with
SDIN_TXDIN = “High” for
register reset
2, 10
TEN_Reset
10
us
C
1.9
Clock output frequency
(CMOS microcontroller
compatible)
fXTO = 13.000MHz
DIV_CNTRL = “High”
(fCLK = fXTO / 4)
DIV_CNTRL = “Low”
(fCLK = fXTO / 8)
1
fCLK
MHz
A
Clock output minimum
“High” and “Low” time
Cload ≤ 20pF,
DIV_CNTRL = “Low”
(fclk = fXTO / 8)
“High” = 0.8 × VS,
“Low” = 0.2 × VS,
fCLK < 1.625MHz
1
TCLKLH
125
220
ns
A
Clock output minimum
“High” and “Low” time
Cload ≤ 10pF,
DIV_CNTRL = “High”
(fclk = fXTO / 4)
“High” = 0.8 × VS,
“Low” = 0.2 × VS,
fCLK < 3.25MHz
1
TCLKLH
62.5
110
ns
A
Clock output minimum
“High” and “Low” time
Cload ≤ 20pF,
DIV_CNTRL = “Low”
(fclk = fXTO / 8)
“High” = 0.8 × VS,
“Low” = 0.2 × VS,
fCLK < 1.85MHz
1
TCLKLH
125
180
ns
C
Clock output minimum
“High” and “Low” time
Cload ≤ 10pF,
DIV_CNTRL = “High”
(fclk = fXTO / 4)
“High” = 0.8 × VS,
“Low” = 0.2 × VS,
fCLK < 3.7MHz
1
TCLKLH
62.6
90
ns
C
1.10
1.11
1.12
1.13
3.25
1.625
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
22
ATA5749
9128E–RKE–09/10
ATA5749
12. Digital Port Characteristics
VS = 1.9V to 3.6V, Tamb = 40°C to +125°C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25°C, all inputs are
Schmitt trigger interfaces.
No. Parameters
Test Conditions
1.1
1.2
1.3
SDIN_TXDIN
SCK
EN input
Pin
Symbol
Min.
“Low” level input voltage
“High” level input voltage
Internal pull-down resistor
VII
Vih
RPDN
0
VS – 0.25
160
“Low” level input voltage
“High” level input voltage
Internal pull-down resistor
VII
Vih
RPDN
0
VS – 0.25
160
“Low” level input voltage
“High” level input voltage
Internal pull-down resistor
VII
Vih
RPDN
0
VS – 0.25
160
Typ.
Max.
Unit
Type*
V
V
kΩ
A
250
0.25
VS
380
V
V
kΩ
A
250
0.25
VS
380
V
V
kΩ
A
250
0.23
VS
380
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
23
9128E–RKE–09/10
13. Ordering Information
Extended Type Number
Package
Remarks
ATA5749-6DQ
TSSOP10
-
14. Package Information
Package: TSSOP 10
(acc. to JEDEC Standard MO-187)
3±0.1
3±0.1
0.25
3.8±0.3
0.5 nom.
0.15
0.85±0.1
1.1 max
Dimensions in mm
Not indicated tolerances ± 0.05
4.9±0.1
4 x 0.5 = 2 nom.
10 9 8 7 6
technical drawings
according to DIN
specifications
Drawing-No.: 6.543-5095.01-4
1 2 3 4 5
24
Issue: 3; 16.09.05
ATA5749
9128E–RKE–09/10
ATA5749
15. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
9128E-RKE-09/10
• El. Char. table: rows 1.2, 1.3, 1.4, 1.7, 1.8, 1.9, 2.1, 2.2, 2.4, 2.5 changed
• Dig. Port Char. table: row 1.3 changed
• Ordering table changed
9128D-RKE-01/09
• Features on page 1 changed
• Section 8 “Absolute Maximum Ratings” on page 17 changed
9128C-RKE-10/08
• Features on page 1 changed
• Section 8 “Absolute Maximum Ratings” on page 17 changed
• Section 12 “Digital Port Characteristics” on page 23 changed
9128B-RKE-08/08
• Put datasheet in the newest template
• Features on page 1 changed
• Section 1 “Description” on page 1 changed
• Figure 1-1 “Block Diagram” on page 2 changed
• Section 3.1 “Fractional-N PLL” on page 4 changed
• Section 3.4 “Clock Driver” on page 6 changed
• Figure 4-1 “Typical Application Circuit” on page 7 changed
• Figure 4-2 “Output Power Measurement Circuit” on page 8 changed
• Section 10 “Electrical Characteristics” numbers 4.2, 4.12 and 4.13 on
pages 20 to 21 changed
25
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