PIC16F193X/LF193X Data Sheet 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology © 2008 Microchip Technology Inc. Preliminary DS41364A Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41364A-page ii Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers Devices Included In This Data Sheet: Low-Power Features: PIC16F193X Devices: • Standby Current: - 100 nA @ 2.0V, typical (PIC16LF193X) • Operating Current: - 6.0 μA @ 32 kHz, 2.0V, typical (PIC16LF193X) - 54 μA @ 1 MHz, 2.0V, typical (PIC16LF193X) • Low-Power Watchdog Timer Current: - 1.0 μA @ 2.0V, typical (PIC16LF193X) • PIC16F1933 • PIC16F1934 • PIC16F1936 • PIC16F1937 • PIC16F1938 • PIC16F1939 PIC16LF193X Devices: • PIC16LF1933 • PIC16LF1934 • PIC16LF1936 • PIC16LF1937 • PIC16LF1938 • PIC16LF1939 Peripheral Features: High-Performance RISC CPU: • Only 49 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 32 MHz oscillator/clock input - DC – 125 ns instruction cycle • Up to 16K x 14 Words of Flash Program Memory • Up to 1024 Bytes of Data Memory (RAM) • Interrupt Capability • 16-Level Deep Hardware Stack • Direct, Indirect and Relative Addressing modes • Processor Read Access to Program Memory • Pinout Compatible to other 28/40-pin PIC16CXXX and PIC16FXXX Microcontrollers Special Microcontroller Features: • Precision Internal Oscillator: - Factory calibrated to ±1%, typical - Software selectable frequency range from 32 MHz to 31 kHz • Power-Saving Sleep mode • Industrial and Extended Temperature Range • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Brown-out Reset (BOR) - Selectable between two trip points - Disable in Sleep option • Multiplexed Master Clear with Pull-up/Input Pin • Programmable Code Protection • High Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM retention: > 40 years • Wide Operating Voltage Range: - 1.8V-5.5V (PIC16F193X) - 1.8V-3.6V (PIC16LF193X) © 2008 Microchip Technology Inc. • Up to 35 I/O Pins and 1 Input-only pin: - High-current source/sink for direct LED drive - Individually programmable Interrupt-on-pin change pins - Individually programmable weak pull-ups • A/D Converter: - 10-bit resolution and up to 14 channels - Can operate during Sleep - Selectable 1.024/2.048/4.096V voltage reference • Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler • Enhanced Timer1 - Dedicated low-power 32 kHz oscillator - 16-bit timer/counter with prescaler - External Gate Input mode with toggle and single shot modes - Interrupt-on-gate completion • Timer2, 4, 6: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler • Two Capture, Compare, PWM Modules (CCP) - 16-bit Capture, max. resolution 12.5 ns - 16-bit Compare, max. resolution 200 ns - 10-bit PWM, max. frequency 20 kHz • Three Enhanced Capture, Compare, PWM modules (ECCP) - Software selectable time-bases - Auto-shutdown and auto-restart - PWM steering • Master Synchronous Serial Port (SSP) with SPI and I2 CTM with: - 7-bit address masking - SMBUS/PMBUSTM compatibility • Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) - RS-232, RS 485 and LIN compatible - Auto-Baud Detect - Auto-wake-up on start Preliminary DS41364A-page 1 PIC16F193X/LF193X Peripheral Features (Continued): • SR Latch (555 Timer): - Multiple Set/Reset input options • Integrated LCD Controller: - Up to 96 segments - Variable clock input - Contrast control - Internal voltage reference selections • 2 Comparators: - Rail-to-rail inputs/outputs - Power mode control - Software enable hysteresis • Voltage Reference module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection PIC16F193X/LF193X Family Types Program Data Memory SRAM I/Os EEPROM Flash (bytes) (bytes) (words) Device 10-bit MI2C/ Timers EUSART A/D Comparators 8/16-bit SPI (ch) ECCP Full Bridge ECCP Half Bridge CCP LCD PIC16F1933 PIC16LF1933 4096 256 256 25 11 2 4/1 Yes Yes 1 2 2 16(1)/4 PIC16F1934 PIC16LF1934 4096 256 256 36 14 2 4/1 Yes Yes 2 1 2 24/4 PIC16F1936 PIC16LF1936 8192 256 512 25 11 2 4/1 Yes Yes 1 2 2 16(1)/4 PIC16F1937 PIC16LF1937 8192 256 512 36 14 2 4/1 Yes Yes 2 1 2 24/4 PIC16F1938 PIC16LF1938 16384 256 1024 25 14 2 4/1 Yes Yes 1 2 2 16(1)/4 PIC16F1939 PIC16LF1939 16384 256 1024 36 14 2 4/1 Yes Yes 2 1 2 24/4 Note 1: COM3 and SEG15 share the same physical pin on PIC16F1933/1936/1938/PIC16LF1933/1936/1938, therefore, SEG15 is not available when using 1/4 multiplex displays. DS41364A-page 2 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X Pin Diagram – 28-Pin SPDIP/SOIC/SSOP (PIC16F1933/1936/1938, PIC16LF1933/1936/1938) 28-pin SPDIP, SOIC, SSOP RB7/ICSPDAT/ICDDAT/SEG13 SEG12/VCAP /SS /SRNQ /C2OUT /C12IN0-/AN0/RA0 2 RB6/ICSPCLK/ICDCLK/SEG14 SEG7/C12IN1-/AN1/RA1 3 26 RB5/AN13/CPS5/P2B(1)/CCP3(1)/P3A(1)/T1G(1)/COM1 25 24 RB4/AN11/CPS4/P1D/COM0 RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3 23 RB2/AN8/CPS2/P1B/VLCD2 22 21 RB1/AN10/C12IN3-/CPS1/P1C/VLCD1 RB0/AN12/CPS0/CCP4/SRI/INT/SEG0 20 VDD 19 VSS 18 RC7/RX/DT/P3B/SEG8 (1) (1) COM2/CVREF/VREF-/C2IN+/AN2/RA2 4 SEG15/COM3/VREF+/C1IN+/AN3/RA3 5 SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4 6 SEG5/VCAP(2)/SS(1)/SRNQ(1)/CPS7/C2OUT(1)/AN4/RA5 VSS 7 8 9 SEG2/CLKIN/OSC1/RA7 Note PIC16LF1933/1936/1938 28 27 (1) PIC16F1933/1936/1938 1 VPP/MCLR/RE3 (2) SEG1/VCAP(2)/CLKOUT/OSC2/RA6 P2B(1)/T1CKI/T1OSO/RC0 10 11 P2A(1)/CCP2(1)/T1OSI/RC1 12 17 RC6/TX/CK/CCP3(1)/P3A(1)/SEG9 SEG3/P1A/CCP1/RC2 SEG6/SCL/SCK/RC3 13 16 RC5/SDO/SEG10 14 15 RC4/SDI/SDA/T1G(1)/SEG11 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 3 PIC16F193X/LF193X 28 27 26 25 24 23 22 RA1/AN1/C12IN1-/SEG7 RA0/AN0/C12IN0-/C2OUT(1)/SRNQ(1)/SS(1)/VCAP(2)/SEG12 28-pin QFN RE3/MCLR/VPP RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCLK/SEG14 RB5/AN13/CPS5/P2B(1)/CCP3(1)/P3A(1)/T1G(1)/COM1 RB4/AN11/CPS4/P1D/COM0 Pin Diagram – 28-Pin QFN (PIC16F1933/1936/1938, PIC16LF1933/1936/1938) 1 21 2 20 3 PIC16F1933/1936/1938 19 4 PIC16LF1933/1936/1938 18 5 17 6 16 7 15 RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3 RB2/AN8/CPS2/P1B/VLCD2 RB1/AN10/C12IN3-/CPS1/P1C/VLCD1 RB0/AN12/CPS0/CCP4/SRI/INT/SEG0 VDD VSS RC7/RX/DT/P3B/SEG8 DS41364A-page 4 SEG3/P1A/CCP1/RC2 SEG6/SCL/SCK/RC3 SEG11/T1G(1)/SDA/SDI/RC4 SEG10/SDO/RC5 SEG9/P3A(1)/CCP3(1)/CK/TX/RC6 P2B(1)/T1CKI/T1OSO/RC0 Note (1)P2A/(1)CCP2/T1OSI/RC1 8 9 10 11 12 13 14 COM2/CVREF/VREF-/C2IN+/AN2/RA2 SEG15/COM3/VREF+/C1IN+/AN3/RA3 SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4 SEG5(1)/VCAP(2)/SS(1)/SRNQ/CPS7/C2OUT(1)/AN4/RA5 VSS SEG2/CLKIN/OSC1/RA7 SEG1/VCAP(2)/CLKOUT/OSC2/RA6 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X SRNQ(1) — — — 28 AN1 — C12IN1- — — — — 1 AN2/ VREF- — C2IN+/ CVREF — — — — 2 AN3/ VREF+ — C1IN+ — — — — Basic C12IN0-/ C2OUT(1) Pull-up — Interrupt AN0 LCD 27 MSSP EUSART 5 CCP RA3 Timers 4 SR Latch 3 RA2 Comparator RA1 Cap Sense 2 A/D 28-Pin SIP RA0 28-PIN SUMMARY (PIC16F1933/1936/1938, PIC16LF1933/1936/1938) 28-Pin QFN I/O TABLE 1: SS(1) SEG12 — — VCAP(2) — SEG7 — — — — COM2 — — — — SEG15/ COM3 — — — RA4 6 3 — CPS6 C1OUT SRQ T0CKI CCP5 — — SEG4 — — — RA5 7 4 AN4 CPS7 C2OUT(1) SRNQ(1) — — — SS(1) SEG5 — — VCAP(2) RA6 10 7 — — — — — — — — SEG1 — — OSC2/ CLKOUT VCAP(2) RA7 9 6 — — — — — — — — SEG2 — — OSC1/ CLKIN RB0 21 18 AN12 CPS0 — SRI — CCP4 — — SEG0 INT/ IOC Y — RB1 22 19 AN10 CPS1 C12IN3- — — P1C — — VLCD1 IOC Y — RB2 23 20 AN8 CPS2 — — — P1B — — VLCD2 IOC Y — RB3 24 21 AN9 CPS3 C12IN2- — — CCP2(1)/ P2A(1) — — VLCD3 IOC Y — RB4 25 22 AN11 CPS4 — — — P1D — — COM0 IOC Y — RB5 26 23 AN13 CPS5 — — T1G(1) P2B(1) CCP3(1)/ P3A(1) — — COM1 IOC Y — RB6 27 24 — — — — — — — — SEG14 IOC Y ICSPCLK/ ICDCLK RB7 28 25 — — — — — — — — SEG13 IOC Y ICSPDAT/ ICDDAT RC0 11 8 — — — — T1OSO/ T1CKI P2B(1) — — — — — — RC1 12 9 — — — — T1OSI CCP2(1)/ P2A(1) — — — — — — RC2 13 10 — — — — — CCP1/ P1A — — SEG3 — — — RC3 14 11 — — — — — — — SCK/SCL SEG6 — — — RC4 15 12 — — — — T1G(1) — — SDI/SDA SEG11 — — — RC5 16 13 — — — — — — — SDO SEG10 — — — RC6 17 14 — — — — — CCP3(1) P3A(1) TX/CK — SEG9 — — — RC7 18 15 — — — — — P3B RX/DT — SEG8 — — — RE3 1 — — — — — — — — — — Y MCLR/VPP VDD 20 17 — — — — — — — — — — — VDD Vss 8, 5, 19 16 — — — — — — — — — — — VSS Note 1: 2: 26 Pin functions can be moved using the APFCON register. PIC16F193X devices only. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 5 PIC16F193X/LF193X Pin Diagram – 40-Pin PDIP (PIC16F1934/1937/1939, PIC16LF1934/1937/1939) 40-Pin PDIP VPP/MCLR/RE3 1 40 RB7/ICSPDAT/ICDDAT/SEG13 SEG12/VCAP(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0 2 39 RB6/ICSPCLK/ICDCLK/SEG14 SEG7/C12IN1-/AN1/RA1 3 38 RB5/AN13/CPS5/CCP3(1)/P3A(1)/T1G(1)/COM1 COM2/CVREF/VREF-/C2IN+/AN2/RA2 4 37 RB4/AN11/CPS4/COM0 SEG15/VREF+/C1IN+/AN3/RA3 5 36 RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3 6 35 RB2/AN8/CPS2/VLCD2 7 34 RB1/AN10/C12IN3-/CPS1/VLCD1 SEG21/CCP3(1)/P3A(1)/AN5/RE0 8 33 RB0/AN12/CPS0/SRI/INT/SEG0 SEG22/P3B/AN6/RE1 9 32 VDD 31 VSS 30 RD7/CPS15/P1D/SEG20 29 RD6/CPS14/P1C/SEG19 28 RD5/CPS13/P1B/SEG18 SEG23/CCP5/AN7/RE2 10 VDD 11 VSS 12 SEG2/CLKIN/OSC1/RA7 13 CAP(2)/CLKOUT/OSC2/RA6 14 27 RD4/CPS12/P2D/SEG17 (1)/T1CKI/T1OSO/RC0 15 26 RC7/RX/DT/SEG8 P2A(1)/CCP2(1)/T1OSI/RC1 16 25 RC6/TX/CK/SEG9 SEG3/P1A/CCP1/RC2 17 24 RC5/SDO/SEG10 SEG6/SCK/SCL/RC3 18 23 RC4/SDI/SDA/T1G(1)/SEG11 COM3/CPS8/RD0 19 22 RD3/CPS11/P2C/SEG16 20 21 RD2/CPS10/P2B(1) SEG1/V P2B CCP4/CPS9/RD1 Note DS41364A-page 6 PIC16F1934/1937/1939 PIC16LF1934/1937/1939 SEG4/SRQ/T0CKI/CPS6/C1OUT/RA4 SEG5/VCAP(2)/SS(1)/SRNQ(1)/CPS7/C2OUT(1)/AN4/RA5 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X Pin Diagram – 44-Pin QFN (PIC16F1934/1937/1939, PIC16LF1934/1937/1939) 12 13 14 15 16 17 18 19 20 21 22 1 33 2 32 3 31 4 30 5 PIC16F1934/1937/1939 29 6 PIC16LF1934/1937/1939 28 7 27 8 26 9 25 10 24 11 23 RA6/OSC2/CLKOUT/VCAP(2)/SEG1 RA7/OSC1/CLKIN/SEG2 VSS VSS NC VDD RE2/AN7/CCP5/SEG23 RE1/AN6/P3B/SEG22 RE0/AN5/CCP3(1)/P3A(1)/SEG21 RA5/AN4/C2OUT(1)/CPS7/SRNQ(1)/SS(1)/VCAP(2)/SEG5 RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4 VLCD3/P2A(1)/CCP2(1)/CPS3/C12IN2-/AN9/RB3 NC COM0/CPS4/AN11/RB4 COM1/T1G(1)/P3A(1)/CCP3(1)/CPS5/AN13/RB5 SEG14/ICDCLK/ICSPCLK/RB6 SEG13/ICDDAT/ICSPDAT/RB7 VPP/MCLR/RE3 (1) (1) (2) SEG12/VCAP /SS /SRNQ /C2OUT(1)/C12IN0-/AN0/RA0 SEG7/C12IN1-/AN1/RA1 COM2/CVREF/VREF-/C2IN+/AN2/RA2 SEG15VREF+/C1IN+/AN3/RA3 SEG8/DT/RX/RC7 SEG17/P2D/CPS12/RD4 SEG18/P1B/CPS13/RD5 SEG19/P1C/CPS14/RD6 SEG20/P1D/CPS15/RD7 VSS VDD VDD SEG0/INT/SRI/CPS0/AN12/RB0 VLCD1/CPS1/C12IN3-/AN10/RB1 VLCD2/CPS2/AN8/RB2 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK/SEG9 RC5/SDO/SEG10 RC4/SDI/SDA/T1G(1)/SEG11 RD3/CPS11/P2C/SEG16 RD2/CPS10/P2B(1) RD1/CPS9/CCP4 RD0/CPS8/COM3 RC3/SCL/SCK/SEG6 RC2/CCP1/P1A/SEG3 RC1/T1OSI/CCP2(1)/P2A(1) RC0/T1OSO/T1CKI/P2B(1) 44-pin QFN Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 7 PIC16F193X/LF193X Pin Diagram – 44-Pin TQFP (PIC16F1934/1937/1939, PIC16LF1934/1937/1939) 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 PIC16F1934/1937/1939 6 PIC16LF1934/1937/1939 7 8 9 10 11 NC RC0/T1OSO/T1CKI/P2B(1) RA6/OSC2/CLKOUT/VCAP(2)/SEG1 RA7/OSC1/CLKIN/SEG2 VSS VDD RE2/AN7/CCP5/SEG23 RE1/AN6/P3B/SEG22 RE0/AN5/CCP3(1)/P3A(1)/SEG21 RA5/AN4/C2OUT(1)/CPS7/SRNQ(1)/SS(1)/VCAP(2)/SEG5 RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4 NC NC COM0/CPS4/AN11/RB4 (1)/P3A(1)/CCP3(1)/CPS5/AN13/RB5 COM1/T1G SEG14/ICDCLK/ICSPCLK/RB6 SEG13/ICDDAT/ICSPDAT/RB7 VPP/MCLR/RE3 SEG12/VCAP(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0 SEG7/C12IN1-/AN1/RA1 COM2/CVREF/VREF-/C2IN+/AN2/RA2 SEG15/VREF+/C1IN+/AN3/RA3 SEG8/DT/RX/RC7 SEG17/P2D/CPS12/RD4 SEG18/P1B/CPS13/RD5 SEG19/P1C/CPS14/RD6 SEG20/P1D/CPS15/RD7 VSS VDD SEG0/INT/SRI/CPS0/AN12/RB0 VLCD1/CPS1/C12IN3-/AN10/RB1 VLCD2/CPS2/AN8/RB2 VLCD3/P2A(1)/CCP2(1)/CPS3/C12IN2-/AN9/RB3 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK/SEG9 RC5/SDO/SEG10 RC4/SDI/SDA/T1G(1)/SEG11 RD3/CPS11/P2C/SEG16 RD2/CPS10/P2B(1) RD1/CPS9/CCP4 RD0/CPS8/COM3 RC3/SCL/SCK/SEG6 RC2/CCP1/P1A/SEG3 RC1/T1OSI/CCP2(1)/P2A(1) NC 44-pin TQFP Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. DS41364A-page 8 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X SRNQ(1) — — — 20 AN1 — C12IN1- — — — — 21 AN2/ VREF- — C2IN+/ CVREF — — — — 22 22 AN3/ VREF+ — C1IN+ — — — — Basic C12IN0-/ C2OUT(1) Pull-up — Interrupt AN0 LCD 5 19 MSSP RA3 EUSART 21 CCP 20 4 Timers 3 RA2 SR Latch RA1 Comparator 19 Cap Sense 44-Pin TQFP 2 A/D 40-Pin PDIP RA0 40/44-PIN SUMMARY(PIC16F1934/1937/1939, PIC16LF1934/1937/1939) 44-Pin QFN I/O TABLE 2: SS(1) SEG12 — — VCAP — SEG7 — — — — COM2 — — — — SEG15 — — — RA4 6 23 23 — CPS6 C1OUT SRQ T0CKI — — SEG4 — — — RA5 7 24 24 AN4 CPS7 C2OUT(1) SRNQ(1) — — — SS(1) SEG5 — — VCAP RA6 14 31 33 — — — — — — — — SEG1 — — OSC2/ CLKOUT VCAP RA7 13 30 32 — — — — — — — — SEG2 — — OSC1/ CLKIN RB0 33 8 9 AN12 CPS0 — SRI — — — — SEG0 INT/ IOC Y — — RB1 34 9 10 AN10 CPS1 C12IN3- — — — — — VLCD1 IOC Y RB2 35 10 11 AN8 CPS2 — — — — — — VLCD2 IOC Y — RB3 36 11 12 AN9 CPS3 C12IN2- — — CCP2(1)/ P2A(1) — — VLCD3 IOC Y — RB4 37 14 14 AN11 CPS4 — — — — — — COM0 IOC Y — RB5 38 15 15 AN13 CPS5 — — T1G(1) CCP3(1)/ P3A(1) — — COM1 IOC Y — RB6 39 16 16 — — — — — — — — SEG14 IOC Y ICSPCLK/ ICDCLK RB7 40 17 17 — — — — — — — — SEG13 IOC Y ICSPDAT/ ICDDAT RC0 15 32 34 — — — — T1OSO/ T1CKI P2B(1) — — — — — — RC1 16 35 35 — — — — T1OSI CCP2(1)/ P2A(1) — — — — — — RC2 17 36 36 — — — — — CCP1/ P1A — — SEG3 — — — — RC3 18 37 37 — — — — — — — SCK/SCL SEG6 — — RC4 23 42 42 — — — — T1G(1) — — SDI/SDA SEG11 — — — RC5 24 43 43 — — — — — — — SDO SEG10 — — — RC6 25 44 44 — — — — — — TX/CK — SEG9 — — — RC7 26 1 1 — — — — — — RX/DT — SEG8 — — — RD0 19 38 38 — CPS8 — — — — — — COM3 — — — RD1 20 39 39 — CPS9 — — — CCP4 — — — — — — RD2 21 40 40 — CPS10 — — — P2B(1) — — — — — — RD3 22 41 41 — CPS11 — — — P2C — — SEG16 — — — RD4 27 2 2 — CPS12 — — — P2D — — SEG17 — — — RD5 28 3 3 — CPS13 — — — P1B — — SEG18 — — — RD6 29 4 4 — CPS14 — — — P1C — — SEG19 — — — RD7 30 5 5 — CPS15 — — — P1D — — SEG20 — — — RE0 8 25 25 AN5 — — — — CCP3(1) P3A(1) — — SEG21 — — — — RE1 9 26 26 AN6 — — — — P3B — — SEG22 — — RE2 10 27 27 AN7 — — — — CCP5 — — SEG23 — — — RE3 1 18 18 — — — — — — — — — — Y MCLR/VPP VDD 11, 32 7, 28 7,8, 28 — — — — — — — — — — — VDD Vss 12, 6, 6,30, 31 29 31 — — — — — — — — — — — VSS Note 1: Pin functions can be moved using the APFCON register. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 9 PIC16F193X/LF193X Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Memory Organization ................................................................................................................................................................. 19 3.0 Resets ........................................................................................................................................................................................ 55 4.0 Interrupts .................................................................................................................................................................................... 67 5.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 79 6.0 I/O Ports ..................................................................................................................................................................................... 81 7.0 Interrupt-on-Change ................................................................................................................................................................. 101 8.0 Oscillator Module (With Fail-Safe Clock Monitor)..................................................................................................................... 105 9.0 SR Latch................................................................................................................................................................................... 119 10.0 Device Configuration ................................................................................................................................................................ 123 11.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 129 12.0 Comparator Module.................................................................................................................................................................. 141 13.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 149 14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 153 15.0 Timer0 Module ......................................................................................................................................................................... 155 16.0 Timer1 Module ......................................................................................................................................................................... 159 17.0 Timer2/4/6 Modules.................................................................................................................................................................. 171 18.0 Capacitive Sensing Module ...................................................................................................................................................... 175 19.0 Capture/Compare/PWM (ECCP1, ECCP2, ECCP3, CCP4, CCP5) Modules .......................................................................... 181 20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 211 21.0 Liquid Crystal Display (LCD) Driver Module ............................................................................................................................. 239 22.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 273 23.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 321 24.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 333 25.0 In-Circuit Serial Programming™ (ICSP™) ................................................................................................................................ 335 26.0 Instruction Set Summary .......................................................................................................................................................... 337 27.0 Development Support............................................................................................................................................................... 351 28.0 Electrical Specifications............................................................................................................................................................ 355 29.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 389 30.0 Packaging Information.............................................................................................................................................................. 391 Appendix A: Revision History............................................................................................................................................................. 403 Appendix B: Device Differences......................................................................................................................................................... 403 Index .................................................................................................................................................................................................. 405 The Microchip Web Site ..................................................................................................................................................................... 413 Customer Change Notification Service .............................................................................................................................................. 413 Customer Support .............................................................................................................................................................................. 413 Reader Response .............................................................................................................................................................................. 414 Product Identification System............................................................................................................................................................. 415 DS41364A-page 10 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 11 PIC16F193X/LF193X NOTES: DS41364A-page 12 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 1.0 DEVICE OVERVIEW The PIC16F193X/LF193X devices are described within this data sheet. They are available in 28/40/44-pin packages. Figure 1-1 shows a block diagram of the PIC16F193X/LF193X devices. Table 1-1 shows the pinout descriptions. FIGURE 1-1: PIC16F193X/LF193X BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Direct Addr PORTA RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RAM Program Memory Read (PMR) Instruction Instruction Reg reg 8 Data Bus Program Counter 9 RAM Addr PORTB Addr MUX 7 12 15 Indirect Addr FSR0reg Reg FSR FSR1reg Reg FSR 15 STATUS Reg reg STATUS 8 3 Power-up Timer Instruction Decodeand & Decode Control Oscillator Start-up Timer OSC2/CLKOUT Timing Generation PORTD 8 Watchdog Timer Brown-out Reset RD0 RC1 RD1 RD2 RD3 RD4 RD5 RD6 RD7 W Reg reg W PORTE VDD Comparators RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 MUX Internal Oscillator Block Timer0 PORTC ALU Power-on Reset OSC1/CLKIN RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 Timer1 CCP4/5 © 2008 Microchip Technology Inc. RE0 RE1 RE2 RE3/MCLR VSS Timer2/4/6 ECCP1/2/3 MSSP Timer1 Addressable EUSART Preliminary Data EEPROM 256 bytes SR Latch LCD DS41364A-page 13 PIC16F193X/LF193X 1.1 Enhanced Mid-range CPU PIC16F193X/LF193X devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, indirect, and relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 4.5 “Context Saving”, for more information. 1.1.1 16-LEVEL STACK WITH OVERFLOW AND UNDERFLOW RESET The PIC16F193X/LF193X devices have an external stack memory 15 bits wide and 16 deep. During normal operation, the stack is assumed to be 16 words deep. If enabled, a Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and cause a software Reset. See section Section 2.4 “Stack” for more details. 1.1.2 FILE SELECT REGISTERS There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one data pointer for all memory. When an FSR points to program memory, there is 1 additional instruction cycle in instructions using INDF to allow the data to be fetched. There are also new instructions to support the FSRs. See Section 2.5 “Indirect Addressing, INDF and FSR Registers” for more details. 1.1.3 INSTRUCTION SET There are 48 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 26.0 “Instruction Set Summary” for more details. DS41364A-page 14 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION Name RA0/AN0/C12IN0-/C2OUT(1)/ SRNQ(1)/SS(1)/VCAP(2)/SEG12 RA1/AN1/C12IN1-/SEG7 RA2/AN2/C2IN+/VREF-/CVREF/ COM2 RA3/AN3/C1IN+/VREF+/ COM3(3)/SEG15 RA4/C1OUT/CPS6/T0CKI/SRQ/ CCP5/SEG4 RA5/AN4/C2OUT(1)/CPS7/ SRNQ(1)/SS(1)/VCAP(2)/SEG5 Function Input Type Output Type RA0 TTL AN0 AN C12IN0- AN C2OUT — CMOS Comparator C2 output. SRNQ — CMOS SR Latch inverting output. SS ST — Description CMOS General purpose I/O. — A/D Channel 0 input. — Comparator C1 or C2 negative input. VCAP Power Power SEG12 — AN RA1 TTL AN1 AN C12IN1SEG7 RA2 TTL AN2 AN Slave Select input. Filter capacitor for Voltage Regulator (PIC16F193X only). LCD Analog output. CMOS General purpose I/O. — A/D Channel 1 input. AN — Comparator C1 or C2 negative input. — AN LCD Analog output. CMOS General purpose I/O. — A/D Channel 2 input. C2IN+ AN — Comparator C2 positive input. VREF- AN — A/D Negative Voltage Reference input. CVREF — AN Comparator Voltage Reference output. COM2 — AN LCD Analog output. RA3 TTL AN3 AN — A/D Channel 3 input. C1IN+ AN — Comparator C1 positive input. VREF+ AN — A/D Voltage Reference input. CMOS General purpose I/O. COM3(3) — AN LCD Analog output. SEG15 — AN LCD Analog output. RA4 TTL C1OUT — CPS6 AN — Capacitive sensing input 6. T0CKI ST — Timer0 clock input. CMOS General purpose I/O. CMOS Comparator C1 output. SRQ — CMOS SR Latch non-inverting output. CCP5 ST CMOS Capture/Compare/PWM5. SEG4 — RA5 TTL AN4 AN AN LCD Analog output. CMOS General purpose I/O. — C2OUT — CPS7 AN SRNQ — SS ST — VCAP Power Power SEG5 — AN A/D Channel 4 input. CMOS Comparator C2 output. — Capacitive sensing input 7. CMOS SR Latch inverting output. Slave Select input. Filter capacitor for Voltage Regulator (PIC16F193X only). LCD Analog output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. 3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only. 4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only © 2008 Microchip Technology Inc. Preliminary DS41364A-page 15 PIC16F193X/LF193X TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED) Name RA6/OSC2/CLKOUT/VCAP(2)/ SEG1 RA7/OSC1/CLKIN/SEG2 RB0/AN12/CPS0/CCP4/SRI/INT/ SEG0 RB1/AN10/C12IN3-/CPS1/P1C/ VLCD1 RB2/AN8/CPS2/P1B/VLCD2 RB3/AN9/C12IN2-/CPS3/ CCP2(1)/P2A(1)/VLCD3 Function Input Type RA6 TTL Output Type Description CMOS General purpose I/O. OSC2 — CLKOUT — XTAL VCAP Power Power SEG1 — AN Crystal/Resonator (LP, XT, HS modes). CMOS FOSC/4 output. Filter capacitor for Voltage Regulator (PIC16F193X only). LCD Analog output. RA7 TTL OSC1 XTAL CMOS General purpose I/O. — Crystal/Resonator (LP, XT, HS modes). CLKIN CMOS — External clock input (EC mode). SEG2 — AN LCD Analog output. RB0 TTL AN12 AN CPS0 AN CCP4 ST CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. — A/D Channel 12 input. — Capacitive sensing input 0. CMOS Capture/Compare/PWM4. SRI — ST SR Latch input. INT ST — External interrupt. AN LCD analog output. SEG0 — RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN10 AN — A/D Channel 10 input. C12IN3- AN — Comparator C1 or C2 negative input. CPS1 AN — Capacitive sensing input 1. P1C — VLCD1 AN RB2 TTL CMOS PWM output. — LCD analog input. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN8 AN — A/D Channel 8 input. CPS2 AN — Capacitive sensing input 2. P1B — VLCD2 AN RB3 TTL AN9 AN CMOS PWM output. — LCD analog input. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. — A/D Channel 9 input. C12IN2- AN — Comparator C1 or C2 negative input. CPS3 AN — Capacitive sensing input 3. CCP2 ST CMOS Capture/Compare/PWM2. P2A — CMOS PWM output. VLCD3 AN — LCD analog input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. 3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only. 4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only DS41364A-page 16 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED) Name RB4/AN11/CPS4/P1D/COM0 RB5/AN13/CPS5/P2B/CCP3(1)/ P3A(1)/T1G(1)/COM1 RB6/ICSPCLK/ICDCLK/SEG14 RB7/ICSPDAT/ICDDAT/SEG13 RC0/T1OSO/T1CKI/P2B RC1/T1OSI/CCP2 (1) (1) (1) /P2A RC2/CCP1/P1A/SEG3 RC3/SCK/SCL/SEG6 Function Input Type RB4 TTL Output Type Description CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN11 AN — A/D Channel 11 input. CPS4 AN — Capacitive sensing input 4. P1D — COM0 — RB5 TTL CMOS PWM output. AN LCD Analog output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN13 AN — A/D Channel 13 input. CPS5 AN — Capacitive sensing input 5. P2B — CMOS PWM output. CCP3 ST CMOS Capture/Compare/PWM3. P3A — CMOS PWM output. T1G ST — Timer1 Gate input. COM1 — AN LCD Analog output. RB6 TTL ICSPCLK ST ICDCLK SEG14 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. — Serial Programming Clock. ST — In-Circuit Debug Clock. — AN LCD Analog output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. ICSPDAT ST CMOS ICSP™ Data I/O. ICDDAT ST CMOS In-Circuit Data I/O. SEG13 — AN LCD Analog output. RC0 ST T1OSO XTAL CMOS General purpose I/O. XTAL T1CKI ST — P2B — CMOS PWM output. CMOS General purpose I/O. Timer1 oscillator connection. Timer1 clock input. RC1 ST T1OSI XTAL CCP2 ST CMOS Capture/Compare/PWM2. P2A — CMOS PWM output. XTAL Timer1 oscillator connection. RC2 ST CMOS General purpose I/O. CCP1 ST CMOS Capture/Compare/PWM1. CMOS PWM output. P1A — SEG3 — AN LCD Analog output. RC3 ST CMOS General purpose I/O. SCK ST CMOS SPI clock. SCL I2C OD I2C™ clock. SEG6 — AN LCD Analog output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. 3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only. 4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only © 2008 Microchip Technology Inc. Preliminary DS41364A-page 17 PIC16F193X/LF193X TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED) Name RC4/SDI/SDA/T1G(1)/SEG11 RC5/SDO/SEG10 RC6/TX/CK/CCP3/P3A/SEG9 RC7/RX/DT/P3B/SEG8 RD0(4)/CPS8/COM3 RD1(4)/CPS9/CCP4 RD2(4)/CPS10/P2B RD3(4)/CPS11/P2C/SEG16 RD4(4)/CPS12/P2D/SEG17 RD5(4)/CPS13/P1B/SEG18 Function Input Type RC4 ST Output Type Description CMOS General purpose I/O. SDI ST — SPI data input. SDA I2C OD I2C™ data input/output. T1G ST — Timer1 Gate input. SEG11 — AN LCD Analog output. RC5 ST CMOS General purpose I/O. SDO — CMOS SPI data output. SEG10 — RC6 ST CMOS General purpose I/O. CMOS USART asynchronous transmit. AN LCD Analog output. TX — CK ST CMOS USART synchronous clock. CCP3 ST CMOS Capture/Compare/PWM3. P3A — CMOS PWM output. SEG9 — RC7 ST AN LCD Analog output. CMOS General purpose I/O. RX ST DT ST CMOS USART synchronous data. CMOS PWM output. P3B — SEG8 — RD0 ST CPS8 AN — AN USART asynchronous input. LCD Analog output. CMOS General purpose I/O. — Capacitive sensing input 8. AN LCD analog output. COM3 — RD1 ST CPS9 AN CCP4 ST CMOS Capture/Compare/PWM4. CMOS General purpose I/O. CMOS General purpose I/O. — Capacitive sensing input 9. RD2 ST CPS10 AN P2B — CMOS PWM output. RD3 ST CMOS General purpose I/O. CPS11 AN P2C — SEG16 — RD4 ST CPS12 AN P2D — SEG17 — RD5 ST CPS13 AN P1D — SEG18 — — — Capacitive sensing input 10. Capacitive sensing input 11. CMOS PWM output. AN LCD analog output. CMOS General purpose I/O. — Capacitive sensing input 12. CMOS PWM output. AN LCD analog output. CMOS General purpose I/O. — Capacitive sensing input 13. CMOS PWM output. AN LCD analog output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. 3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only. 4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only DS41364A-page 18 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED) Name RD6(4)/CPS14/P1C/SEG19 RD7(4)/CPS15/P1D/SEG20 RE0(5)/AN5/P3A(1)/CCP3(1)/ SEG21 RE1 RE2 (5) /AN6/P3B/SEG22 (5) /AN7/CCP5/SEG23 Function Input Type RD6 ST CPS14 AN P1C — SEG19 — RD7 ST CPS15 AN P1D — Output Type Description CMOS General purpose I/O. — Capacitive sensing input 14. CMOS PWM output. AN LCD analog output. CMOS General purpose I/O. — Capacitive sensing input 15. CMOS PWM output. SEG20 — RE0 ST AN5 AN P3A — CMOS PWM output. CCP3 ST CMOS Capture/Compare/PWM3. SEG21 — RE1 ST AN6 AN P3B — SEG22 — AN LCD analog output. CMOS General purpose I/O. — AN A/D Channel 5 input. LCD analog output. CMOS General purpose I/O. — A/D Channel 6 input. CMOS PWM output. AN LCD analog output. RE2 ST AN7 AN CMOS General purpose I/O. CCP5 ST SEG23 — AN LCD analog output. General purpose input. — A/D Channel 7 input. CMOS Capture/Compare/PWM5. RE3 TTL — MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. RE3/MCLR/VPP Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. 3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only. 4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only © 2008 Microchip Technology Inc. Preliminary DS41364A-page 19 PIC16F193X/LF193X NOTES: DS41364A-page 20 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. Table 2-1 shows the memory sizes implemented for the PIC16F193X/LF193X device family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 2-1, 2-2 and 2-3). TABLE 2-1: DEVICE SIZES AND ADDRESSES Device Program Memory Space (Words) Last Program Memory Address PIC16F1933/PIC16LF1933 4,096 0FFFh PIC16F1934/PIC16LF1934 4,096 0FFFh PIC16F1936/PIC16LF1936 8,192 1FFFh PIC16F1937/PIC16LF1937 8,192 1FFFh PIC16F1938/PIC16LF1938 16,384 3FFFh PIC16F1939/PIC16LF1939 16,384 3FFFh © 2008 Microchip Technology Inc. Preliminary DS41364A-page 21 PIC16F193X/LF193X FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F1933/PIC16LF1933/ PIC16F1934/PIC16LF1934 FIGURE 2-2: PC<14:0> CALL, CALLW RETURN, RETLW INTERRUPT, RETFIE On-chip Program Memory PROGRAM MEMORY MAP AND STACK FOR THE PIC16F1936/PIC16LF1936/ PIC16F1937/PIC16LF1937 PC<14:0> 15 CALL, CALLW RETURN, RETLW INTERRUPT, RETFIE 15 Stack Level 0 Stack Level 1 Stack Level 0 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h Page 0 Page 0 07FFh 0800h 07FFh 0800h Page 1 Rollover to Page 0 0FFFh 1000h On-chip Program Memory Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 Rollover to Page 0 Rollover to Page 1 DS41364A-page 22 Rollover to Page 3 7FFFh Preliminary 1FFFh 2000h 7FFFh © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 2-3: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F1938/PIC16LF1938/ PIC16F1939/PIC16LF1939 PC<14:0> 2.1.1 There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 2.1.1.1 CALL, CALLW 15 RETURN, RETLW INTERRUPT, RETFIE Stack Level 0 Stack Level 1 READING PROGRAM MEMORY AS DATA RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 2-1. EXAMPLE 2-1: constants brw retlw retlw retlw retlw Stack Level 15 On-chip Program Memory Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 Page 4 Page 7 Rollover to Page 0 Rollover to Page 7 1FFFh 2000h 3FFFh 4000h RETLW INSTRUCTION DATA1 DATA2 DATA3 DATA4 my_function ;… LOTS OF CODE… movlw DATA_INDEX call constants ;… THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 2.1.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 2-2 demonstrates accessing the program memory via an FSR. 7FFFh EXAMPLE 2-2: ACCESSING PROGRAM MEMORY VIA FSR bsf FSR1H,7 moviw 0[INDF1] ;THE PROGRAM MEMORY IS IN W © 2008 Microchip Technology Inc. Preliminary DS41364A-page 23 PIC16F193X/LF193X 2.2 Data Memory Organization The data memory is partitioned in up to 32 memory banks with up to 128 bytes in a bank. Each bank consists of 12 core registers, 20 Special Function Registers (SFR), 16 common registers, and up to 80 bytes of General Purpose Registers (GPR). The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All banks contain the core SFRs and common registers. Unimplemented SFRs or GPRs will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 2.5 “Indirect Addressing, INDF and FSR Registers” for more information. 2.2.1 GENERAL PURPOSE REGISTER FILE The general purpose register file is an 8-bit RAM memory for use by your application. There are up to 80 bytes of GPR in each data memory bank. 2.2.2 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in the following sections. The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. DS41364A-page 24 Preliminary © 2008 Microchip Technology Inc. PIC16F1933/1934 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB PORTC 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB TRISC 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB LATC 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB — 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 00Fh PORTD(1) 08Fh TRISD(1) 10Fh LATD(1) 18Fh ANSELD(1) (1) BANK 5 BANK 6 BANK 7 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — WPUB — 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — Preliminary © 2008 Microchip Technology Inc. 20Fh — 28Fh — 30Fh — 38Fh — 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh PORTE PIR1 PIR2 PIR3 — TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON — CPSCON0 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh TRISE PIE1 PIE2 PIE3 — OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 — APFCON — 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh ANSELE(1) EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 — — RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 — — — — — — — 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh — CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON — CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh — CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON — CCPR4L CCPR4H CCP4CON — CCPR5L CCPR5H CCP5CON 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh — — — — IOCBP IOCBN IOCBF — — — — — — — — 01Fh 020h CPSCON1 09Fh 0A0h — 11Fh 120h — 19Fh 1A0h BAUDCTR 21Fh 220h — 29Fh 2A0h CCPTMRS1 31Fh 320h — 39Fh 3A0h — 06Fh 070h General Purpose Register 96 Bytes General Purpose Register 80 Bytes 0EFh 0F0h 16Fh 170h Accesses 70h – 7Fh 07Fh Legend: Note 1: General Purpose Register 80 Bytes Unimplemented Read as ‘0’ 1EFh 1F0h Accesses 70h – 7Fh 0FFh 17Fh = Unimplemented data memory locations, read as ‘0’. Unimplemented Read as ‘0’ 26Fh 270h Accesses 70h – 7Fh 1FFh Not available on PIC16F1933/1936/1938/PIC16LF1933/1936/1938. Unimplemented Read as ‘0’ 27Fh 36Fh 370h 2EFh 2F0h Accesses 70h – 7Fh Unimplemented Read as ‘0’ Accesses 70h – 7Fh 2FFh Unimplemented Read as ‘0’ 3EFh 3F0h Accesses 70h – 7Fh 37Fh Accesses 70h – 7Fh 3FFh PIC16F193X/LF193X DS41364A-page 25 TABLE 2-2: PIC16F1933/1934 MEMORY MAP, BANKS 8-15 BANK 8 Preliminary 400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — TMR4 PR4 T4CON — — — — TMR6 PR6 T6CON — BANK 9 480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h © 2008 Microchip Technology Inc. Unimplemented Read as ‘0’ 46Fh 470h Legend: BANK 10 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h Unimplemented Read as ‘0’ 4EFh 4F0h Accesses 70h – 7Fh 47Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 11 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h Unimplemented Read as ‘0’ 56Fh 570h Accesses 70h – 7Fh 4FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Unimplemented Read as ‘0’ 5EFh 5F0h Accesses 70h – 7Fh 57Fh = Unimplemented data memory locations, read as ‘0’. BANK 12 600h 601h 602h 603h 604h 605h 606h 607h 608h 609h 60Ah 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h BANK 13 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h Unimplemented Read as ‘0’ 66Fh 670h Accesses 70h – 7Fh 5FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 14 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h Unimplemented Read as ‘0’ 6EFh 6F0h Accesses 70h – 7Fh 67Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 15 INDF0 780h INDF1 781h PCL 782h STATUS 783h FSR0L 784h FSR0H 785h FSR1L 786h FSR1H 787h BSR 788h WREG 789h PCLATH 78Ah INTCON 78Bh — 78Ch — 78Dh — 78Eh — 78Fh — 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah See Table 2-10 or 79Bh Table 2-11 79Ch 79Dh 79Eh 79Fh 7A0h Unimplemented Read as ‘0’ 76Fh 770h Accesses 70h – 7Fh 6FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — 7EFh 7F0h Accesses 70h – 7Fh 77Fh Accesses 70h – 7Fh 7FFh PIC16F193X/LF193X DS41364A-page 26 TABLE 2-3: PIC16F1936/1937 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB PORTC 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB TRISC 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB LATC 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB — 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 00Fh PORTD(1) 08Fh TRISD(1) 10Fh LATD(1) 18Fh ANSELD(1) (1) BANK 5 BANK 6 BANK 7 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — WPUB — 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — Preliminary © 2008 Microchip Technology Inc. 20Fh — 28Fh — 30Fh — 38Fh — 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh PORTE PIR1 PIR2 PIR3 — TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 TxCON — CPSCON0 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh TRISE PIE1 PIE2 PIE3 — OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 — APFCON — 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh ANSELE(1) EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 — — RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 — — — — — — — 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh — CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON — CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh — CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON — CCPR4L CCPR4H CCP4CON — CCPR5L CCPR5H CCP5CON 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh — — — — IOCBP IOCBN IOCBF — — — — — — — — 01Fh 020h CPSCON1 09Fh 0A0h — 11Fh 120h — 19Fh 1A0h BAUDCON 21Fh 220h — 29Fh 2A0h CCPTMRS1 31Fh — 39Fh 320h General Purpose 3A0h Register 16 Bytes 32Fh 06Fh 070h General Purpose Register 96 Bytes General Purpose Register 80 Bytes 0EFh 0F0h 16Fh 170h Accesses 70h – 7Fh 07Fh Legend: Note 1: General Purpose Register 80 Bytes General Purpose Register 80 Bytes 1EFh 1F0h Accesses 70h – 7Fh 0FFh 17Fh = Unimplemented data memory locations, read as ‘0’. General Purpose Register 80 Bytes 26Fh 270h Accesses 70h – 7Fh 1FFh Not available on PIC16F1933/1936/1938/PIC16LF1933/1936/1938. General Purpose Register 80 Bytes 27Fh Accesses 70h – 7Fh 2FFh 3EFh 3F0h Accesses 70h – 7Fh 37Fh Unimplemented Read as ‘0’ Unimplemented Read as ‘0’ 36Fh 370h 2EFh 2F0h Accesses 70h – 7Fh 330h — Accesses 70h – 7Fh 3FFh PIC16F193X/LF193X DS41364A-page 27 TABLE 2-4: PIC16F1936/1937 MEMORY MAP, BANKS 8-15 BANK 8 Preliminary 400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — TMR4 PR4 T4CON — — — — TMR6 PR6 T6CON — BANK 9 480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h © 2008 Microchip Technology Inc. Unimplemented Read as ‘0’ 46Fh 470h Legend: BANK 10 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h Unimplemented Read as ‘0’ 4EFh 4F0h Accesses 70h – 7Fh 47Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 11 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h Unimplemented Read as ‘0’ 56Fh 570h Accesses 70h – 7Fh 4FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Unimplemented Read as ‘0’ 5EFh 5F0h Accesses 70h – 7Fh 57Fh = Unimplemented data memory locations, read as ‘0’. BANK 12 600h 601h 602h 603h 604h 605h 606h 607h 608h 609h 60Ah 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h BANK 13 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h Unimplemented Read as ‘0’ 66Fh 670h Accesses 70h – 7Fh 5FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 14 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h Unimplemented Read as ‘0’ 6EFh 6F0h Accesses 70h – 7Fh 67Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 15 INDF0 780h INDF1 781h PCL 782h STATUS 783h FSR0L 784h FSR0H 785h FSR1L 786h FSR1H 787h BSR 788h WREG 789h PCLATH 78Ah INTCON 78Bh — 78Ch — 78Dh — 78Eh — 78Fh — 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah See Table 2-10 or 79Bh Table 2-11 79Ch 79Dh 79Eh 79Fh 7A0h Unimplemented Read as ‘0’ 76Fh 770h Accesses 70h – 7Fh 6FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — 7EFh 7F0h Accesses 70h – 7Fh 77Fh Accesses 70h – 7Fh 7FFh PIC16F193X/LF193X DS41364A-page 28 TABLE 2-5: PIC16F1938/1939 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB PORTC 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB TRISC 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB LATC 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB — 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 00Fh PORTD(1) 08Fh TRISD(1) 10Fh LATD(1) 18Fh ANSELD(1) (1) BANK 5 BANK 6 BANK 7 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — WPUB — 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — Preliminary © 2008 Microchip Technology Inc. 20Fh — 28Fh — 30Fh — 38Fh — 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh PORTE PIR1 PIR2 PIR3 — TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON — CPSCON0 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh TRISE PIE1 PIE2 PIE3 — OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 — APFCON — 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh ANSELE(1) EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 — — RC1REG TX1REG SPBRGL1 SPBRGH1 RCSTA1 TXSTA1 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 — — — — — — — 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh — CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON — CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh — CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON — CCPR4L CCPR4H CCP4CON — CCPR5L CCPR5H CCP5CON 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh — — — — IOCBP IOCBN IOCBF — — — — — — — — 01Fh 020h CPSCON1 09Fh 0A0h — 11Fh 120h — 19Fh 1A0h BAUDCTL1 21Fh 220h — 29Fh 2A0h CCPTMRS1 31Fh 320h — 39Fh 3A0h — 06Fh 070h General Purpose Register 96 Bytes General Purpose Register 80 Bytes 0EFh 0F0h 16Fh 170h Accesses 70h – 7Fh 07Fh Legend: Note 1: 0FFh General Purpose Register 80 Bytes General Purpose Register 80 Bytes 1EFh 1F0h Accesses 70h – 7Fh 17Fh General Purpose Register 80 Bytes 26Fh 270h Accesses 70h – 7Fh 1FFh = Unimplemented data memory locations, read as ‘0’. Not available on PIC16F1933/1936/1938/PIC16LF1933/1936/1938. General Purpose Register 80 Bytes 27Fh Accesses 70h – 7Fh 2FFh General Purpose Register 80 Bytes 36Fh 370h 2EFh 2F0h Accesses 70h – 7Fh 32Fh 330h General Purpose Register 80 Bytes 3EFh 3F0h Accesses 70h – 7Fh 37Fh Accesses 70h – 7Fh 3FFh PIC16F193X/LF193X DS41364A-page 29 TABLE 2-6: PIC16F1938/1939 MEMORY MAP, BANKS 8-15 BANK 8 Preliminary 400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — TMR4 PR4 T4CON — — — — TMR6 PR6 T6CON — BANK 9 480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h © 2008 Microchip Technology Inc. General Purpose Register 80 Bytes 46Fh 470h Legend: BANK 10 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h General Purpose Register 80 Bytes 4EFh 4F0h Accesses 70h – 7Fh 47Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 11 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h General Purpose Register 80 Bytes 56Fh 570h Accesses 70h – 7Fh 4FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — General Purpose Register 80 Bytes 5EFh 5F0h Accesses 70h – 7Fh 57Fh = Unimplemented data memory locations, read as ‘0’. BANK 12 INDF0 600h INDF1 601h PCL 602h STATUS 603h FSR0L 604h FSR0H 605h FSR1L 606h FSR1H 607h BSR 608h WREG 609h PCLATH 60Ah INTCON 60Bh — 60Ch — 60Dh — 60Eh — 60Fh — 610h — 611h — 612h — 613h — 614h — 615h — 616h — 617h — 618h — 619h — 61Ah — 61Bh — 61Ch — 61Dh — 61Eh — 61Fh 620h General Purpose Register 48 Bytes INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 14 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h Unimplemented Read as ‘0’ INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 15 INDF0 780h INDF1 781h PCL 782h STATUS 783h FSR0L 784h FSR0H 785h FSR1L 786h FSR1H 787h BSR 788h WREG 789h PCLATH 78Ah INTCON 78Bh — 78Ch — 78Dh — 78Eh — 78Fh — 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah See Table 2-10 or 79Bh Table 2-11 79Ch 79Dh 79Eh 79Fh 7A0h Unimplemented Read as ‘0’ Unimplemented Read as ‘0’ 66Fh 670h Accesses 70h – 7Fh 5FFh BANK 13 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h 6EFh 6F0h Accesses 70h – 7Fh 67Fh 76Fh 770h Accesses 70h – 7Fh 6FFh 7EFh 7F0h Accesses 70h – 7Fh 77Fh Accesses 70h – 7Fh 7FFh PIC16F193X/LF193X DS41364A-page 30 TABLE 2-7: © 2008 Microchip Technology Inc. TABLE 2-8: PIC16F193X/LF193X MEMORY MAP, BANKS 16-23 BANK 16 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 17 880h 881h 882h 883h 884h 885h 886h 887h 888h 889h 88Ah 88Bh 88Ch 88Dh 88Eh 88Fh 890h 891h 892h 893h 894h 895h 896h 897h 898h 899h 89Ah 89Bh 89Ch 89Dh 89Eh 89Fh 8A0h Unimplemented Read as ‘0’ DS41364A-page 31 86Fh 870h Legend: BANK 18 900h 901h 902h 903h 904h 905h 906h 907h 908h 909h 90Ah 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 919h 91Ah 91Bh 91Ch 91Dh 91Eh 91Fh 920h Unimplemented Read as ‘0’ 8EFh 8F0h 8FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 19 980h 981h 982h 983h 984h 985h 986h 987h 988h 989h 98Ah 98Bh 98Ch 98Dh 98Eh 98Fh 990h 991h 992h 993h 994h 995h 996h 997h 998h 999h 99Ah 99Bh 99Ch 99Dh 99Eh 99Fh 9A0h Unimplemented Read as ‘0’ INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Accesses 70h – 7Fh 97Fh = Unimplemented data memory locations, read as ‘0’. BANK 20 A00h A01h A02h A03h A04h A05h A06h A07h A08h A09h A0Ah A0Bh A0Ch A0Dh A0Eh A0Fh A10h A11h A12h A13h A14h A15h A16h A17h A18h A19h A1Ah A1Bh A1Ch A1Dh A1Eh A1Fh A20h Unimplemented Read as ‘0’ 9EFh 9F0h 96Fh 970h Accesses 70h – 7Fh Accesses 70h – 7Fh 87Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 21 A80h A81h A82h A83h A84h A85h A86h A87h A88h A89h A8Ah A8Bh A8Ch A8Dh A8Eh A8Fh A90h A91h A92h A93h A94h A95h A96h A97h A98h A99h A9Ah A9Bh A9Ch A9Dh A9Eh A9Fh AA0h Unimplemented Read as ‘0’ BANK 22 B00h B01h B02h B03h B04h B05h B06h B07h B08h B09h B0Ah B0Bh B0Ch B0Dh B0Eh B0Fh B10h B11h B12h B13h B14h B15h B16h B17h B18h B19h B1Ah B1Bh B1Ch B1Dh B1Eh B1Fh B20h Unimplemented Read as ‘0’ Accesses 70h – 7Fh A7Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — AEFh AF0h A6Fh A70h Accesses 70h – 7Fh 9FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 23 B80h B81h B82h B83h B84h B85h B86h B87h B88h B89h B8Ah B8Bh B8Ch B8Dh B8Eh B8Fh B90h B91h B92h B93h B94h B95h B96h B97h B98h B99h B9Ah B9Bh B9Ch B9Dh B9Eh B9Fh BA0h Unimplemented Read as ‘0’ Unimplemented Read as ‘0’ Accesses 70h – 7Fh B7Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BEFh BF0h B6Fh B70h Accesses 70h – 7Fh AFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Accesses 70h – 7Fh BFFh PIC16F193X/LF193X Preliminary 800h 801h 802h 803h 804h 805h 806h 807h 808h 809h 80Ah 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h PIC16F193X/LF193X MEMORY MAP, BANKS 24-31 BANK 24 Preliminary C00h C01h C02h C03h C04h C05h C06h C07h C08h C09h C0Ah C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 25 C80h C81h C82h C83h C84h C85h C86h C87h C88h C89h C8Ah C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h © 2008 Microchip Technology Inc. Unimplemented Read as ‘0’ C6Fh C70h Legend: BANK 26 D00h D01h D02h D03h D04h D05h D06h D07h D08h D09h D0Ah D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h Unimplemented Read as ‘0’ CEFh CF0h Accesses 70h – 7Fh CFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 27 D80h D81h D82h D83h D84h D85h D86h D87h D88h D89h D8Ah D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h Unimplemented Read as ‘0’ D6Fh D70h Accesses 70h – 7Fh CFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Unimplemented Read as ‘0’ DEFh DF0h Accesses 70h – 7Fh D7Fh = Unimplemented data memory locations, read as ‘0’. BANK 28 E00h E01h E02h E03h E04h E05h E06h E07h E08h E09h E0Ah E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h BANK 29 E80h E81h E82h E83h E84h E85h E86h E87h E88h E89h E8Ah E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h Unimplemented Read as ‘0’ E6Fh E70h Accesses 70h – 7Fh DFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 30 F00h F01h F02h F03h F04h F05h F06h F07h F08h F09h F0Ah F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h Unimplemented Read as ‘0’ EEFh EF0h Accesses 70h – 7Fh E7Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 31 F80h F81h F82h F83h F84h F85h F86h F87h F88h F89h F8Ah F8Bh F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h F98h F99h F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON See Table 2-12 Unimplemented Read as ‘0’ F6Fh F70h Accesses 70h – 7Fh EFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — FEFh FF0h Accesses 70h – 7Fh F7Fh Accesses 70h – 7Fh FFFh PIC16F193X/LF193X DS41364A-page 32 TABLE 2-9: PIC16F193X/LF193X TABLE 2-10: PIC16F1933/1936/1938 MEMORY MAP, BANK 15 TABLE 2-11: Bank 15 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7A1h 7A2h 7A3h 7A4h 7A5h 7A6h 7A7h 7A8h 7A9h 7AAh 7ABh 7ACh 7ADh 7AEh 7AFh 7B0h 7B1h 7B2h 7B3h 7B4h 7B5h 7B6h 7B7h 7B8h PIC16F1934/1937/1939 MEMORY MAP, BANK 15 Bank 15 LCDCON LCDPS LCDREF LCDCST LCDRL — — LCDSE0 LCDSE1 — — — — — — LCDDATA0 LCDDATA1 — LCDDATA3 LCDDATA4 — LCDDATA6 LCDDATA7 — LCDDATA9 LCDDATA10 — — — — — — — — — — — — — 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7A1h 7A2h 7A3h 7A4h 7A5h 7A6h 7A7h 7A8h 7A9h 7AAh 7ABh 7ACh 7ADh 7AEh 7AFh 7B0h 7B1h 7B2h 7B3h 7B4h 7B5h 7B6h 7B7h 7B8h LCDCON LCDPS LCDREF LCDCST LCDRL — — LCDSE0 LCDSE1 LCDSE2 — — — — — LCDDATA0 LCDDATA1 LCDDATA2 LCDDATA3 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7 LCDDATA8 LCDDATA9 LCDDATA10 LCDDATA11 — — — — — — — — — — — — Unimplemented Read as ‘0’ Unimplemented Read as ‘0’ 7EFh 7EFh Legend: Legend: = Unimplemented data memory locations, read as ‘0’. © 2008 Microchip Technology Inc. Preliminary = Unimplemented data memory locations, read as ‘0’. DS41364A-page 33 PIC16F193X/LF193X TABLE 2-12: PIC16F193X/LF193X MEMORY MAP, BANK 31 Bank 31 F8Ch Unimplemented Read as ‘0’ FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD — STKPTR TOSL TOSH = Unimplemented data memory locations, read as ‘0’. DS41364A-page 34 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 0 000h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 001h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 002h(2) PCL Program Counter (PC) Least Significant Byte 003h(2) STATUS 004h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 005h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 006h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 007h(2) FSR1H Indirect Data Memory Address 1 High Pointer 008h(2) BSR 009h(2) WREG 00Ah(1, 2) PCLATH — — — — — — TO BSR4 0000 0000 0000 0000 PD Z DC C 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 Working Register — ---1 1000 ---q quuu ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 00Bh(2) INTCON 00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu 00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 00Fh(3) PORTD PORTD Data Latch when written: PORTD pins when read 010h PORTE GIE PEIE TMR0IE — — — INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu — RE3 RE2(3) RE1(3) RE0(3) ---- xxxx ---- uuuu 011h PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 012h PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 0000 00-0 0000 00-0 013h PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — -000 0-0- -000 0-0- 014h PIR4 Unimplemented 015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 018h T1CON TMR1CS1 TMR1CS0 019h T1GCON TMR1GE 01Ah TMR2 Timer 2 Module Register 01Bh PR2 Timer 2 Period Register 01Ch T2CON — — T1GPOL — xxxx xxxx uuuu uuuu T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — T1GTM T1GSPM T1GGO/ DONE T1GVAL T1GSS1 TMR1ON 0000 00-0 uuuu uu-u T1GSS0 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 01Dh — 01Eh CPSCON0 CPSON — — — 01Fh CPSCON1 — — — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: Unimplemented © 2008 Microchip Technology Inc. — CPSRNG1 CPSRNG0 CPSOUT CPSCH3 Preliminary CPSCH2 CPSCH1 T0XCS — 0--- 0000 0--- 0000 CPSCH0 ---- 0000 ---- 0000 DS41364A-page 35 PIC16F193X/LF193X TABLE 2-13: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 1 080h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 081h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 082h(2) PCL Program Counter (PC) Least Significant Byte 083h(2) STATUS 084h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 085h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 086h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 087h(2) FSR1H Indirect Data Memory Address 1 High Pointer 088h(2) BSR 089h(2) WREG 08Ah(1, 2) PCLATH — — — — — — TO BSR4 0000 0000 0000 0000 PD Z DC C 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 Working Register — ---1 1000 ---q quuu ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 08Bh(2) INTCON 08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111 08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111 08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111 08Fh(3) TRISD PORTD Data Direction Register 090h TRISE GIE PEIE TMR0IE — — — INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 1111 1111 1111 1111 — TRISE3 TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111 ---- 1111 091h PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 092h PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 0000 00-0 0000 00-0 093h PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — -000 0-0- -000 0-0- 094h — 095h OPTION_REG WPUEN INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 096h PCON STKOVF STKUNF — — RMCLR RI POR BOR 00-- 11qq qq-- qquu 097h WDTCON — — WDTPS4 WDTPS3 WDTPS2 WDTPS1 098h OSCTUNE — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 099h OSCCON SPLLEN IRCF3 IRCF2 IRCF1 IRCF0 — SCS1 SCS0 0011 1-00 0011 1-00 09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFR 00q0 0q0- qqqq qq0- 09Bh ADRESL A/D Result Register Low 09Ch ADRESH A/D Result Register High 09Dh ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 09Eh ADCON1 ADFM ADCS2 ADCS1 ADCS0 — ADNREF 09Fh — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: DS41364A-page 36 Unimplemented — — WDTPS0 SWDTEN --01 0110 --01 0110 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Unimplemented GO/DONE ADON -000 0000 -000 0000 ADPREF1 ADPREF0 0000 -000 0000 -000 — Preliminary — © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 2 100h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 102h(2) PCL Program Counter (PC) Least Significant Byte 103h(2) STATUS 104h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 105h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 106h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 107h(2) FSR1H Indirect Data Memory Address 1 High Pointer 108h(2) BSR 109h(2) WREG 10Ah(1, 2) PCLATH — — — — — — TO BSR4 0000 0000 0000 0000 PD Z DC C 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 Working Register — ---1 1000 ---q quuu ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 10Bh(2) INTCON 10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu 10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu 10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu 10Fh(3) LATD PORTD Data Latch 110h LATE 111h CM1CON0 C1ON C1OUT 112h CM1CON1 C1INTP C1INTN 113h CM2CON0 C2ON C2OUT 114h CM2CON1 C2INTP 115h CMOUT — GIE PEIE TMR0IE INTE IOCIE TMR0IF LATE3 LATE2(3) C1OE C1POL — C1PCH1 C1PCH0 — C2OE C2POL C2INTN C2PCH1 — — — IOCIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu — — INTF — LATE1(3) LATE0(3) ---- -xxx ---- -uuu C1SP C1HYS C1SYNC 0000 -100 0000 -100 — C1NCH1 C1NCH0 0000 --00 0000 --00 — C2SP C2HYS C2SYNC 0000 -100 0000 -100 C2PCH0 — — C2NCH1 C2NCH0 0000 --00 0000 --00 — — — MC2OUT MC1OUT ---- --00 ---- --00 116h BORCON SBOREN — — — — 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 0q00 0000 0q00 0000 118h DACCON0 DACEN DACLPS DACOE --- DACPSS1 DACPSS0 --- DACNSS 000- 00-0 000- 00-0 — — BORRDY 1--- ---q u--- ---u 119h DACCON1 --- --- --- DACR4 DACR3 DACR2 DACR1 DACR0 ---0 0000 ---0 0000 11Ah SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000 11Bh SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000 T1GSEL P2BSEL SSSEL CCP2SEL -000 0000 -000 0000 11Ch — 11Dh APFCON 11Eh — Unimplemented — — 11Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: Unimplemented — © 2008 Microchip Technology Inc. CCP3SEL — SRNQSEL C2OUTSEL Preliminary — DS41364A-page 37 PIC16F193X/LF193X TABLE 2-13: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 3 180h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 181h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 182h(2) PCL Program Counter (PC) Least Significant Byte 183h(2) STATUS 184h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 185h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 186h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 187h(2) FSR1H Indirect Data Memory Address 1 High Pointer 188h(2) BSR 189h(2) WREG 18Ah(1, 2) PCLATH — — — — — — TO BSR4 0000 0000 0000 0000 PD Z DC C 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 Working Register — ---1 1000 ---q quuu ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 18Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 18Ch ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 --11 1111 18Dh ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111 18Eh — 18Fh(3) ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111 — — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111 190h(3) ANSELE 191h EEADRL 192h EEADRH Unimplemented — EEPROM / Program Memory Address Register Low Byte — — 0000 0000 0000 0000 EEPROM / Program Memory Address Register High Byte -000 0000 -000 0000 193h EEDATL 194h EEDATH — — 195h EECON1 EEPGD CFGS 196h EECON2 EEPROM control register 2 197h — Unimplemented — — 198h — Unimplemented — — 199h RCREG USART Receive Data Register 19Ah TXREG USART Transmit Data Register 19Bh SPBRGL BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 19Ch SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: DS41364A-page 38 EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu EEPROM / Program Memory Read Data Register High Byte LWLO FREE WRERR WREN WR --xx xxxx --uu uuuu RD 0000 x000 0000 q000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 4 200h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 201h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 202h(2) PCL Program Counter (PC) Least Significant Byte 203h(2) STATUS 204h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 205h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 206h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 207h(2) FSR1H Indirect Data Memory Address 1 High Pointer 208h(2) BSR 209h(2) WREG 20Ah(1, 2) PCLATH — — — — — — TO BSR4 0000 0000 0000 0000 PD Z DC C 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 Working Register — ---1 1000 ---q quuu ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 20Bh(2) INTCON 20Ch — 20Dh WPUB 20Eh — Unimplemented — — 20Fh — Unimplemented — — 210h WPUE GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 Unimplemented WPUB7 — WPUB6 — — — — WPUE3 — — — — ---- 1--- ---- 1--- 211h SSPBUF 212h SSPADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 0000 0000 0000 0000 213h SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111 214h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 215h SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 216h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 218h — Unimplemented — — 219h — Unimplemented — — 21Ah — Unimplemented — — 21Bh — Unimplemented — — 21Ch — Unimplemented — — 21Dh — Unimplemented — — 21Eh — Unimplemented — — 21Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: xxxx xxxx uuuu uuuu Synchronous Serial Port Receive Buffer/Transmit Register © 2008 Microchip Technology Inc. Preliminary DS41364A-page 39 PIC16F193X/LF193X TABLE 2-13: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 5 280h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 281h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 282h(2) PCL Program Counter (PC) Least Significant Byte 283h(2) STATUS 284h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 285h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 286h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 287h(2) FSR1H Indirect Data Memory Address 1 High Pointer 288h(2) BSR 289h(2) WREG 28Ah(1, 2) PCLATH — — — — — TO — BSR4 0000 0000 0000 0000 PD Z DC C 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 Working Register — ---1 1000 ---q quuu ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 28Bh(2) INTCON 28Ch — Unimplemented — — 28Dh — Unimplemented — — 28Eh — Unimplemented — — 28Fh — Unimplemented — — 290h — Unimplemented — — 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) 293h CCP1CON 294h PWM1CON 295h CCP1AS 296h PSTR1CON 297h — Unimplemented 298h CCPR2L Capture/Compare/PWM Register 2 (LSB) 299h CCPR2H Capture/Compare/PWM Register 2 (MSB) 29Ah CCP2CON 29Bh PWM2CON 29Ch CCP2AS GIE PEIE P1M1 P1M0 P1RSEN P1DC6 CCP1ASE CCP1AS2 — — TMR0IE DC1B1 INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC1B0 CCP1M3 P1DC5 P1DC4 P1DC3 CCP1AS1 CCP1AS0 PSS1AC1 — STR1SYNC STR1D CCP1M2 CCP1M1 P1DC2 P1DC1 CCP1M0 0000 0000 0000 0000 P1DC0 0000 0000 0000 0000 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000 STR1C STR1B STR1A ---0 0001 ---0 0001 — P2M1 P2M0 P2RSEN P2DC6 CCP2ASE CCP2AS2 DC2B1 — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC2B0 CCP2M3 P2DC5 P2DC4 P2DC3 CCP2AS1 CCP2AS0 PSS2AC1 CCP2M2 CCP2M1 P2DC2 P2DC1 CCP2M0 0000 0000 0000 0000 P2DC0 0000 0000 0000 0000 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000 29Dh PSTR2CON — — — STR2SYNC STR2D 29Eh CCPTMRS0 C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 29Fh CCPTMRS1 — — — — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: DS41364A-page 40 Preliminary STR2C STR2B STR2A ---0 0001 ---0 0001 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000 — C5TSEL1 C5TSEL0 ---- --00 ---- --00 © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 6 300h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 301h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 302h(2) PCL Program Counter (PC) Least Significant Byte 303h(2) STATUS 304h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 305h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 306h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 307h(2) FSR1H Indirect Data Memory Address 1 High Pointer 308h(2) BSR 309h(2) WREG 30Ah(1, 2) PCLATH — — — — — TO — BSR4 0000 0000 0000 0000 PD Z DC C 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 Working Register — ---1 1000 ---q quuu ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 30Bh(2) INTCON 30Ch — Unimplemented — — 30Dh — Unimplemented — — 30Eh — Unimplemented — — 30Fh — Unimplemented — — 310h — Unimplemented — — 311h CCPR3L Capture/Compare/PWM Register 3 (LSB) 312h CCPR3H Capture/Compare/PWM Register 3 (MSB) 313h CCP3CON 314h PWM3CON 315h CCP3AS 316h PSTR3CON 317h — Unimplemented 318h CCPR4L Capture/Compare/PWM Register 4 (LSB) 319h CCPR4H Capture/Compare/PWM Register 4 (MSB) 31Ah CCP4CON GIE PEIE P3M1 P3M0 P3RSEN P3DC6 CCP3ASE CCP3AS2 — — — TMR0IE DC3B1 INTE DC3B0 IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP3M3 P3DC5 P3DC4 P3DC3 CCP3AS1 CCP3AS0 PSS3AC1 — STR3SYNC STR3D CCP3M2 CCP3M1 P3DC2 P3DC1 CCP3M0 0000 0000 0000 0000 P3DC0 0000 0000 0000 0000 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 0000 0000 STR3C STR3B STR3A ---0 0001 ---0 0001 — — DC4B1 DC4B0 — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 --00 0000 31Bh — Unimplemented 31Ch CCPR5L Capture/Compare/PWM Register 5 (LSB) 31Dh CCPR5H Capture/Compare/PWM Register 5 (MSB) 31Eh CCP5CON 31Fh — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: — — — DC5B1 DC5B0 xxxx xxxx uuuu uuuu CCP5M3 Unimplemented © 2008 Microchip Technology Inc. — xxxx xxxx uuuu uuuu CCP5M2 CCP5M1 CCP5M0 --00 0000 --00 0000 — Preliminary — DS41364A-page 41 PIC16F193X/LF193X TABLE 2-13: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 7 380h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 381h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 382h(2) PCL Program Counter (PC) Least Significant Byte 383h(2) STATUS 384h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 385h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 386h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 387h(2) FSR1H Indirect Data Memory Address 1 High Pointer 388h(2) BSR 389h(2) WREG 38Ah(1, 2) PCLATH — — — — — — TO BSR4 0000 0000 0000 0000 PD Z DC C 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 Working Register — ---1 1000 ---q quuu ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 38Bh(2) INTCON 38Ch — Unimplemented — — 38Dh — Unimplemented — — 38Eh — Unimplemented — — 38Fh — Unimplemented — — 390h — Unimplemented — — 391h — Unimplemented — — 392h — Unimplemented — — 393h — Unimplemented — — 394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000 395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000 396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000 397h — Unimplemented — — 398h — Unimplemented — — 399h — Unimplemented — — 39Ah — Unimplemented — — 39Bh — Unimplemented — — 39Ch — Unimplemented — — 39Dh — Unimplemented — — 39Eh — Unimplemented — — 39Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: DS41364A-page 42 GIE PEIE TMR0IE INTE IOCIE Preliminary TMR0IF INTF IOCIF 0000 000x 0000 000u © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 8 400h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 401h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 402h(2) PCL Program Counter (PC) Least Significant Byte 403h(2) STATUS 404h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 405h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 406h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 407h(2) FSR1H Indirect Data Memory Address 1 High Pointer 408h(2) BSR 409h(2) WREG 40Ah(1, 2) PCLATH — — — — — — TO BSR4 0000 0000 0000 0000 PD Z DC C 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 Working Register — ---1 1000 ---q quuu ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 40Bh(2) INTCON 40Ch — Unimplemented — — 40Dh — Unimplemented — — 40Eh — Unimplemented — — 40Fh — Unimplemented — — 410h — Unimplemented — — 411h — Unimplemented — — 412h — Unimplemented — — 413h — Unimplemented — — 414h — Unimplemented — — 415h TMR4 Timer 4 Module Register 416h PR4 Timer 4 Period Register 417h T4CON 418h — Unimplemented — — 419h — Unimplemented — — 41Ah — Unimplemented — — 41Bh — Unimplemented — — 41Ch TMR6 Timer 6 Module Register 41Dh PR6 Timer 6 Period Register 41Eh T6CON 41Fh — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: GIE — — PEIE T4OUTPS3 T6OUTPS3 TMR0IE INTE IOCIE INTF IOCIF 0000 000x 0000 000u 0000 0000 0000 0000 1111 1111 1111 1111 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000 0000 0000 0000 0000 1111 1111 1111 1111 T6OUTPS2 T6OUTPS1 T6OUTPS0 Unimplemented © 2008 Microchip Technology Inc. TMR0IF TMR6ON T6CKPS1 T6CKPS0 -000 0000 -000 0000 — Preliminary — DS41364A-page 43 PIC16F193X/LF193X TABLE 2-13: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Banks 9-14 x00h/ x80h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x00h/ x81h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x02h/ x82h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x03h/ x83h(2) STATUS x04h/ x84h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h/ x85h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h/ x86h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h/ x87h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x08h/ x88h(2) BSR x09h/ x89h(2) WREG x0Ah/ PCLATH x8Ah(1),(2) — — — — — — TO BSR4 PD Z BSR3 BSR2 DC BSR1 C BSR0 Working Register — ---1 1000 ---q quuu ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 x0Bh/ x8Bh(2) INTCON x0Ch/ x8Ch — x1Fh/ x9Fh — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: DS41364A-page 44 GIE PEIE TMR0IE INTE IOCIE Unimplemented TMR0IF INTF IOCIF 0000 000x 0000 000u — Preliminary — © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 15 780h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 781h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 782h(2) PCL Program Counter (PC) Least Significant Byte 783h(2) STATUS 784h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 785h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 786h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 787h(2) FSR1H Indirect Data Memory Address 1 High Pointer 788h(2) BSR 789h(2) WREG 78Ah(1, 2) PCLATH — — — — — — TO BSR4 0000 0000 0000 0000 PD Z DC C 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 Working Register — ---1 1000 ---q quuu ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 78Bh(2) INTCON 78Ch — Unimplemented — — 78Dh — Unimplemented — — 78Eh — Unimplemented — — 78Fh — Unimplemented — — 790h — Unimplemented — — 791h LCDCON 792h LCDPS 793h LCDREF 794h LCDCST 795h LCDRL 796h — Unimplemented — — 797h — Unimplemented — — 798h LCDSE0 GIE PEIE LCDEN SLPEN WFT LCDIRE TMR0IE INTE IOCIE WERR — BIASMD LCDA WA LP3 LCDIRS LCDIRI — VLCD3PE — — — — — LRLAP1 LRLAP0 LRLBP1 LRLBP0 — SE7 SE6 SE5 SE4 CS1 SE3 TMR0IF INTF IOCIF 0000 000x 0000 000u CS0 LMUX1 LMUX0 000- 0011 000- 0011 LP2 LP1 LP0 0000 0000 0000 0000 — 000- 000- 000- 000- VLCD2PE VLCD1PE LCDCST2 LCDCST1 LCDCST0 ---- -000 ---- -000 LRLAT2 SE2 LRLAT1 SE1 LRLAT0 0000 -000 0000 -000 SE0 0000 0000 uuuu uuuu 799h LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu 79Ah LCDSE2(3) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu 79Bh — Unimplemented — — 79Ch — Unimplemented — — 79Dh — Unimplemented — — 79Eh — Unimplemented — — 79Fh — Unimplemented — — 7A0h LCDDATA0 SEG7 COM0 SEG6 COM0 SEG5 COM0 SEG4 COM0 SEG3 COM0 SEG2 COM0 SEG1 COM0 SEG0 COM0 xxxx xxxx uuuu uuuu 7A1h LCDDATA1 SEG15 COM0 SEG14 COM0 SEG13 COM0 SEG12 COM0 SEG11 COM0 SEG10 COM0 SEG9 COM0 SEG8 COM0 xxxx xxxx uuuu uuuu 7A2h LCDDATA2(3) SEG23 COM0 SEG22 COM0 SEG21 COM0 SEG20 COM0 SEG19 COM0 SEG18 COM0 SEG17 COM0 SEG16 COM0 xxxx xxxx uuuu uuuu 7A3h LCDDATA3 SEG7 COM1 SEG6 COM1 SEG5 COM1 SEG4 COM1 SEG3 COM1 SEG2 COM1 SEG1 COM1 SEG0 COM1 xxxx xxxx uuuu uuuu 7A4h LCDDATA4 SEG15 COM1 SEG14 COM1 SEG13 COM1 SEG12 COM1 SEG11 COM1 SEG10 COM1 SEG9 COM1 SEG8 COM1 xxxx xxxx uuuu uuuu 7A5h LCDDATA5(3) SEG23 COM1 SEG22 COM1 SEG21 COM1 SEG20 COM1 SEG19 COM1 SEG18 COM1 SEG17 COM1 SEG16 COM1 xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: © 2008 Microchip Technology Inc. Preliminary DS41364A-page 45 PIC16F193X/LF193X TABLE 2-13: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 15 (Continued) 7A6h LCDDATA6 SEG7 COM2 SEG6 COM2 SEG5 COM2 SEG4 COM2 SEG3 COM2 SEG2 COM2 SEG1 COM2 SEG0 COM2 xxxx xxxx uuuu uuuu 7A7h LCDDATA7 SEG15 COM2 SEG14 COM2 SEG13 COM2 SEG12 COM2 SEG11 COM2 SEG10 COM2 SEG9 COM2 SEG8 COM2 xxxx xxxx uuuu uuuu 7A8h LCDDATA8(3) SEG23 COM2 SEG22 COM2 SEG21 COM2 SEG20 COM2 SEG19 COM2 SEG18 COM2 SEG17 COM2 SEG16 COM2 xxxx xxxx uuuu uuuu 7A9h LCDDATA9 SEG7 COM3 SEG6 COM3 SEG5 COM3 SEG4 COM3 SEG3 COM3 SEG2 COM3 SEG1 COM3 SEG0 COM3 xxxx xxxx uuuu uuuu 7AAh LCDDATA10 SEG15 COM3 SEG14 COM3 SEG13 COM3 SEG12 COM3 SEG11 COM3 SEG10 COM3 SEG9 COM3 SEG8 COM3 xxxx xxxx uuuu uuuu 7ABh LCDDATA11(3) SEG23 COM3 SEG22 COM3 SEG21 COM3 SEG20 COM3 SEG19 COM3 SEG18 COM3 SEG17 COM3 SEG16 COM3 xxxx xxxx uuuu uuuu 7ACh — 7EFh — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: DS41364A-page 46 Unimplemented — Preliminary — © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Banks 16-30 x00h/ x80h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x00h/ x81h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x02h/ x82h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x03h/ x83h(2) STATUS x04h/ x84h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h/ x85h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h/ x86h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h/ x87h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x08h/ x88h(2) BSR x09h/ x89h(2) WREG x0Ah/ PCLATH x8Ah(1),(2) — — — — — — TO BSR4 PD Z BSR3 BSR2 DC BSR1 C BSR0 Working Register — ---1 1000 ---q quuu ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 x0Bh/ x8Bh(2) INTCON x0Ch/ x8Ch — x1Fh/ x9Fh — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: GIE PEIE TMR0IE INTE IOCIE Unimplemented © 2008 Microchip Technology Inc. TMR0IF INTF IOCIF 0000 000x 0000 000u — Preliminary — DS41364A-page 47 PIC16F193X/LF193X TABLE 2-13: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 31 F80h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F81h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F82h(2) PCL Program Counter (PC) Least Significant Byte F83h(2) STATUS F84h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu F85h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 F86h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu F87h(2) FSR1H Indirect Data Memory Address 1 High Pointer F88h(2) BSR F89h(2) WREG F8Ah(1),(2 PCLATH ) F8Bh(2) INTCON F8Ch — FE3h — FE4h — — — — — — TO BSR4 0000 0000 0000 0000 PD Z DC C 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 Working Register — GIE ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE ---1 1000 ---q quuu TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF Unimplemented 0000 000x 0000 000u — Z STATUS_ DC C — ---- -xxx ---- -uuu SHAD FE5h WREG_ Working Register Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu SHAD FE6h BSR_ Bank Select Register Normal (Non-ICD) Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ Program Counter Latch High Register Normal (Non-ICD) Shadow -xxx xxxx uuuu uuuu SHAD FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu SHAD FE9h FSR0H_ SHAD FEAh FSR1L_ SHAD FEBh FSR1H_ SHAD FECh — Unimplemented — — FEDh STKPTR FEEh TOSL FEFh TOSH Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. Note 1: 2: 3: DS41364A-page 48 — — — Current Stack pointer Top of Stack Low byte — ---1 1111 ---1 1111 xxxx xxxx uuuu uuuu Top of Stack High byte -xxx xxxx -uuu uuuu Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 2.2.3 CORE REGISTERS The core registers contain the registers that directly affect the basic operation of the PIC16F193X/LF193X. These registers are listed below: • • • • • • • • • • • • INDF0 INDF1 PCL STATUS FSR0 Low FSR0 High FSR1 Low FSR1 High BSR WREG PCLATH INTCON Note: The core registers are the first 12 addresses of every data memory bank. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 49 PIC16F193X/LF193X 2.2.3.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 2-1: U-0 It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 26.0 “Instruction Set Summary”). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. STATUS: STATUS REGISTER U-0 — For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). — U-0 R-1/q — TO R-1/q PD R/W-x/x R/W-x/x R/W-x/x Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. DS41364A-page 50 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 2.2.3.2 OPTION register The OPTION register, shown in Register 2-2, is a readable and writable register, which contains various control bits to configure: • External INT interrupt • Timer0 • Weak pull-ups REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is inactive and has no effect on the Timer0 interrupt rate 0 = Prescaler is active and affects the Timer0 interrupt rate bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 © 2008 Microchip Technology Inc. Preliminary DS41364A-page 51 PIC16F193X/LF193X 2.3 2.3.3 PCL and PCLATH COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-4 shows the five situations for the loading of the PC. A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). FIGURE 2-4: If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>. LOADING OF PC IN DIFFERENT SITUATIONS 14 PCH 6 7 PCL 0 PC Instruction with PCL as Destination 8 0 ALU Result PCLATH 14 PCH PCL 0 PC GOTO, CALL 6 4 0 PCLATH 14 11 PCH PCL 0 CALLW 6 7 0 8 W PCLATH 14 PCH PCL BRW If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction. 15 PC + W 14 PCH PCL PC 2.4 0 BRA 15 PC + OPCODE <8:0> 2.3.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. 2.3.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556). DS41364A-page 52 BRANCHING If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. 0 PC 2.3.4 The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. OPCODE <10:0> PC The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. Stack All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 2-1 and 2-3). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer, if the STVREN bit = 0 (Configuration Word 2). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). Note 1: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 2.4.1 ACCESSING THE STACK 2.5 The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow. During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETURN and RETFIE will decrement STKPTR. At any time STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will write the PC and then increment the STKPTR, and a return will decrement the PC and then unload the PC. 2.4.2 Indirect Addressing, INDF and FSR Registers The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Word 2 is programmed, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 53 PIC16F193X/LF193X FIGURE 2-5: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: DS41364A-page 54 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 2.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 2-6: TRADITIONAL DATA MEMORY MAP Direct Addressing 4 BSR 0 6 Indirect Addressing From Opcode 7 0 0 Bank Select Location Select 0000 FSRxH 0 0 0 7 FSRxL 0 0 Bank Select 0001 0010 Location Select 1111 0x00 0x7F Bank 0 Bank 1 Bank 2 © 2008 Microchip Technology Inc. Preliminary Bank 31 DS41364A-page 55 PIC16F193X/LF193X 2.5.2 2.5.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. FIGURE 2-7: 7 FSRnH 0 0 1 LINEAR DATA MEMORY MAP 0 7 FSRnL To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower 8 bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 2-8: 7 1 0 PROGRAM FLASH MEMORY FSRnH PROGRAM FLASH MEMORY MAP 0 Location Select Location Select 0x2000 7 FSRnL 0x8000 0 0x0000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Program Flash Memory (low 8 bits) Bank 2 0x16F 0xF20 Bank 30 0x29AF DS41364A-page 56 0xFFFF 0x7FFF 0xF6F Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 3.0 RESETS The PIC16F193X/LF193X various kinds of Reset: a) b) c) d) e) f) g) differentiates between Power-on Reset (POR) WDT Reset during normal operation MCLR Reset Brown-out Reset (BOR) RESET instruction Stack Overflow Stack Underflow Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 3-6. These bits are used in software to determine the nature of the Reset. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 3-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 28.0 “Electrical Specifications” for pulse width specifications. Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” on: • • • • Power-on Reset (POR) MCLR Reset WDT Reset Brown-out Reset (BOR) FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Full/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out VDD Rise Detect POR Pulse VDD Brown-out Reset S BOR Enable OST/PWRT OST(2) 1024 Cycles Chip_Reset 10-bit Ripple Counter R Q OSC1 PWRT(2) 64 ms LFINTOSC 11-bit Ripple Counter Enable PWRT Enable OST(1) Note 1: 2: See Table 3-5 for time-out situations. PWRT and OST counters are reset by POR and BOR. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 57 PIC16F193X/LF193X TABLE 3-1: STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RMCLR RI POR BOR TO PD Condition 0 0 1 1 0 x 1 1 Power-on Reset or LDO Reset 0 0 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 0 x x 0 Illegal, PD is set on POR 0 0 1 1 u 0 1 1 Brown-out Reset u u u u u u 0 u WDT Reset u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u 1 0 Interrupt Wake-up from Sleep u u 0 u u u u u MCLR Reset during normal operation u u 0 u u u 1 0 MCLR Reset during Sleep u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 3-2: RESET CONDITION FOR SPECIAL REGISTERS(2) Program Counter STATUS Register PCON Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 ---1 0uuu uu-- uuuu ---u uuuu uu-- u0uu Condition Interrupt Wake-up from Sleep RESET Instruction Executed PC + 1 (1) 0000h Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as ‘0’. DS41364A-page 58 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 3.1 MCLR The PIC16F193X/LF193X has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a Reset does not drive the MCLR pin low. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 3-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the RE3/MCLR pin becomes an external Reset input. In this mode, the RE3/MCLR pin has a weak pull-up to VDD. In-Circuit Serial Programming is not affected by selecting the internal MCLR option. Low-voltage programming (LVP) mode will override MCLRE. For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 3.3 The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from the WDT oscillator. For more information, see Section 8.5 “Internal Clock Modes”. The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. The Power-up Timer delay will vary from chip-to-chip and vary due to: • VDD variation • Temperature variation • Process variation See DC parameters for details “Electrical Specifications”). Note: FIGURE 3-2: RECOMMENDED MCLR CIRCUIT VDD Power-up Timer (PWRT) 3.4 (Section 28.0 The Power-up Timer is enabled by the PWRTE bit in the Configuration Word. Watchdog Timer (WDT) The WDT has the following features: PIC® MCU • Independent prescaler from Timer0 • Time-out period is from 1.024 ms to 268 seconds, typical • Enabled by Configuration bits WDTE<1:0> • Can be disabled during Sleep • Controlled by WDTCON register R1 10 kΩ MCLR C1 0.1 μF WDT is cleared under certain conditions described in Table 3-3. 3.4.1 3.2 Power-on Reset (POR) The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. A maximum rise time for VDD is required. See Section 28.0 “Electrical Specifications” for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section 3.5 “Brown-Out Reset (BOR)”). WDT OSCILLATOR The WDT derives its time base from the 31 kHz internal oscillator. Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset. When the OST count has expired, the WDT will begin counting (if enabled). When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 59 PIC16F193X/LF193X 3.4.2 WDT CONTROL The WDTE<1:0> bits are located in the Configuration Word Register 1. When set to ‘11’, the WDT runs continuously. When entering Sleep the WDT is always cleared. When set to ‘10’, the WDT is enabled while running, and disabled during Sleep. When ‘01’ the WDT is under control of the SWDTEN bit, and when ‘00’ the WDT is always disabled. The WDTCON register contains the SWDTEN bit and WDTPS<4:0> bits. When the WDTE<1:0> bits in the Configuration Word 1 register are anything but ‘01’, the SWDTEN bit has no effect. When WDTE = 01, the SWDTEN bit can be used to enable and disable the WDT. Setting the bit will enable the WDT and clearing the bit will disable the WDT. The WDTPS<4:0> bits control the prescaler. See Register 3-1. The Reset value of WDTCON gives a nominal WDT interval of ~2s. Upon Reset, the SWDTEN value will leave the WDT disabled if WDTE<1:0> is ‘01’ in the Configuration Word. The prescaler will always be cleared on a Reset. FIGURE 3-3: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> = 00 LFINTOSC 23-bit Programmable Prescaler WDT WDT Time-out WDTE<1:0> = 01 SWDTEN WDTPS<4:0> WDTE<1:0> = 11 WDTE<1:0> = 10 Sleep TABLE 3-3: WDT STATUS Conditions WDT WDTE<1:0> = 00 Cleared WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) DS41364A-page 60 Unaffected Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 3-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 — — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 00000 = 1:32 (Interval 1 ms typ) 00001 = 1:64 (Interval 2 ms typ) 00010 = 1:128 (Interval 4 ms typ) 00011 = 1:256 (Interval 8 ms typ) 00100 = 1:512 (Interval 16 ms typ) 00101 = 1:1024 (Interval 32 ms typ) 00110 = 1:2048 (Interval 64 ms typ) 00111 = 1:4096 (Interval 128 ms typ) 01000 = 1:8192 (Interval 256 ms typ) 01001 = 1:16384 (Interval 512 ms typ) 01010 = 1:32768 (Interval 1s typ) 01011 = 1:65536 (Interval 2s typ) (Reset value) 01100 01101 01110 01111 10000 10001 10010 = = = = = = = 1:131072 (217) (Interval 4s typ) 1:262144 (218) (Interval 8s typ) 1:524288 (219) (Interval 16s typ) 1:1048576 (220) (Interval 32s typ) 1:2097152 (221) (Interval 64s typ) 1:4194304 (222) (Interval 128s typ) 1:8388608 (223) (Interval 256s typ) 10011 = Reserved. Results in minimum interval (1:32) • • • 11111 = Reserved. Results in minimum interval (1:32) bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 61 PIC16F193X/LF193X 3.5 Brown-Out Reset (BOR) Sleep. When BOREN = 01, the BOR is controlled by the SBOREN bit of the BORCON register. When BOREN = 00, the BOR is disabled. Brown-out Reset is enabled by programming the BOREN<1:0> bits in the Configuration register. The brown-out trip point is selectable from two trip points via the BORV bit in the Configuration register. If VDD falls below VBOR for greater than parameter (TBOR) (see Section 28.0 “Electrical Specifications”), the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not ensured to occur if VDD falls below VBOR for more than parameter (TBOR). Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. Two bits are used to enable the BOR. When BOREN = 11, the BOR is always enabled. When BOREN = 10, the BOR is enabled, but disabled during TABLE 3-4: If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 64 ms Reset. BOR OPERATING MODES BOREN Config bits SBOREN Device Mode BOR Mode Device Device Operation upon Operation upon wake- up from release of POR Sleep BOR_ON (11) X X Active Waits for BOR ready(1) BOR_NSLEEP (10) X Awake Active BOR_NSLEEP (10) X Sleep Disabled BOR_SBOREN (01) 1 X Active Begins immediately BOR_SBOREN (01) 0 X Disabled Begins immediately BOR_OFF (00) X X Disabled Begins immediately Waits for BOR ready Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in startup. FIGURE 3-4: BROWN-OUT SITUATIONS VDD Internal Reset VBOR 64 ms(1) VDD Internal Reset VBOR < 64 ms 64 ms(1) VDD VBOR Internal Reset Note 1: 64 ms(1) 64 ms delay only if PWRTE bit is programmed to ‘0’. DS41364A-page 62 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 3-2: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u U-0 U-0 U-0 U-0 U-0 U-0 R/W-q/u SBOREN — — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN ≠ 01: SBOREN is read/write, but has no effect on the BOR. If BOREN = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active and armed 0 = The Brown-out Reset circuit is disabled or is warming up © 2008 Microchip Technology Inc. Preliminary DS41364A-page 63 PIC16F193X/LF193X 3.5.1 BOR HIBERNATE/REARM The BOR circuit has an output that feeds into the POR circuit and rearms the POR within the operating range of the BOR. This early rearming of the POR ensures that the device will remain in Reset in the event that VDD falls below the operating range of the BOR circuitry. 3.6 Reset Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Table 3-6 for default conditions after a RESET instruction has occurred. 3.7 Stack Overflow/Underflow Device Resets on Stack Overflow and Stack Underflow conditions are enabled by setting the STVREN bit in Configuration Word 2. When STVREN is set, an overflow or underflow condition will set the appropriate STKOVF or STKUNF bit in the PCON register and then cause a device Reset. When STVREN is cleared, an overflow or underflow condition will set the appropriate STKOVF or STKUNF bit, but not cause a device Reset. The STKOVF or STKUNF bit is cleared by user software or a Power-on Reset. 3.8 Power-Up Time-out Sequence On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR or BOR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit = 1 (PWRT disabled), there will be no time out at all. Figure 3-5, Figure 3-6 and Figure 3-7 depict time-out sequences. Since the time outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 3-6). This is useful for testing purposes or to synchronize more than one PIC16F193X/LF193X device operating in parallel. Table 3-7 shows the Reset conditions for some special registers. DS41364A-page 64 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 3.9 Power Control (PCON) Register The Power Control (PCON) register has six Status bits to indicate what type of Reset that last occurred. 3.9.1 The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 3-3. PCON REGISTER The Power Control (PCON) register contains flag bits (refer to Table 3-6) to differentiate between a: • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) Stack Overflow Reset (STKOVF) Stack Underflow Reset (STKUVF) REGISTER 3-3: PCON: POWER CONTROL REGISTER R/W-0/q R/W-0/q U-0 U-0 R/W-1/q R/W-1/q R/W-q/u R/W-q/u STKOVF STKUNF — — RMCLR RI POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred (more CALLs than fit on the stack) 0 = A Stack Overflow has not occurred or set to ‘0’ by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred (more RETURNs than CALLs) 0 = A Stack Underflow has not occurred or set to ‘0’ by firmware bit 5-4 Unimplemented: Read as ‘0’ bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) © 2008 Microchip Technology Inc. Preliminary DS41364A-page 65 PIC16F193X/LF193X TABLE 3-5: TIME-OUT IN VARIOUS SITUATIONS Power-up and Brown-out Reset PWRTE = 0 PWRTE = 1 Wake-up from Sleep or Oscillator Switch XT, HS, LP 64 ms + 1024 • TOSC 1024 • TOSC 1024 • TOSC External RC 64 ms — — EC 64 ms — — 64 ms 1 μs 1 μs Oscillator Configuration INTOSC Note 1: LP mode with T1OSC disabled. TABLE 3-6: RESET BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RMCLR RI POR BOR TO PD Condition 0 0 1 1 0 x 1 1 Power-on Reset 0 0 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 0 x x 0 Illegal, PD is set on POR 0 0 1 u u 0 1 1 Brown-out Reset u u u u u u 0 u WDT Reset u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u 1 0 Interrupt Wake-up from Sleep u u 0 u u u u u MCLR Reset during normal operation u u 0 u u u 1 0 MCLR Reset during Sleep u u u 0 u u u u RESET instruction executed 1 u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u Stack Underflow Reset (STVREN = 1) Legend: u = unchanged, x = unknown FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset DS41364A-page 66 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 3-6: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3 FIGURE 3-7: VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset © 2008 Microchip Technology Inc. Preliminary DS41364A-page 67 PIC16F193X/LF193X RESET CONDITION FOR SPECIAL REGISTERS(2) TABLE 3-7: Program Counter STATUS Register PCON Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 ---1 0uuu uu-- uuuu Condition Interrupt Wake-up from Sleep PC + 1 (1) RESET Instruction Executed 0000h ---u uuuu uu-- u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as ‘0’. TABLE 3-8: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN — — — — — — BORRDY 63 PCON STKOVF STKUNF — — RMCLR RI POR BOR 65 STATUS — — — TO PD Z DC C 50 WDTCON — — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN 61 Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. DS41364A-page 68 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.0 INTERRUPTS The PIC16F193X/LF193X device family features an interruptible core, allowing certain events to preempt normal program flow. An Interrupt Service Routine (ISR) is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. The PIC16F193X/LF193X device family has 23 interrupt sources, differentiated by corresponding interrupt enable and flag bits: • • • • • • • • External Edge Detect on INT Pin Interrupt Interrupt-on-Change Interrupt A/D Conversion Complete Interrupt EEPROM Write Complete Interrupt EUSART Receive Interrupt EUSART Transmit Interrupt LCD Module Interrupt Oscillator Fail Interrupt FIGURE 4-1: • • • • • • • • • • • • • • • Timer0 Overflow Interrupt Timer1 Gate Interrupt Timer1 Overflow Interrupt Timer2 Match with PR2 Interrupt Timer4 Match with PR4 Interrupt Timer6 Match with PR6 Interrupt Comparator C1 Interrupt Comparator C2 Interrupt CCP1 Event Interrupt CCP2 Event Interrupt CCP3 Event Interrupt CCP4 Event Interrupt CCP5 Event Interrupt MSSP Event Interrupt MSSP Bus Collision Interrupt A block diagram of the interrupt logic is shown in Figure 4-1. INTERRUPT LOGIC Wake-up (If in Sleep mode) TMR0IF TMR0IE INTF Interrupt to CPU INTE IOCIF IOCIE From Peripheral Interrupt Logic (Figure 4-2) PEIE GIE © 2008 Microchip Technology Inc. Preliminary DS41364A-page 69 PIC16F193X/LF193X FIGURE 4-2: PERIPHERAL INTERRUPT LOGIC TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE • • • • • • CCP5IF CCP5IE OSFIF OSFIE TMR1IF TMR1IE • • • To Interrupt Logic (Figure 4-1) • • • TMR6IF TMR6IE C2IF C2IE C1IF C1IE EEIF EEIE BCLIF BCLIE LCDIF LCDIE DS41364A-page 70 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.1 Operation that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1, PIE2 and PIE3 registers) For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. The INTCON, PIR1, PIR2 and PIR3 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • PC is loaded with the interrupt vector 0004h 4.2 Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is 3 or 4 instruction cycles. For asynchronous interrupts, the latency is 3 to 5 instruction cycles, depending on when the interrupt occurs. See Figure 4-3 for timing details. The ISR determines the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt FIGURE 4-3: Interrupt Latency INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF flag (INTCON<1>) Interrupt Latency (2) (5) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Dummy Cycle 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 28.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 71 PIC16F193X/LF193X 4.3 Interrupts During Sleep 4.5 Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section 24.0 “Power-Down Mode (Sleep)” for more details. 4.4 INT Pin Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: • • • • • W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register Upon exit from the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. Depending on the user’s application, other registers may also need to be saved. The external interrupt, INT pin, causes an asynchronous, edge-triggered interrupt. The INTEDG bit of the OPTION register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. This interrupt is disabled by clearing the INTE bit of the INTCON register. DS41364A-page 72 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.5.1 INTCON REGISTER Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 4-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF(1) INTF IOCIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit(1) 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred (must be cleared in software) 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit 1 = When at least one of the interrupt-on-change pins changed state (must be cleared in software) 0 = None of the interrupt-on-change pins have changed state Note 1: TMR0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing TMR0IF bit. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 73 PIC16F193X/LF193X 4.5.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 4-2. REGISTER 4-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enable the Timer1 Gate Acquisition complete interrupt 0 = Disable the Timer1 Gate Acquisition complete interrupt bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt DS41364A-page 74 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.5.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 4-3. REGISTER 4-3: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 EEIE: EEPROM Write Completion Interrupt Enable bit 1 = Enables the EEPROM Write Completion interrupt 0 = Disables the EEPROM Write Completion interrupt bit 3 BCLIE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2 LCDIE: LCD Module Interrupt Enable bit 1 = Enables the LCD module interrupt 0 = Disables the LCD module interrupt bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt © 2008 Microchip Technology Inc. Preliminary DS41364A-page 75 PIC16F193X/LF193X 4.5.4 PIE3 REGISTER The PIE3 register contains the interrupt enable bits, as shown in Register 4-4. REGISTER 4-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 CCP5IE: CCP5 Interrupt Enable bit 1 = Enables the CCP5 interrupt 0 = Disables the CCP5 interrupt bit 5 CCP4IE: CCP4 Interrupt Enable bit 1 = Enables the CCP4 interrupt 0 = Disables the CCP4 interrupt bit 4 CCP3IE: CCP3 Interrupt Enable bit 1 = Enables the CCP3 interrupt 0 = Disables the CCP3 interrupt bit 3 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enables the TMR6 to PR6 Match interrupt 0 = Disables the TMR6 to PR6 Match interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 Match interrupt 0 = Disables the TMR4 to PR4 Match interrupt bit 0 Unimplemented: Read as ‘0’ DS41364A-page 76 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.5.5 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 4-5. REGISTER 4-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Timer1 Gate is inactive 0 = Timer1 Gate is active bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = A/D conversion complete (must be cleared in software) 0 = A/D conversion has not completed or has not been started bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is not full bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The Transmission/Reception is complete (must be cleared in software) 0 = Waiting to Transmit/Receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = A Timer2 to PR2 match occurred (must be cleared in software) 0 = No Timer2 to PR2 match occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software) 0 = The TMR1 register did not overflow © 2008 Microchip Technology Inc. Preliminary DS41364A-page 77 PIC16F193X/LF193X 4.5.6 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 4-6. REGISTER 4-6: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = No oscillator failure has been detected bit 6 C2IF: Comparator C2 Interrupt Flag 1 = An enabled edge was detected on Comparator C2 (must be cleared in software) 0 = No enabled edge was detected on Comparator C2 bit 5 C1IF: Comparator C1 Interrupt Flag 1 = An enabled edge was detected on Comparator C1 (must be cleared in software) 0 = No enabled edge was detected on Comparator C1 bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit 1 = The EEPROM Write operation has completed (must be cleared in software) 0 = The EEPROM Write operation has not completed or has not been started bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit 1 = A Bus Collision was detected (must be cleared in software) 0 = No Bus collision was detected bit 2 LCDIF: LCD Module Interrupt Flag bit 1 = The LCD module has completed displaying a frame (must be cleared in software). 0 = The LCD module has not completed displaying a frame bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode DS41364A-page 78 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.5.7 PIR3 REGISTER The PIR3 register contains the interrupt enable bits, as shown in Register 4-7. REGISTER 4-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 CCP5IF: CCP5 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 5 CCP4IF: CCP4 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 4 CCP3IF: CCP3 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 3 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit 1 = TMR6 to PR6 post-scaled match occurred (must be cleared in software) 0 = No TMR6 to PR6 match occurred bit 2 Unimplemented: Read as ‘0’ bit 1 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 post-scaled match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. Preliminary DS41364A-page 79 PIC16F193X/LF193X TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Name INTCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 INTEDG T0CS T0SE PSA PS2 PS1 PS0 51 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 74 OPTION_REG WPUEN PIE1 TMR1GIE PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 75 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 76 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 78 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 79 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts. DS41364A-page 80 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 5.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F193X devices differ from the PIC16LF193X devices due to an internal Low Dropout (LDO) voltage regulator. The PIC16F193X contain an internal LDO, while the PIC16LF193X do not. The lithography of the die allows a maximum operating voltage of 3.6V on the internal digital logic. In order to continue to support 5.0V designs, a LDO voltage regulator is integrated on the die. The LDO voltage regulator allows for the internal digital logic to operate at 3.2V, while I/O’s operate at 5.0V (VDD). The LDO voltage regulator requires an external bypass capacitor for stability. One of three pins, denoted as VCAP, can be configured for the external bypass capacitor. It is recommended that the capacitor be a ceramic cap between 0.1 to 1.0 µF. On power-up, the external capacitor will look like a large load on the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor. After the cap is fully charged, the device is released from Reset. For more information, refer to Section 28.0 “Electrical Specifications”. See Configuration Word 2 register (Register 10-2) for VCAP enable bits. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 81 PIC16F193X/LF193X NOTES: DS41364A-page 82 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.0 I/O PORTS Depending on the device selected and peripherals enabled, there are up to five ports available. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: • TRISx registers (data direction register) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. Ports with analog functions also have an ANSELx register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 6-1. FIGURE 6-1: GENERIC I/O PORT OPERATION Read LATx D Write LATx Write PORTx TRISx Q CK VDD Data Register Data Bus I/O pin Read PORTx To peripherals VSS ANSELx © 2008 Microchip Technology Inc. Preliminary DS41364A-page 83 PIC16F193X/LF193X 6.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 6-1. For this device family, the following functions can be moved between different pins. • • • • • • These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. SS (Slave Select) CCP2 CCP3 Timer1 Gate SR Latch SRNQ output Comparator C2 output REGISTER 6-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’. bit 6 CCP3SEL: CCP3 Input/Output Pin Selection bit For 28-Pin Devices (PIC16F1933/1936/1938): 0 = CCP3/P3A function is on RC6/TX/CK/CCP3/P3A/SEG9 1 = CCP3/P3A function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1 For 40-Pin Devices (PIC16F1934/1937/1939): 0 = CCP3/P3A function is on RE0/AN5/CCP3/P3A/SEG21 1 = CCP3/P3A function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1 bit 5 T1GSEL: Timer1 Gate Input Pin Selection bit 0 = T1G function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1 1 = T1G function is on RC4/SDI/SDA/T1G/SEG11 bit 4 P2BSEL: CCP2 PWM B Output Pin Selection bit For 28-Pin Devices (PIC16F1933/1936/1938): 0 = P2B function is on RC0/T1OSO/T1CKI/P2B 1 = P2B function is on RB5/AN13/P2B/CPS5/T1G/COM1 For 40-Pin Devices (PIC16F1934/1937/1939): 0 = P2B function is on RC0/T1OSO/T1CKI/P2B 1 = P2B function is on RD2/CPS10/P2B bit 3 SRNQSEL: SR Latch nQ Output Pin Selection bit 0 = SRnQ function is on RA5/AN4/C2OUT/SRnQ/SS/CPS7/SEG5/VCAP 1 = SRnQ function is on RA0/AN0/C12IN0-/C2OUT/SRnQ/SS/SEG12/VCAP bit 2 C2OUTSEL: Comparator C2 Output Pin Selection bit 0 = C2OUT function is on RA5/AN4/C2OUT/SRnQ/SS/CPS7/SEG5/VCAP 1 = C2OUT function is on RA0/AN0/C12IN0-/C2OUT/SRnQ/SS/SEG12/VCAP bit 1 SSSEL: SS Input Pin Selection bit 0 = SS function is on RA5/AN4/C2OUT/SRNQ/SS/CPS7/SEG5/VCAP 1 = SS function is on RA0/AN0/C12IN0-/C2OUT/SRNQ/SS/SEG12/VCAP bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit 0 = CCP2/P2A function is on RC1/T1OSI/CCP2/P2A 1 = CCP2/P2A function is on RB3/AN9/C12IN2-/CPS3/CCP2/P2A/VLCD3 DS41364A-page 84 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.2 PORTA Registers TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 6-4). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 6-1 shows how to initialize PORTA. Note: EXAMPLE 6-1: BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF Reading the PORTA register (Register 6-2) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). The TRISA register (Register 6-4) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the REGISTER 6-2: The ANSELA register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. PORTA PORTA LATA LATA ANSELA ANSELA TRISA 0Ch TRISA INITIALIZING PORTA ; ;Init PORTA ;Data Latch ; ; ;digital I/O ; ;Set RA<3:2> as inputs ;and set RA<7:4,1:0> ;as outputs PORTA: PORTA REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RA<7:0>: PORTA I/O Value bits(1) bit 7-0 Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 6-3: LATA: PORTA DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: LATA<7:0>: PORTA Output Latch Value bits(1) Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 85 PIC16F193X/LF193X 6.2.1 ANSELA REGISTER The ANSELA register (Register 6-5) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. REGISTER 6-4: TRISA: PORTA TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISA<7:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output REGISTER 6-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSA<5:0>: Analog Select between Analog or Digital Function on pins RA<5:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS41364A-page 86 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. RA0 1. 2. 3. 4. 5. VCAP (enabled by Configuration Word) SEG12 (LCD) SRNQ (SR Latch) C2OUT (Comparator) RA0 RA1 1. 2. SEG7 (LCD) RA1 RA2 1. 2. 3. COM2 (LCD) DACOUT (DAC) RA2 RA3 1. 2. 3. RA4 1. 2. 3. 4. 5. SEG4 (LCD) SRQ (SR Latch) C1OUT (Comparator) CCP5 (CCP), 28-pin only RA4 RA5 1. 2. 3. 4. 5. VCAP (enabled by Configuration Word) SEG5 (LCD) SRNQ (SR Latch) C2OUT (Comparator) RA5 RA6 1. 2. 3. 4. 5. VCAP (enabled by Configuration Word) OSC2 (enabled by Configuration Word) CLKOUT (enabled by Configuration Word) SEG1 (LCD) RA6 RA7 1. 2. 3. OSC1/CLKIN (enabled by Configuration Word) SEG2 (LCD) RA7 COM3 (LCD), 28-pin only SEG15 (LCD) RA3 © 2008 Microchip Technology Inc. Preliminary DS41364A-page 87 PIC16F193X/LF193X TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 137 ADCON1 ADFM ADCS2 ADCS1 ADCS0 — ADREF ADREF1 ADREF0 138 ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 86 APFCON — CCP3SEL T1GSEL P2BSEL SSSEL CCP2SEL 84 CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 148 CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 148 CPSCON0 CPSON — — — CPSCON1 — — — — CONFIG2(1) — — DACCON0 DACEN DACLPS VCAPEN1 VCAPEN0 DACOE --- SRNQSEL C2OUTSEL CPSRNG1 CPSRNG0 CPSOUT T0XCS 180 CPSCH3 CPSCH2 CPSCH1 CPSCH0 181 — — — — 128 --- DACNSS 153 DACPSS1 DACPSS0 LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 85 LCDCON LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 243 LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 247 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 247 WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 51 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 85 SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 122 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 277 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 86 OPTION_REG PORTA TRISA Legend: Note 1: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. PIC16F193X only. DS41364A-page 88 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.3 6.3.1 PORTB and TRISB Registers WEAK PULL-UPS PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 6-9). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 6-2 shows how to initialize PORTB. Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:0> enable or disable each pull-up (see Register 6-8). Each weak pull-up is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the WPUEN bit of the OPTION register. Reading the PORTB register (Register 6-6) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. All of the PORTB pins are individually configurable as an interrupt-on-change pin. Control bits IOCB<7:0> enable or disable the interrupt function for each pin. The interrupt-on-change feature is disabled on a Power-on Reset. Reference Section 7.0 “Interrupt-On-Change” for more information. 6.3.2 INTERRUPT-ON-CHANGE The TRISB register (Register 6-9) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. Example 6-2 shows how to initialize PORTB. EXAMPLE 6-2: INITIALIZING PORTB BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW PORTB PORTB ANSELB ANSELB TRISB B’11110000’ MOVWF TRISB Note: ; ;Init PORTB ;Make RB<7:0> digital ; ;Set RB<7:4> as inputs ;and RB<3:0> as outputs ; The ANSELB register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 89 PIC16F193X/LF193X REGISTER 6-6: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RB<7:0>: PORTB I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 6-7: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared LATB<7:0>: PORTB Output Latch Value bits(1) bit 7-0 Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. REGISTER 6-8: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: 2: WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. DS41364A-page 90 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.3.3 ANSELB REGISTER The ANSELB register (Register 6-10) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELB bits has no affect on digital output functions. A pin with TRIS clear and ANSELB set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. REGISTER 6-9: TRISB: PORTB TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISB<7:0>: PORTB Tri-State Control bit 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output REGISTER 6-10: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital Function on Pins RB<5:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 91 PIC16F193X/LF193X 6.3.4 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. RB0 1. 2. 3. CCP2/P2A RB3 RB4 1. 2. 3. COM0 P1D, 28-pin only RB4 RB5 COM1 P2B, 28-pin only P3A RB5 RB6 1. 2. 3. 4. P1C (ECCP1), 28-pin only RB1 RB2 1. 2. 1. 2. 1. 2. 3. 4. SEG0 (LCD) CCP4, 28-pin only RB0 RB1 1. 2. RB3 P1B (ECCP1), 28-pin only RB2 RB7 1. 2. 3. 4. TABLE 6-2: ICSPCLK (Programming) ICDCLK (enabled by Configuration Word) SEG14 (LCD) RB6 ICSPDAT (Programming) ICDDAT (enabled by Configuration Word) SEG13 (LCD) RB7 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 Bit 5 Bit 4 ADCON0 — CHS4 CHS3 CHS2 ANSELB — — ANSB5 ANSB4 Bit 3 Bit 0 Register on Page GO/DONE ADON 137 ANSB1 ANSB0 91 Bit 2 Bit 1 CHS1 CHS0 ANSB3 ANSB2 — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL 84 CCPxCON PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 184 CPSCON0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 180 CPSCON1 — — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0 181 APFCON INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 104 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 104 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 104 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 90 LCDCON LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 243 LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 247 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 247 WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 51 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 90 TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS1 T1GSS0 170 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 91 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 90 OPTION_REG PORTB T1GCON TRISB WPUB Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. DS41364A-page 92 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.4 PORTC and TRISC Registers PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 6-13). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 6-3 shows how to initialize PORTC. Reading the PORTC register (Register 6-11) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. REGISTER 6-11: The TRISC register (Register 6-13) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. EXAMPLE 6-3: BANKSEL CLRF BANKSEL MOVLW MOVWF INITIALIZING PORTC PORTC PORTC TRISC B‘00001100’ TRISC ; ;Init PORTC ; ;Set RC<3:2> as inputs ;and set RC<7:4,1:0> ;as outputs The location of the CCP2 function is controlled by the CCP2SEL bit in the APFCON register (refer to Register 6-1). PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 6-12: LATC: PORTC DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: LATC<7:0>: PORTC Output Latch Value bits(1) Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 93 PIC16F193X/LF193X REGISTER 6-13: TRISC: PORTC TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output DS41364A-page 94 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.4.1 PORTC FUNCTIONS AND OUTPUT PRIORITIES RC5 Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. RC0 1. 2. 3. T1OSO (Timer1 Oscillator) P2B (CCP) RC0 SEG10 (LCD) SDL (MSSP) RC5 RC6 1. 2. 3. 4. 5. SEG9 (LCD) TX (EUSART) CK (EUSART) P3A (CCP), 28-pin only RC6 RC7 1. 2. 3. 4. RC1 1. 2. 3. 1. 2. 3. T1OSI (Timer1 Oscillator) P2A (CCP) RC1 SEG8 (LCD) DT (EUSART) P3B (CCP), 28 pin only RC7 RC1 1. 2. 3. SEG3 (LCD) P1A (CCP) RC2 RC3 1. 2. 3. 4. SEG6 (LCD) SCL (MSSP) SCK (MSSP) RC3 RC4 1. 2. 3. SEG11 (LCD) SDA (MSSP) RC4 TABLE 6-3: Name APFCON CCPxCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 — CCP3SEL T1GSEL P2BSEL PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 SRNQSEL C2OUTSEL Register on Page Bit 1 Bit 0 SSSEL CCP2SEL 84 CCPxM1 CCPxM0 184 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 93 LCDCON LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 243 LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 247 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 247 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 93 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 223 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 277 SSPSTAT SMP CKE D/A P S R/W UA BF 276 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 169 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 222 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 94 TRISC Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 95 PIC16F193X/LF193X 6.5 PORTD and TRISD Registers PORTD(1) is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISD (Register 6-16). Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 6-4 shows how to initialize PORTD. The TRISD register (Register 6-16) controls the PORTD pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISD register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. EXAMPLE 6-4: BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF Reading the PORTD register (Register 6-14) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. INITIALIZING PORTD PORTD PORTD ANSELD ANSELD TRISD B‘00001100’ TRISD ; ;Init PORTD ;Make PORTD digital ; ;Set RD<3:2> as inputs ;and set RD<7:4,1:0> ;as outputs Note 1: PORTD is available on PIC16F1936 and PIC16F1938 only. PORTD: PORTD REGISTER(1) REGISTER 6-14: R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RD<7:0>: PORTD General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: PORTD is not implemented on PIC16F1933/1936/1938 devices, read as ‘0’. REGISTER 6-15: LATD: PORTD DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared LATD<7:0>: PORTD Output Latch Value bits(1,2) bit 7-0 Note 1: 2: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is return of actual I/O pin values. PORTD implemented on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. DS41364A-page 96 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.5.1 ANSELD REGISTER The ANSELD register (Register 6-17) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELD bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The state of the ANSELD bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode REGISTER 6-16: The ANSELD register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. TRISD: PORTD TRI-STATE REGISTER(1) R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits 1 = PORTD pin configured as an input (tri-stated) 0 = PORTD pin configured as an output Note 1: 2: TRISD is not implemented on PIC16F1933/1936/1938 devices, read as ‘0’. PORTD implemented on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. REGISTER 6-17: ANSELD: PORTD ANALOG SELECT REGISTER(2) R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ANSD<7:0>: Analog Select between Analog or Digital Function on Pins RD<7:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: 2: 3: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. ANSELD register is not implemented on the PIC16F1933/1936/1938. Read as ‘0’. PORTD implemented on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 97 PIC16F193X/LF193X 6.5.2 PORTD FUNCTIONS AND OUTPUT PRIORITIES RD4 Each PORTD pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. 1. 2. 3. RD5 When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. 1. 2. 3. RD0 RD6 1. 2. COM3 (LCD) RD0 1. 2. 3. CCP4 (CCP) RD1 RD7 RD1 1. 2. 1. 2. 3. RD2 1. 2. P2B (CCP) RD2 SEG17 (LCD) P2D (CCP) RD4 SEG18 (LCD) P1B (CCP) RD5 SEG19 (LCD) P1C (CCP) RD6 SEG20 (LCD) P1D (CCP) RD7 RD3 1. 2. 3. SEG16 (LCD) P2C (CCP) RD3 SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1) TABLE 6-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 97 CCPxCON PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CPSCON0 CPSON — — — Name ANSELD CPSCON1 CPSRNG1 CPSRNG0 CCPxM1 CCPxM0 184 CPSOUT T0XCS 180 — — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0 181 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 96 LCDCON LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 243 LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 247 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 96 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 97 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD. Note 1: These registers are not implemented on the PIC16F1933/1936/1938 devices, read as ‘0’. DS41364A-page 98 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.6 PORTE and TRISE Registers port pins are read, this value is modified and then written to the PORT data latch. RE3 reads ‘0’ when MCLRE = 1. PORTE(1) is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The exception is RE3, which is input only and its TRIS bit will always read as ‘1’. Example 6-5 shows how to initialize PORTE. Note 1: RE<2:0> and TRISE<2:0> pins are available on PIC16F1936 and PIC16F1938 only. EXAMPLE 6-5: BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF Reading the PORTE register (Register 6-18) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the REGISTER 6-18: INITIALIZING PORTE PORTE PORTE ANSELE ANSELE TRISE B‘00001100’ TRISE ; ;Init PORTE ; ;digital I/O ; ;Set RE<3:2> as inputs ;and set RE<1:0> ;as outputs PORTE: PORTE REGISTER U-0 U-0 U-0 U-0 R-x/u R/W-x/u R/W-x/u R/W-x/u — — — — RE3 RE2(1) RE1(1) RE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 RE<3:0>: PORTE I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: RE<2:0> are not implemented on the PIC16F1933/1936/1938. Read as ‘0’. REGISTER 6-19: LATE: PORTE DATA LATCH REGISTER U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — LATE3 LATE2 LATE1 LATE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 LATE<3:0>: PORTE Output Latch Value bits(1) Note 1: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is return of actual I/O pin values. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 99 PIC16F193X/LF193X REGISTER 6-20: U-0 WPUE: WEAK PULL-UP PORTE REGISTER U-0 — — U-0 — U-0 R/W-1/1 U-0 U-0 U-0 — WPUE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 WPUE: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 2-0 Note 1: 2: Unimplemented: Read as ‘0’ Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. DS41364A-page 100 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.6.1 ANSELE REGISTER The TRISE register (Register 6-21) controls the PORTE pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISE register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. The ANSELE register (Register 6-22) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELE bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. Note: The state of the ANSELE bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. REGISTER 6-21: The ANSELE register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. TRISE: PORTE TRI-STATE REGISTER U-0 U-0 U-0 U-0 R-1 R/W-1 R/W-1 R/W-1 — — — — TRISE3 TRISE2(1) TRISE1(1) TRISE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 TRISE3: RE3 Port Tri-state Control bit This bit is always ‘1’ as RE3 is an input only bit 2-0 TRISE<2:0>: RE<2:0> Tri-State Control bits(1) 1 = PORTE pin configured as an input (tri-stated) 0 = PORTE pin configured as an output Note 1: TRISE<2:0> are not implemented on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938. Read as ‘0’. REGISTER 6-22: ANSELE: PORTE ANALOG SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 — — — — — ANSE2(2) ANSE1(2) ANSE0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ANSE<2:0>: Analog Select between Analog or Digital Function on Pins RE<2:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: 2: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. ANSELE register is not implemented on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938. Read as ‘0’ © 2008 Microchip Technology Inc. Preliminary DS41364A-page 101 PIC16F193X/LF193X 6.6.2 PORTE FUNCTIONS AND OUTPUT PRIORITIES Each PORTE pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. RE0 1. 2. 3. SEG21 (LCD) CCP3/P3A (CCP) RE0 RE1 1. 2. 3. SEG22 (LCD) P3B (CCP) RE1 RE2 1. 2. 3. SEG23 (LCD) CCP5 (CCP) RE2 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 137 ANSELE — — — — — ANSE2 ANSE1 ANSE0 101 PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 184 — — — — LATE3 LATE2 LATE1 LATE0 99 LCDCON LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 243 247 Name CCPxCON LATE LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 PORTE — — — — RE3 RE2 RE1 RE0 99 TRISE — — — — TRISE3 TRISE2 TRISE1 TRISE0 101 WPUE — — — — WPUE3 — — — 100 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE. Note 1: These registers are not implemented on the PIC16F1933/1936/1938 devices, read as ‘0’. DS41364A-page 102 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 7.0 INTERRUPT-ON-CHANGE 7.4 The PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTB pin, or combination of PORTB pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features: • • • • Interrupt-on-Change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags The individual status flags, (IOCBFx bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. EXAMPLE 7-1: MOVLW XORWF ANDWF Figure 7-1 is a block diagram of the IOC module. 7.1 0xff IOCBF, W IOCBF, F Enabling the Module To allow individual PORTB pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 7.2 Clearing Interrupt Flags Individual Pin Configuration For each PORTB pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated IOCBPx bit of the IOCBP register is set. To enable a pin to detect a falling edge, the associated IOCBNx bit of the IOCBN register is set. 7.5 Operation in Sleep The Interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCBF register will be updated prior to the first instruction executed out of Sleep. A pin can be configured to detect rising and falling edges simultaneously by setting both the IOCBPx bit and the IOCBNx bit of the IOCBP and IOCBN registers, respectively. 7.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of PORTB. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCBFx bits. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 103 PIC16F193X/LF193X REGISTER 7-1: IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 7-2: IOCBN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCBN<7:0>: Interrupt-on-Change Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 7-3: IOCBF: INTERRUPT-ON-CHANGE FLAG REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCBF<7:0>: Interrupt-on-Change Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change. DS41364A-page 104 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 7-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCIE IOCBNx D IOCBFx Q From all other IOCBFx individual pin detectors CK R IOC Interrupt to CPU Core RBx IOCBPx D Q CK R Q2 Clock Cycle TABLE 7-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page 91 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 104 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 104 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 104 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 91 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupt-on-Change. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 105 PIC16F193X/LF193X NOTES: DS41364A-page 106 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) The oscillator module can be configured in one of six clock modes. 8.1 Overview 1. 2. 3. The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 8-1 illustrates a block diagram of the oscillator module. 4. 5. 6. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of three internal oscillators, with a choice of speeds selectable via software. Additional clock features include: Clock Source modes are configured by the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1). The internal clock can be generated from two internal oscillators. The HFINTOSC is a calibrated high-frequency oscillator. The MFINTOSC is a calibrated medium-frequency oscillator. The LFINTOSC is an uncalibrated low-frequency oscillator. • Selectable system clock source between external or internal via software. • Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. • Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. FIGURE 8-1: EC – External clock. LP – 32 kHz Low-Power Crystal mode. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode. HS – High Gain Crystal or Ceramic Resonator mode. RC – External Resistor-Capacitor (RC). INTOSC – Internal oscillator. SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM External Oscillator LP, XT, HS, RC, EC OSC2 Sleep 4 x PLL Sleep Oscillator Timer1 FOSC<2:0> = 100 T1OSO 31 kHz Source 500 kHz Source 16 MHz (HFINTOSC) 500 kHz (MFINTOSC) 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz MUX Internal Oscillator Block 16 MHz Source IRCF<3:0> Postscaler T1OSI T1OSCEN Enable Oscillator 31 kHz 31 kHz (LFINTOSC) © 2008 Microchip Technology Inc. T1OSC CPU and Peripherals MUX OSC1 Internal Oscillator Clock Control FOSC<2:0> SCS<1:0> Clock Source Option for other modules WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Preliminary DS41364A-page 107 PIC16F193X/LF193X 8.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 8-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: • Frequency selection bits (IRCF) • System clock select bits (SCS) • Software PLL enable bit (SPLLEN) REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0 SPLLEN IRCF3 IRCF2 IRCF1 IRCF0 — SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 000x = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 = 31 kHz LF 31.25 kHz MF 31.25 kHz HF(2) 62.5 kHz MF 125 kHz MF 250 kHz MF 500 kHz MF (default upon Reset) 125 kHz HF(2) 250 kHz HF(2) 500 kHz HF(2) 1 MHz HF 2 MHz HF 4 MHz HF 8 MHz HF 16 MHz HF bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by CONFIG1[FOSC<2:0>]. Note 1: 2: Reset state depends on state of the IESO Configuration bit. Duplicate frequency derived from HFINTOSC. DS41364A-page 108 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.3 Clock Source Modes Clock Source modes can be classified as external or internal. • External Clock modes rely on external circuitry for the clock source. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. • Internal clock sources are contained internally within the oscillator module. The oscillator module has two internal oscillators: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHZ (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bit of the OSCCON register. See Section 8.6 “Clock Switching” for additional information. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 8-1. TABLE 8-1: 8.4 External Clock Modes 8.4.1 OSCILLATOR START-UP TIMER (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 8.6.3 “Timer1 Oscillator Ready (T1OSCR) Bit”). OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay LFINTOSC(1) Oscillator Warm-up Delay (TWARM) Sleep/POR MFINTOSC(1) HFINTOSC(1) 31 kHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz Sleep/POR EC, RC(1) DC – 32 MHz 2 cycles LFINTOSC EC, RC(1) DC – 32 MHz 1 cycle of each Sleep/POR Timer1 Oscillator LP, XT, HS(1) 32 kHz-20 MHz 1024 Clock Cycles (OST) Any clock source MFINTOSC(1) HFINTOSC(1) 31.25 kHz-500 kHz 31.25 kHz-16 MHz 2 μs (approx.) Any clock source LFINTOSC(1) 31 kHz 1 cycle of each Any clock source Timer1 Oscillator 32 kHz 1024 Clock Cycles (OST) PLL inactive PLL active 16-32 MHz 2 ms (approx.) Note 1: 8.4.2 PLL inactive. EC MODE FIGURE 8-2: The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 8-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. © 2008 Microchip Technology Inc. Clock from Ext. System FOSC/4 or I/O(1) Note 1: Preliminary EXTERNAL CLOCK (EC) MODE OPERATION OSC1/CLKIN PIC® MCU OSC2/CLKOUT(1) Output depends upon CLKOUTEN bit of the Configuration Word 1. DS41364A-page 109 PIC16F193X/LF193X 8.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 8-3). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). 3: For oscillator design assistance, reference the following Microchip Applications Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 8-3 and Figure 8-4 show typical circuits for quartz crystal and ceramic resonators, respectively. FIGURE 8-3: FIGURE 8-4: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) PIC® MCU OSC1/CLKIN C1 PIC® MCU OSC1/CLKIN C1 To Internal Logic RP(3) RF(2) Sleep To Internal Logic Quartz Crystal C2 CERAMIC RESONATOR OPERATION (XT OR HS MODE) RS(1) RF(2) C2 Ceramic RS(1) Resonator Sleep Note 1: OSC2/CLKOUT Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 MΩ to 10 MΩ). DS41364A-page 110 Preliminary OSC2/CLKOUT A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 MΩ to 10 MΩ). 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.4.4 EXTERNAL RC MODE 8.5 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The oscillator module has three independent, internal oscillators that can be configured or selected as the system clock source. 1. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 8-5 shows the external RC mode connections. FIGURE 8-5: VDD 2. EXTERNAL RC MODES PIC® MCU REXT OSC1/CLKIN 3. Internal Clock CEXT OSC2/CLKOUT The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bits of the OSCCON register. See Section 8.6 “Clock Switching” for more information. Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V 3 kΩ ≤ REXT ≤ 100 kΩ, 3-5V CEXT > 20 pF, 2-5V Note 1: The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 8-3). The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 8-3). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register. VSS FOSC/4 or I/O(1) Internal Clock Modes 8.5.1 Output depends upon CLKOUTEN bit of the Configuration Word 1. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: • threshold voltage variation • component tolerances • packaging variations in capacitance INTOSC MODE The INTOSC mode configures the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1). In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The user also needs to take into account variation due to tolerance of external RC components used. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 111 PIC16F193X/LF193X 8.5.2 HFINTOSC 8.5.4 The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 8-3). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 8-1). One of nine frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 8.5.7 “Frequency Select Bits (IRCF)” for more information. The HFINTOSC is enabled by: • Configure the IRCF<3:0> bits for the desired HF frequency (see Register 8-1), and • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ The High Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running and can be utilized. The High Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value. The High Frequency Internal Oscillator Status Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. 8.5.3 MFINTOSC The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 8-3). LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 8-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 8.5.7 “Frequency Select Bits (IRCF)” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled: • Configure the IRCF<3:0> bits for the desired LF frequency (see Register 8-1), and • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ Peripherals that use the LFINTOSC are: • • • • LCD Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 8-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 8.5.7 “Frequency Select Bits (IRCF)” for more information. The MFINTOSC is enabled by: • Configure the IRCF<3:0> bits for the desired HF frequency (see Register 8-1), and • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running and can be utilized. DS41364A-page 112 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.5.5 OSCSTAT REGISTER The OSCSTAT register contains flags that represent the current status of the oscillators module. REGISTER 8-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-0/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 T1OSCR: Timer1 Oscillator Ready bit If the Timer1 oscillator is enabled (T1OSCEN = 1) 1 = Timer1 oscillator is ready and can be switched to 0 = Timer1 oscillator is not ready else Timer1 oscillator is disabled - clock source is T1CKI 1 = Timer1 oscillator is always ready bit 6 PLLR 4x PLL Ready bit 1 = 4x PLL is ready and can be switched to 0 = 4x PLL oscillator is not ready bit 5 OSTS: Oscillator Start-up Time-out Status bit 1 = Device running from the clock defined by FOSC<3:0> of the CONFIG1 register 0 = Device running from the internal oscillator (HFINTOSC, MFINTOSC or LFINTOSC) bit 4 HFIOFR: High Frequency Internal Oscillator Ready bit 1 = 16 MHz Internal Oscillator (HFINTOSC) is ready and can be switched to 0 = 16 MHz Internal Oscillator (HFINTOSC) is not ready bit 3 HFIOFL: High Frequency Internal Oscillator Status Locked bit (2% Stable) 1 = 16 MHz Internal Oscillator (HFINTOSC) is in lock 0 = 16 MHz Internal Oscillator (HFINTOSC) has not yet locked bit 2 MFIOFR: Medium Frequency Internal Oscillator (500 kHz HFINTOSC Output) Ready bit 1 = 500 kHz Internal Oscillator (MFINTOSC) is ready and can be switched to 0 = 500 kHz Internal Oscillator (MFINTOSC) is not ready bit 1 LFIOFR: Low Frequency Internal Oscillator Ready bit 1 = 31 kHz Internal Oscillator (LFINTOSC) is ready and can be switched to 0 = 31 kHz Internal Oscillator (LFINTOSC) is not ready bit 0 HFIOFS: High Frequency Internal Oscillator Stable bit (0.5% Stable) 1 = 16 MHz Internal Oscillator (HFINTOSC) is in communications stable 0 = 16 MHz Internal Oscillator (HFINTOSC) is not yet communications stable © 2008 Microchip Technology Inc. Preliminary DS41364A-page 113 PIC16F193X/LF193X 8.5.6 OSCTUNE REGISTER The HFINTOSC and MFINTOSC are factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 8-3). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. The OSCTUNE register applies the same adjustment to both the HFINTOSC and the MFINTOSC simultaneously. REGISTER 8-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<4:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 = • • • 000001 = 000000 = Oscillator module is running at the factory-calibrated frequency. 111111 = • • • 100000 = Minimum frequency DS41364A-page 114 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.5.7 FREQUENCY SELECT BITS (IRCF) The output of the 16 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 8-1). The Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register select the frequency output of the internal oscillators. One of eight frequencies can be selected via software: • • • • • • • • • 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz (Default after Reset) 250 kHz 125 kHz 31 kHz (LFINTOSC) Note: 8.5.8 When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 8-6). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. 2. 3. Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. INTERNAL OSCILLATOR CLOCK SWITCH TIMING 4. 5. 6. 7. IRCF<3:0> bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. The new clock is now active. The OSCSTAT register is updated as required. Clock switch is complete. See Figure 8-6 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 8-1. Start-up delay specifications are located in the oscillator tables of Section 28.0 “Electrical Specifications”. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 115 PIC16F193X/LF193X FIGURE 8-6: HFINTOSC/ MFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC/ MFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> ≠0 =0 System Clock HFINTOSC/ MFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC ≠0 IRCF <3:0> =0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF <3:0> =0 ≠0 System Clock DS41364A-page 116 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.6 Clock Switching 8.7 The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. 8.6.1 SYSTEM CLOCK SELECT (SCS) BIT The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals. • When the SCS bits of the OSCCON register = 00, the system clock source is determined by configuration of the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1). • When the SCS bits of the OSCCON register = 01, the system clock source is the Timer1 oscillator. • When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bit of the OSCCON register is always cleared. Note: 8.6.2 Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT The Oscillator Start-up Time-out Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1), or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. 8.6.3 Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. When the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 8.4.1 “Oscillator Start-up Timer (OST)”). The OST will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit of the OSCSTAT register is set, program execution switches to the external oscillator. 8.7.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Word Register 1) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). • SCS (of the OSCCON register) = 00. • FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1) configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: • Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or • Wake-up from Sleep. TIMER1 OSCILLATOR READY (T1OSCR) BIT The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. © 2008 Microchip Technology Inc. Two-Speed Clock Start-up Mode If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. Preliminary DS41364A-page 117 PIC16F193X/LF193X 8.7.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 8.7.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source. FIGURE 8-7: CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1), or the internal oscillator. TWO-SPEED START-UP INTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC + 1 PC System Clock DS41364A-page 118 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.8 8.8.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word Register 1 (CONFIG1). The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Timer1 Oscillator and RC). FIGURE 8-8: FSCM BLOCK DIAGRAM External Clock LFINTOSC Oscillator ÷ 64 31 kHz (~32 μs) 488 Hz (~2 ms) S Q R Q Sample Clock 8.8.1 The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device will be operating from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared. 8.8.4 Clock Monitor Latch RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. Clock Failure Detected Note: FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 8-8. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 8.8.2 FAIL-SAFE CONDITION CLEARING Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 119 PIC16F193X/LF193X FIGURE 8-9: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: TABLE 8-2: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CONFIG1(2) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 126 OSCCON SPLLEN IRCF3 IRCF2 IRCF1 IRCF0 — SCS1 SCS0 108 OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 113 OSCTUNE PIE2 PIR2 T1CON — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 114 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 75 OSFIF C2IF TMR1CS1 TMR1CS0 C1IF EEIF BCLIF LCDIF — CCP2IF 78 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 169 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word Register 1 (Register 10-1) for operation of all register bits. DS41364A-page 120 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 9.0 SR LATCH 9.2 The module consists of a single SR Latch with multiple Set and Reset inputs as well as separate latch outputs. The SR Latch module includes the following features: • • • • Programmable input selection SR Latch output is available internally/externally Separate Q and Q outputs Firmware Set and Reset 9.1 The SRQEN and SRNQEN bits of the SRCON0 register control the Q and Q latch outputs. Both of the SR latch outputs may be directly output to an I/O pin at the same time. The applicable TRIS bit of the corresponding port must be cleared to enable the port pin output driver. 9.3 Latch Operation The latch is a Set-Reset latch that does not depend on a clock source. Each of the Set and Reset inputs are active-high. The latch can be Set or Reset by CxOUT, SRI pin, or variable clock. Additionally the SRPS and the SRPR bits of the SRCON0 register may be used to Set or Reset the SR Latch, respectively. The latch is Reset-dominant, therefore, if both Set and Reset inputs are high the latch will go to the Reset state. Both the SRPS and SRPR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset operation. FIGURE 9-1: Latch Output Effects of a Reset Upon any device Reset, the SR latch is not initialized. The user’s firmware is responsible to initialize the latch output before enabling it to the output pins. SR LATCH SIMPLIFIED BLOCK DIAGRAM SRLEN SRPS Pulse Gen(2) SRQEN SRI S SRSPE SRCLK Q SRQ SRSCKE SYNCC2OUT(3) SRSC2E SYNCC1OUT(3) SRSC1E SRPR SR Latch(1) Pulse Gen(2) SRI R SRRPE SRCLK Q SRNQ SRRCKE SYNCC2OUT(3) SRRC2E SRLEN SRNQEN SYNCC1OUT(3) SRRC1E Note 1: 2: 3: If R = 1 and S = 1 simultaneously, Q = 0, Q = 1 Pulse generator causes a 1 Q-state pulse width. Name denotes the connection point at the comparator output. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 121 PIC16F193X/LF193X TABLE 9-1: SRCLK FREQUENCY TABLE SRCLK Divider FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 110 256 62.5 kHz 39.0 kHz 31.3 kHz 7.81 kHz 1.95 kHz 125 kHz 78.1 kHz 62.5 kHz 15.6 kHz 3.90 kHz 101 100 128 250 kHz 156 kHz 125 kHz 31.25 kHz 7.81 kHz 64 500 kHz 313 kHz 250 kHz 62.5 kHz 15.6 kHz 011 32 1 MHz 625 kHz 500 kHz 125 kHz 31.3 kHz 010 16 2 MHz 1.25 MHz 1 MHz 250 kHz 62.5 kHz 001 8 4 MHz 2.5 MHz 2 MHz 500 kHz 125 kHz 000 4 8 MHz 5 MHz 4 MHz 1 MHz 250 kHz REGISTER 9-1: SRCON0: SR LATCH CONTROL 0 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/S-0/0 R/S-0/0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared S = Bit is set only - bit 7 SRLEN: SR Latch Enable bit 1 = SR latch is enabled 0 = SR latch is disabled bit 6-4 SRCLK<2:0>: SR Latch Clock Divider bits 000 = Generates a 1 FOSC wide pulse every 4th FOSC cycle clock 001 = Generates a 1 FOSC wide pulse every 8th FOSC cycle clock 010 = Generates a 1 FOSC wide pulse every 16th FOSC cycle clock 011 = Generates a 1 FOSC wide pulse every 32th FOSC cycle clock 100 = Generates a 1 FOSC wide pulse every 64th FOSC cycle clock 101 = Generates a 1 FOSC wide pulse every 128th FOSC cycle clock 110 = Generates a 1 FOSC wide pulse every 256th FOSC cycle clock 111 = Generates a 1 FOSC wide pulse every 512th FOSC cycle clock bit 3 SRQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRQ pin 0 = Q is internal only If SRLEN = 0: SR latch is disabled bit 2 SRNQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRnQ pin 0 = Q is internal only If SRLEN = 0: SR latch is disabled bit 1 SRPS: Pulse Set Input of the SR Latch bit 1 = Pulse input for 1 Q-clock period 0 = Do not generate pulse. Always reads back ‘0’. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse input for 1 Q-clock period 0 = Do not generate pulse. Always reads back ‘0’. DS41364A-page 122 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 9-2: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SRI pin status sets SR Latch 0 = SRI pin status has no effect on SR Latch bit 6 SRSCKE: SR Latch Set Clock Enable bit 1 = Set input of SR latch is pulsed with SRCLK 0 = Set input of SR latch is not pulsed with SRCLK bit 5 SRSC2E: SR Latch C2 Set Enable bit 1 = C2 Comparator output sets SR Latch 0 = C2 Comparator output has no effect on SR Latch bit 4 SRSC1E: SR Latch C1 Set Enable bit 1 = C1 Comparator output sets SR Latch 0 = C1 Comparator output has no effect on SR Latch bit 3 SRRPE: SR Latch Peripheral Reset Enable bit 1 = SRI pin resets SR Latch 0 = SRI pin has no effect on SR Latch bit 2 SRRCKE: SR Latch Reset Clock Enable bit 1 = Reset input of SR latch is pulsed with SRCLK 0 = Reset input of SR latch is not pulsed with SRCLK bit 1 SRRC2E: SR Latch C2 Reset Enable bit 1 = C2 Comparator output resets SR Latch 0 = C2 Comparator output has no effect on SR Latch bit 0 SRRC1E: SR Latch C1 Reset Enable bit 1 = C1 Comparator output resets SR Latch 0 = C1 Comparator output has no effect on SR Latch © 2008 Microchip Technology Inc. Preliminary DS41364A-page 123 PIC16F193X/LF193X NOTES: DS41364A-page 124 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 10.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Word 1 and Configuration Word 2 registers, Code Protection and Device ID. 10.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 register at 8007h and Configuration Word 2 register at 8008h. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 125 PIC16F193X/LF193X REGISTER 10-1: CONFIGURATION WORD 1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 FCMEN IESO CLKOUTEN BOREN1 BOREN0 CPD CP bit 13 bit 7 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 MCLRE PWRTE WDTE1 WDTE0 FOSC2 FOSC1 FOSC0 bit 6 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit 1 = CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT 0 = CLKOUT function is enabled on RA6/CLKOUT bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the PCON register 00 = BOR disabled bit 8 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 7 CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: RE3/MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = RE3/MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = RE3/MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit.. bit 5 PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled Note 1: 2: 3: Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during an erase. The entire program memory will be erased when the code protection is turned off. DS41364A-page 126 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 10-1: bit 2-0 Note 1: 2: 3: CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode: CLKIN on RA7/OSC1/CLKIN 110 = ECM: External Clock, Medium-Power mode: CLKIN on RA7/OSC1/CLKIN 101 = ECL: External Clock, Low-Power mode: CLKIN on RA7/OSC1/CLKIN 100 = INTOSC oscillator: I/O function on RA7/OSC1/CLKIN 011 = EXTRC oscillator: RC function on RA7/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during an erase. The entire program memory will be erased when the code protection is turned off. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 127 PIC16F193X/LF193X REGISTER 10-2: CONFIGURATION WORD 2 R/P-1/1 R/P-1/1 U-1 R/P-1/1 R/P-1/1 R/P-1/1 U-1 LVP DEBUG — BORV STVREN PLLEN — bit 13 bit 7 U-1 R/P-1/1 R/P-1/1 U-1 U-1 R/P-1/1 R/P-1/1 — VCAPEN1 VCAPEN0 — — WRT1 WRT0 bit 6 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR/VPP must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger bit 11 Unimplemented: Read as ‘1’ bit 10 BORV: Brown-out Reset Voltage Selection bit 1 = Brown-out Reset voltage set to 1.9V 0 = Brown-out Reset voltage set to 2.7V bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled bit 7-6 Unimplemented: Read as ‘1’ bit 5-4 VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits(2) 00 = VCAP functionality is enabled on RA0 01 = VCAP functionality is enabled on RA5 10 = VCAP functionality is enabled on RA6 11 = No capacitor on VCAP pin bit 3-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 4 kW FLASH memory (PIC16F1933/PIC16LF1933 and PIC16F1934/PIC16LF1934 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by EECON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control 00 = 000h to FFFh write-protected, no addresses may be modified by EECON control 8 kW FLASH memory (PIC16F1936/PIC16LF1936 and PIC16F1937/PIC16LF1937 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 1FFFh may be modified by EECON control 01 = 000h to FFFh write-protected, 1000h to 1FFFh may be modified by EECON control 00 = 000h to 1FFFh write-protected, no addresses may be modified by EECON control 16 kW FLASH memory (PIC16F1938/PIC16LF1938 and PIC16F1939/PIC16LF1939 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 3FFFh may be modified by EECON control 01 = 000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by EECON control 00 = 000h to 3FFFh write-protected, no addresses may be modified by EECON control Note 1: 2: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. Reads as ‘11’ on PIC16LF193X only. DS41364A-page 128 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 10.2 Code Protection Code protection is controlled using the CP bit in Configuration Word 1. When code protection is enabled, all program memory locations (0000h-7FFFh) read as all ‘0’. Further programming is disabled for the program memory (0000h-7FFFh). Data memory is protected with its own Code-Protect bit (CPD). When data code protection is enabled (CPD = 0), all data memory locations read as ‘0’. Further programming is disabled for the data memory. Data memory can still be programmed and read during program execution. The user ID locations and Configuration Words can be programmed and read out regardless of the code protection settings. 10.3 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are reported when using MPLAB® IDE. See the “PIC16193X/PIC16LF193X Memory Programming Specification” (DS41360A) for more information. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 129 PIC16F193X/LF193X NOTES: DS41364A-page 130 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 11.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result register (ADRES). Figure 11-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. FIGURE 11-1: ADC BLOCK DIAGRAM ADNREF = 1 VREF- ADNREF = 0 AVDD AVSS ADPREF = 0X ADPREF = 11 VREF+ AN0 00000 AN1 00001 AN2 00010 AN3 00011 AN4 00100 AN5 00101 AN6 00110 AN7 00111 AN8 01000 AN9 01001 AN10 01010 AN11 01011 AN12 01100 AN13 01101 Temp Sens 11101 DAC(2) 11110 FVR Buffer1 11111 ADPREF = 10 ADC 10 GO/DONE ADFM 0 = Left Justify 1 = Right Justify 16 ADON VSS ADRESH ADRESL CHS<4:0> Note 1: 2: When ADON = 0, all multiplexer inputs are disconnected. See Section 10.0 “Fixed Voltage Reference” for more information. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 131 PIC16F193X/LF193X 11.1 11.1.4 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 11.1.1 The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 6.0 “I/O Ports” for more information. Note: 11.1.2 The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: • • • • • • • PORT CONFIGURATION Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 11-2. For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 28.0 “Electrical Specifications” for more information. Table 11-1 gives examples of appropriate ADC clock selections. Note: CHANNEL SELECTION CONVERSION CLOCK The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. When changing channels, a delay is required before starting the next conversion. Refer to Section 11.2 “ADC Operation” for more information. 11.1.3 ADC VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: • VREF+ • AVDD • FVR (Fixed Voltage Reference) The ADNREF bits of the ADCON1 register provides control of the negative voltage reference. The negative voltage reference can be: • VREF• AVSS See Section 14.0 “Fixed Voltage Reference” for more details on the fixed voltage reference. DS41364A-page 132 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 11-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES Device Frequency (FOSC) Device Frequency (FOSC) ADC Clock Period (TAD) ADC Clock Source ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 μs Fosc/4 100 125 ns (2) (2) (2) (2) 1.0 μs 4.0 μs Fosc/8 001 0.5 μs(2) 400 ns(2) 0.5 μs(2) 1.0 μs 2.0 μs 8.0 μs(3) Fosc/16 101 800 ns 800 ns 1.0 μs 2.0 μs 4.0 μs 16.0 μs(3) Fosc/32 010 1.0 μs 1.6 μs 2.0 μs 4.0 μs 8.0 μs(3) 32.0 μs(3) μs(3) 64.0 μs(3) Fosc/64 FRC Legend: Note 1: 2: 3: 4: 110 2.0 μs x11 1.0-6.0 μs 200 ns 3.2 μs (1,4) 1.0-6.0 μs 250 ns 4.0 μs (1,4) 1.0-6.0 μs 500 ns 8.0 (1,4) μs(3) 1.0-6.0 μs (1,4) 16.0 1.0-6.0 μs (1,4) 1.0-6.0 μs(1,4) Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 1.6 μs for VDD. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. FIGURE 11-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 133 PIC16F193X/LF193X 11.1.5 INTERRUPTS 11.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 11-3 shows the two output formats. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. Please refer to Section 11.1.5 “Interrupts” for more information. FIGURE 11-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 10-bit A/D Result Unimplemented: Read as ‘0’ MSB (ADFM = 1) bit 7 LSB bit 0 Unimplemented: Read as ‘0’ DS41364A-page 134 bit 0 bit 7 bit 0 10-bit A/D Result Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 11.2 11.2.1 11.2.4 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 11.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 11.2.6 “A/D Conversion Procedure”. COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF Interrupt Flag bit • Update the ADRESH and ADRESL registers with new conversion result 11.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. © 2008 Microchip Technology Inc. ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 11.2.5 SPECIAL EVENT TRIGGER The Special Event Trigger of the CCP5 module allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. Using the Special Event Trigger does not assure proper ADC timing. It is the user’s responsibility to ensure that the ADC timing requirements are met. Refer to Section 19.0 “Capture/Compare/PWM Modules (ECCP1, ECCP2, ECCP3, CCP4, CCP5)” for more information. Preliminary DS41364A-page 135 PIC16F193X/LF193X 11.2.6 A/D CONVERSION PROCEDURE EXAMPLE 11-1: This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: • Disable pin output driver (Refer to the TRIS register) • Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: • Select ADC conversion clock • Configure voltage reference • Select ADC input channel • Turn on ADC module Configure ADC interrupt (optional): • Clear ADC interrupt flag • Enable ADC interrupt • Enable peripheral interrupt • Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B’01110000’ ;ADC Frc clock MOVWF ADCON1 ; BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B’10000001’ ;Right justify, MOVWF ADCON0 ;Vdd Vref, AN0, On CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 11.3 “A/D Acquisition Requirements”. DS41364A-page 136 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 11.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 11-1: ADCON0: A/D CONTROL REGISTER 0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 00000 = AN0 00001 = AN1 00010 = AN2 00011 = AN3 00100 = AN4 00101 = AN5 00110 = AN6 00111 = AN7 01000 = AN8 01001 = AN9 01010 = AN10 01011 = AN11 01100 = AN12 01101 = AN13 01110 = Reserved. No channel connected. . . . 11100 = Reserved. No channel connected. 11101 = Temperature Reference from band gap 11110 = DAC output (aka CVREF output) 11111 = Fixed Voltage Reference (FVR) Buffer 1 Output bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: See Section 10.0 “Fixed Voltage Reference” for more information. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 137 PIC16F193X/LF193X REGISTER 11-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 ADFM ADCS2 ADCS1 ADCS0 — ADNREF ADPREF1 ADPREF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded. bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock supplied from a dedicated RC oscillator) bit 3 Unimplemented: Read as ‘0’ bit 2 ADNREF: A/D Negative Voltage Reference Configuration bit 0 = VREF- is connected to AVSS 1 = VREF- is connected to external VREF- bit 1-0 ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits 00 = VREF+ is connected to AVDD 01 = Reserved 10 = VREF+ is connected to external VREF+ 11 = VREF+ is connected to internal fixed voltage reference REGISTER 11-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result DS41364A-page 138 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 11-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES1 ADRES0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. REGISTER 11-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — ADRES9 ADRES8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result REGISTER 11-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result © 2008 Microchip Technology Inc. Preliminary DS41364A-page 139 PIC16F193X/LF193X 11.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 11-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 11-4. The maximum recommended impedance for analog sources is 10 kΩ. As the EQUATION 11-1: Assumptions: source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 11-1 may be used. This equation assumes that 1/2 LSb error is used (256 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Temperature = 50°C and external impedance of 10k Ω 5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 2µs + T C + [ ( Temperature - 25°C ) ( 0.05µs/°C ) ] The value for TC can be approximated with the following equations: 1 ⎞ = V CHOLD V AP P LI ED ⎛ 1 – -------------------------n+1 ⎝ ⎠ (2 )–1 ;[1] VCHOLD charged to within 1/2 lsb –TC ----------⎞ ⎛ RC V AP P LI ED ⎜ 1 – e ⎟ = V CHOLD ⎝ ⎠ ;[2] VCHOLD charge response to VAPPLIED – Tc ---------⎞ ⎛ 1 RC ⎞ ;combining [1] and [2] V AP P LI ED ⎜ 1 – e ⎟ = V A PP LIE D ⎛⎝ 1 – -------------------------n+1 ⎠ ⎝ ⎠ (2 )–1 Note: Where n = number of bits of the ADC. Solving for TC: T C = – C HOLD ( R IC + R SS + R S ) ln(1/511) = – 10pF ( 1k Ω + 7k Ω + 10k Ω ) ln(0.001957) = 1.12 µs Therefore: T ACQ = 2ΜS + 1.12 ΜS + [ ( 50°C- 25°C ) ( 0.05ΜS /°C ) ] = 4.42 ΜS Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. DS41364A-page 140 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 11-4: ANALOG INPUT MODEL VDD VT ≈ 0.6V ANx Rs CPIN 5 pF VA VT ≈ 0.6V RIC ≤ 1k Sampling Switch SS Rss I LEAKAGE(1) CHOLD = 10 pF VSS/VREF- Legend: CHOLD CPIN 6V 5V VDD 4V 3V 2V = Sample/Hold Capacitance = Input Capacitance I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC RSS = Resistance of Sampling Switch SS = Sampling Switch VT = Threshold Voltage RSS 5 6 7 8 9 10 11 Sampling Switch (kΩ) Note 1: Refer to Section 28.0 “Electrical Specifications”. FIGURE 11-5: ADC TRANSFER FUNCTION Full-Scale Range FFh FEh FDh ADC Output Code FCh 1 LSB ideal FBh Full-Scale Transition 04h 03h 02h 01h 00h Analog Input Voltage 1 LSB ideal VSS © 2008 Microchip Technology Inc. Zero-Scale Transition Preliminary VREF DS41364A-page 141 PIC16F193X/LF193X TABLE 11-2: Name SUMMARY OF ASSOCIATED ADC REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 137 ADCON1 ADFM ADCS2 ADCS1 ADCS0 — ADNREF ADPREF1 ADPREF0 138 ADRESH A/D Result Register High ADRESL A/D Result Register Low 138 139 ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 91 ANSELE — — — — — ANSE2 ANSE1 ANSE0 101 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 184 GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 73 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 74 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 86 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 91 CCP2CON INTCON 86 — — — — TRISE3 TRISE2 TRISE1 TRISE0 101 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 156 DACCON0 DACEN DACLPS DACOE --- DACPSS1 DACPSS0 --- DACNSS 153 --- --- --- DACR4 DACR3 DACR2 DACR1 DACR0 153 TRISE DACCON1 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for ADC module. DS41364A-page 142 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 12.0 COMPARATOR MODULE FIGURE 12-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: • • • • • • • • • Independent comparator control Programmable input selection Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep Programmable Speed/Power optimization PWM shutdown Programmable and fixed voltage reference 12.1 SINGLE COMPARATOR VIN+ + VIN- – Output VINVIN+ Output Note: Comparator Overview The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. A single comparator is shown in Figure 12-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 143 PIC16F193X/LF193X FIGURE 12-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH<1:0> CxON(1) 2 CxINTP Interrupt det CXIN0- 0 CXIN1- 1 MUX 2 (2) CXIN2CXIN3- 3 Set CxIF det CXPOL CxVN D Cx(3) CxVP 0 MUX 1 (2) CXIN+ DAC CxINTN Interrupt CXOUT MCXOUT Q To Data Bus + EN Q1 CxHYS CxSP To ECCP PWM Logic 2 FVR Buffer2 3 CXSYNC CxON VSS CXPCH<1:0> 0 CXOE TRIS bit CXOUT 2 D (from Timer1) T1CLK Note 1: 2: 3: Q 1 To Timer1 SYNCCXOUT When CxON = 0, the Comparator will produce a ‘0’ at the output When CxON = 0, all multiplexer inputs are disconnected. Output of comparator can be frozen during debugging. DS41364A-page 144 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 12.2 12.2.3 Comparator Control Each comparator has 2 control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register 12-1) contain Control and Status bits for the following: • • • • • • Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 12-1 shows the output state versus input conditions, including polarity control. TABLE 12-1: Interrupt enable Interrupt edge polarity Positive input channel selection Negative input channel selection 12.2.1 CxPOL CxOUT CxVN > CxVP 0 0 CxVN < CxVP 0 1 CxVN > CxVP 1 0 CxVN < CxVP 1 1 12.2.4 COMPARATOR ENABLE Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current consumption. 12.2.2 COMPARATOR OUTPUT SELECTION COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS Input Condition The CMxCON1 registers (see Register 12-2) contain Control bits for the following: • • • • COMPARATOR OUTPUT POLARITY COMPARATOR SPEED/POWER SELECTION The trade-off between speed or power can be optimized during program execution with the CxSP control bit. The default state for this bit is ‘1’ which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to ‘0’. The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: • CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set Note 1: The CxOE bit overrides the PORT data latch. Setting the CxON has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 145 PIC16F193X/LF193X 12.3 Comparator Hysteresis To enable the interrupt, you must set the following bits: A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. These hysteresis levels change as a function of the comparator’s Speed/Power mode selection. Table 12-2 shows the hysteresis levels. TABLE 12-2: CxSP HYSTERESIS LEVELS CxHYS Enabled CxHYS Disabled 0 ± 3mV << ± 1mV 1 ± 20mV ± 3mV • CxON, CxPOL and CxSP bits of the CMxCON0 register • CxIE bit of the PIE2 register • CxINTP bit of the CMxCON1 register (for a rising edge detection) • CxINTN bit of the CMxCON1 register (for a falling edge detection) • PEIE and GIE bits of the INTCON register The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: These levels are approximate. See Section 28.0 “Electrical Specifications” for more information. 12.4 Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1. See Section 16.6 “Timer1 Gate” for more information. This feature is useful for timing the duration or interval of an analog event. It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not increment while a change in the comparator is occurring. 12.4.1 COMPARATOR OUTPUT SYNCHRONIZATION The output from either comparator, C1 or C2, can be synchronized with Timer1 by setting the CxSYNC bit of the CMxCON0 register. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 12-2) and the Timer1 Block Diagram (Figure 16-1) for more information. 12.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present. 12.6 Comparator Positive Input Selection Configuring the CxPCH<1:0> bits of the CMxCON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: • • • • CxIN+ analog pin DAC FVR (Fixed Voltage Reference) AVSS (Analog Ground) See Section 14.0 “Fixed Voltage Reference” for more information on the fixed voltage reference module. See Section 11.0 “Analog-to-Digital Converter (ADC) Module” for more information on the CVDAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. 12.7 Comparator Negative Input Selection The CxNCH<1:0> bits of the CMxCON0 register direct one of four analog pins to the comparator inverting input. Note: When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. DS41364A-page 146 Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the CxPOL bit of the CMxCON0 register, or by switching the comparator on or off with the CxON bit of the CMxCON0 register. Preliminary To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 12.8 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 28.0 “Electrical Specifications” for more details. 12.9 Interaction with ECCP Logic The C1 and C2 comparators can be used as general purpose comparators. Their outputs can be brought out to the C1OUT and C2OUT pins. However, when the ECCP Auto-Shutdown is active it can use one or both comparators. If auto-restart is also enabled the comparators can be configured as a closed loop analog feedback to the ECCP thereby, creating an analog controlled PWM. 12.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 12-3. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. FIGURE 12-3: ANALOG INPUT MODEL VDD VT ≈ 0.6V Rs < 10K RIC To Comparator AIN CPIN 5 pF VA VT ≈ 0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC RS = Source Impedance = Analog Voltage VA = Threshold Voltage VT Note 1: See Section 28.0 “Electrical Specifications” © 2008 Microchip Technology Inc. Preliminary DS41364A-page 147 PIC16F193X/LF193X REGISTER 12-1: CMxCON0: COMPARATOR X CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled and consumes no active power 0 = Comparator is disabled bit 6 CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 CxOE: Comparator Output Enable bit 1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by CxON. 0 = CxOUT is internal only bit 4 CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in normal power, higher speed mode 0 = Comparator operates in low-power, low-speed mode bit 1 CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on tmr1_clk. Output updated on the falling edge of tmr1_clk. 0 = Comparator output to Timer1 and I/O pin is asynchronous. Refer to Figure 12-2. DS41364A-page 148 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 12-2: CMxCON1: COMPARATOR CX CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 CxINTP CxINTN CxPCH1 CxPCH0 — — CxNCH1 CxNCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit bit 5-4 CxPCH<1:0>: Comparator Positive Input Channel Select bits 00 = CxVP connects to CxIN+ pin 01 = CxVP connects to CVDAC 10 = CxVP connects to FVR Voltage Reference 11 = CxVP connects to AVSS bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CxNCH<1:0>: Comparator Negative Input Channel Select bits 00 = CxVN connects to CxIN0- pin 01 = CxVN connects to CxIN1- pin 10 = CxVN connects to CxIN2- pin 11 = CxVN connects to CxIN3- pin Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port TRIS bit = 0. REGISTER 12-3: CMOUT: COMPARATOR OUTPUT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — — — — — — MC2OUT MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit © 2008 Microchip Technology Inc. Preliminary DS41364A-page 149 PIC16F193X/LF193X TABLE 12-3: Name REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 0 Register on Page C1HYS C1SYNC 148 C2HYS C2SYNC 148 C1NCH1 C1NCH0 149 C2NCH1 C2NCH0 149 — MC2OUT MC1OUT 149 CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 156 — DACPSS1 DACPSS0 — DACNSS 153 — DACR4 DACR3 DACR2 DACR1 DACR0 153 Bit 7 Bit 6 Bit 5 Bit 4 CM1CON0 C1ON C1OUT C1OE C1POL --- C1SP CM2CON0 C2ON C2OUT C2OE C2POL — C2SP CM1CON1 C1NTP C1INTN C1PCH1 C1PCH0 — — CM2CON1 C2NTP C2INTN C2PCH1 C2PCH0 — — CMOUT — — — — — FVRCON FVREN FVRRDY TSEN TSRNG DACCON0 DACEN DACLPS DACOE DACCON1 — — INTCON Bit 3 Bit 2 Bit 1 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 78 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 75 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 93 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 93 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 94 ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 86 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 91 PORTC Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. DS41364A-page 150 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 13.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with VDD, with 32 selectable output levels. The output of the DAC can be configured to supply a reference voltage to the following: • Comparator positive input • ADC input channel • DACOUT device pin The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DACCON0 register. 13.1 Output Voltage Selection Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to DACOUT. Figure 13-1 shows an example buffering technique. 13.5 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 13.6 Effects of a Reset A device Reset affects the following: The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. The DAC output voltage is determined by the following equations: • • • • Voltage reference is disabled Fixed voltage reference is disabled DAC is removed from the DACOUT pin The DACR<4:0> range select bits are cleared EQUATION 13-1: DACR<4:0> VOUT = ⎛ ( VSOURCE+ – VSOURCE- ) × -------------------------------⎞ ⎝ ⎠ 2∧5 + VSOURCEVSOURCE+ = VDD, VREF+ or FVR1 VSOURCE+ = VSS or VREF- 13.2 Output Clamped to VSS The DAC output voltage can be set to Vss with no power consumption by setting the DACEN bit of the DACCON0 register to ‘0’: This allows the comparator to detect a zero-crossing while not consuming additional current from the DAC. 13.3 Output Ratiometric to VDD The DAC is VDD derived and therefore, the DAC output changes with fluctuations in VDD. The tested absolute accuracy of the DAC can be found in Section 28.0 “Electrical Specifications”. 13.4 Voltage Reference Output The DAC can be output to the device DACOUT pin by setting the DACOE bit of the DACCON0 register to ‘1’. Selecting the reference voltage for output on the DACOUT pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been configured for reference voltage output will always return a ‘0’. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 151 PIC16F193X/LF193X FIGURE 13-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM FVR_BUFFER2 Digital-to-Analog Converter (DAC) VDD 4 DACR<4:0> VREF+ DACPSS<1:0> R 2 R DACEN R 32 Steps R 32-to-1 MUX R DAC (To Comparator and ADC Modules) R R DACNSS<1:0> CVREF DACOE 2 VREF- DS41364A-page 152 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 13-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 DACEN DACLPS DACOE --- DACPSS1 DACPSS0 --- DACNSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DACEN: DAC Enable bit 0 = DAC is disabled 1 = DAC is enabled bit 6 DACLPS: DAC Low-Power Voltage State Select bit 0 = VDAC = DAC Negative reference source selected 1 = VDAC = DAC Positive reference source selected bit 5 DACOE: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACOUT pin 0 = DAC voltage level is disconnected from the DACOUT pin bit 4 Unimplemented: Read as ‘0’ bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits 00 = VDD 01 = VREF+ 10 = FVR1 output 11 = Reserved, do not use bit 1 Unimplemented: Read as ‘0’ bit 0 DACNSS: DAC Negative Source Select bits 0 = VSS 1 = VREF- REGISTER 13-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 --- --- --- DACR4 DACR3 DACR2 DACR1 DACR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DACR<4:0>: DAC Voltage Output Select bits VOUT = ((VSOURCE+) - (VSOURCE-))*(DACR<4:0>/(2^5)) + VSOURCE- Note 1: The output select bits are always right justified to ensure that any number of bits can be used without affecting the register layout. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 153 PIC16F193X/LF193X TABLE 13-1: REGISTERS ASSOCIATED WITH THE DIGITAL-TO-ANALOG CONVERTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 156 DACCON0 DACEN DACLPS DACOE --- DACPSS1 DACPSS0 --- DACNSS 153 DACCON1 --- --- --- DACR4 DACR3 DACR2 DACR1 DACR0 153 Name Legend: Shaded cells are not used with the DAC. DS41364A-page 154 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 14.0 FIXED VOLTAGE REFERENCE The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: • • • • • ADC input channel ADC positive reference Comparator positive input Programmable voltage reference LCD bias generator The FVR can be enabled by setting the FVREN bit of the FVRCON register. 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC and comparator modules is routed through two independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x. FIGURE 14-1: The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 11.0 “Analog-to-Digital Converter (ADC) Module” for additional information on selecting the appropriate input channel. The CDAFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the comparator module. Reference Section 12.0 “Comparator Module” for additional information on selecting the appropriate input channel. 14.2 FVR Stabilization Period When the fixed voltage reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section 28.0 “Electrical Specifications” for the minimum delay requirement. VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> 2 X1 X2 X4 FVR_BUFFER1 (To ADC Module) X1 X2 X4 FVR_BUFFER2 (To Comparators, DAC) 2 FVR_VREF (To LCD Bias Generator) FVREN FVRRDY FIGURE 14-2: + _ 1.024V Fixed Reference VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC16F193X/ PIC16LF193X CVREF Module R Voltage Reference Output Impedance © 2008 Microchip Technology Inc. + – CVREF Preliminary Buffered CVREF Output DS41364A-page 155 PIC16F193X/LF193X REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FVREN FVRRDY(1) — — CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 0 = Fixed Voltage Reference output is not active or stable 1 = Fixed Voltage Reference output is ready for use bit 5-4 Reserved: Read as ‘0’. Maintain these bits clear. bit 3-2 CDAFVR<1:0>: Comparator and D/A Converter Fixed Voltage Reference Selection bit 00 = Comparator and D/A Converter Fixed Voltage Reference Peripheral output is off. 01 = Comparator and D/A Converter Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = Comparator and D/A Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 = Comparator and D/A Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) bit 1-0 ADFVR<1:0>: A/D Converter Fixed Voltage Reference Selection bit 00 = A/D Converter Fixed Voltage Reference Peripheral output is off. 01 = A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 = A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) Note 1: 2: FVRRDY is always ‘1’ on regulated parts (PIC16F193X). Fixed Voltage Reference output cannot exceed VDD. TABLE 14-1: Name FVRCON Legend: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 156 Shaded cells are not used with the voltage reference. DS41364A-page 156 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 15.0 TIMER0 MODULE When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. The Timer0 module is an 8-bit timer/counter with the following features: • • • • • • Note: 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 15.1.2 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION register to ‘1’ and resetting the T0XCS bit in the CPSCON0 register to ‘0’. Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 15.1.1 8-Bit Counter Mode using the Capacitive Sensing Oscillator (CPSCLK) signal is selected by setting the TMR0CS bit in the OPTION register to ‘1’ and setting the T0XCS bit in the CPSCON0 register to ‘1’. 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the TMR0CS bit of the OPTION register. FIGURE 15-1: 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. Figure 15-1 is a block diagram of the Timer0 module. 15.1 The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION register. BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 8 T0CKI 1 0 Sync 2 TCY 1 0 From CPSCLK 1 TMR0SE TMR0CS 8-bit Prescaler PSA TMR0 Set Flag bit TMR0IF on Overflow Overflow to Timer1 T0XCS 8 PS<2:0> © 2008 Microchip Technology Inc. Preliminary DS41364A-page 157 PIC16F193X/LF193X 15.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 15.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: 15.1.5 The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 28.0 “Electrical Specifications”. 15.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41364A-page 158 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 15-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits TABLE 15-1: Name CPSCON0 INTCON TRISA Timer0 Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 CPSON — — — GIE PEIE TMR0IE INTE OPTION_REG WPUEN TMR0 Bit Value INTEDG TMR0CS TMR0SE Bit 3 Bit 2 Bit 1 CPSRNG1 CPSRNG0 CPSOUT Bit 0 Register on Page T0XCS 180 RBIE TMR0IF INTF RBIF 73 PSA PS2 PS1 PS0 51 TRISA3 TRISA2 TRISA1 TRISA0 Timer0 Module Register TRISA7 TRISA6 TRISA5 157* TRISA4 86 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module. * Page provides register information. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 159 PIC16F193X/LF193X NOTES: DS41364A-page 160 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 16.0 TIMER1 MODULE WITH GATE CONTROL • • • • The Timer1 module is a 16-bit timer/counter with the following features: Figure 16-1 is a block diagram of the Timer1 module. • • • • • • • • 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 3-bit prescaler Dedicated LP oscillator circuit Optionally synchronized comparator out Multiple Timer1 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Special Event Trigger (with CCP) • Selectable Gate Source Polarity FIGURE 16-1: Gate Toggle Mode Gate Single-pulse Mode Gate Value Status Gate Event Interrupt TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1GSPM 00 T1G From Timer0 Overflow 01 Comparator 1 SYNCC1OUT 10 Comparator 2 SYNCC2OUT 11 0 T1G_IN T1GVAL 0 Single Pulse TMR1ON T1GPOL D Q CK R Q 1 Q1 Acq. Control 1 Data Bus D Q RD T1GCON EN Interrupt T1GGO/DONE Set TMR1GIF det T1GTM TMR1GE Set flag bit TMR1IF on Overflow TMR1ON To Comparator Module TMR1(2) EN Synchronized clock input 0 TMR1H TMR1L Q D T1CLK 1 TMR1CS<1:0> T1OSO OUT T1OSC T1OSI Cap. Sensing Oscillator T1SYNC 11 Synchronize(3) Prescaler 1, 2, 4, 8 1 det 10 EN 0 T1OSCEN (1) FOSC Internal Clock 01 FOSC/4 Internal Clock 00 2 T1CKPS<1:0> FOSC/2 Internal Clock Sleep input T1CKI To LCD and Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 161 PIC16F193X/LF193X 16.1 Timer1 Operation 16.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 16-2 displays the clock source selections. 16.2.1 When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. 16.2.2 When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI or the capacitive sensing oscillator signal. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. Timer1 Operation TMR1GE 0 0 Off 0 1 Off 1 0 Always On 1 1 Count Enabled EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. TIMER1 ENABLE SELECTIONS TMR1ON INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. Table 16-1 displays the Timer1 enable selections. TABLE 16-1: Clock Source Selection When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • • • • TABLE 16-2: Timer1 enabled after POR Write to TMR1H or TMR1L Timer1 is disabled Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. CLOCK SOURCE SELECTIONS TMR1CS1 TMR1CS0 T1OSCEN Clock Source 0 1 x System Clock (FOSC) 0 0 x Instruction Clock (FOSC/4) 1 1 x Capacitive Sensing Oscillator 1 0 0 External Clocking on T1CKI Pin 1 0 1 Osc.Circuit On T1OSI/T1OSO Pins DS41364A-page 162 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 16.3 Timer1 Prescaler 16.6 Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry. This is also referred to as Timer1 Gate Enable. Timer1 Gate can also be driven by multiple selectable sources. 16.6.1 16.4 Timer1 Oscillator A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. The oscillator circuit is enabled by setting the T1OSCEN bit of the T1CON register. The oscillator will continue to run during Sleep. Note: 16.5 The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 16.5.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”). Note: 16.5.1 When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. Timer1 Gate TIMER1 GATE ENABLE The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 16-3 for timing details. TABLE 16-3: TIMER1 GATE ENABLE SELECTIONS T1CLK T1GPOL T1G ↑ 0 0 Counts ↑ 0 1 Holds Count ↑ 1 0 Holds Count ↑ 1 1 Counts 16.6.2 Timer1 Operation TIMER1 GATE SOURCE SELECTION The Timer1 Gate source can be selected from one of four different sources. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 16-4: T1GSS TIMER1 GATE SOURCES Timer1 Gate Source 00 Timer1 Gate Pin 01 Overflow of Timer0 (TMR0 increments from FFh to 00h) 10 Comparator 1 Output SYNCC1OUT (optionally synchronized out) 11 Comparator 2 Output SYNCC2OUT (optionally synchronized out) For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 163 PIC16F193X/LF193X 16.6.2.1 T1G Pin Gate Operation 16.6.4 The T1G pin is one source for Timer1 Gate Control. It can be used to supply an external source to the Timer1 Gate circuitry. 16.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 Gate circuitry. 16.6.2.3 Comparator C1 Gate Operation The output resulting from a Comparator 1 operation can be selected as a source for Timer1 Gate Control. The Comparator 1 output (SYNCC1OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 12.4.1 “Comparator Output Synchronization”. 16.6.2.4 Comparator C2 Gate Operation The output resulting from a Comparator 2 operation can be selected as a source for Timer1 Gate Control. The Comparator 2 output (SYNCC2OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 12.4.1 “Comparator Output Synchronization”. 16.6.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 Gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 16-4 for timing details. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. Clearing the T1GSPM bit of the T1GCON register will also clear the T1GGO/DONE bit. See Figure 16-5 for timing details. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 Gate source to be measured. See Figure 16-6 for timing details. 16.6.5 TIMER1 GATE VALUE STATUS When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GCON bit is valid even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). 16.6.6 TIMER1 GATE EVENT INTERRUPT When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. DS41364A-page 164 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 16.7 Timer1 Interrupt 16.9 The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: 16.8 The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. ECCP/CCP Capture/Compare Time Base The CCP modules uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see Section 19.0 “Capture/Compare/PWM Modules (ECCP1, ECCP2, ECCP3, CCP4, CCP5)”. 16.10 ECCP/CCP Special Event Trigger Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: • • • • • When any of the CCP’s are configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. TMR1ON bit of the T1CON register must be set TMR1IE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set T1SYNC bit of the T1CON register must be set TMR1CS bits of the T1CON register must be configured • T1OSCEN bit of the T1CON register must be configured Timer1 should be synchronized to the FOSC/4 to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h). For more information, see Section 11.2.5 “Special Event Trigger”. In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence. Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. FIGURE 16-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 165 PIC16F193X/LF193X FIGURE 16-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N FIGURE 16-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 DS41364A-page 166 N N+1 N+2 N+3 N+4 Preliminary N+5 N+6 N+7 N+8 © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 16-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 TMR1GIF N N+1 Set by hardware on falling edge of T1GVAL Cleared by software © 2008 Microchip Technology Inc. N+2 Preliminary Cleared by software DS41364A-page 167 PIC16F193X/LF193X FIGURE 16-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 TMR1GIF DS41364A-page 168 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL Preliminary N+4 Cleared by software © 2008 Microchip Technology Inc. PIC16F193X/LF193X 16.11 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 16-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 16-1: T1CON: TIMER1 CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 = Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC) 10 = Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on T1OSI/T1OSO pins 01 = Timer1 clock source is system clock (FOSC) 00 = Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated Timer1 oscillator circuit enabled 0 = Dedicated Timer1 oscillator circuit disabled bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS<1:0> = 1X 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMR1CS<1:0> = 0X This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop © 2008 Microchip Technology Inc. Preliminary DS41364A-page 169 PIC16F193X/LF193X 16.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 16-2, is used to control Timer1 Gate. REGISTER 16-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R-x/x R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL T1GSS1 T1GSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started This bit is automatically cleared when T1GSPM is cleared. bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 Gate pin 01 = Timer0 overflow output 10 = Comparator 1 optionally synchronized output (SYNCC1OUT) 11 = Comparator 2 optionally synchronized output (SYNCC2OUT) DS41364A-page 170 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 16-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 91 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 184 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 184 73 Name INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 74 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 90 PORTB TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 165* 165* TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 94 — TMR1ON 169 T1GSS1 T1GSS0 170 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL 91 Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 171 PIC16F193X/LF193X NOTES: DS41364A-page 172 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 17.0 TIMER2/4/6 MODULES There are three identical Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4 and Timer6 (also Timer2/4/6). The Timer2/4/6 modules incorporate the following features: • 8-bit Timer and Period registers (TMRx and PRx, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMRx match with PRx, respectively • Optional use as the shift clock for the MSSPx modules (Timer2 only) See Figure 17-1 for a block diagram of Timer2/4/6. FIGURE 17-1: TIMER2/4/6 BLOCK DIAGRAM TMRx Output FOSC/4 Prescaler 1:1, 1:4, 1:16, 1:64 2 TMRx Sets Flag bit TMRxIF Reset Postscaler 1:1 to 1:16 Comparator EQ TxCKPS<1:0> 4 PRx TxOUTPS<3:0> © 2008 Microchip Technology Inc. Preliminary DS41364A-page 173 PIC16F193X/LF193X 17.1 Timer2/4/6 Operation 17.3 The clock input to the Timer2/4/6 modules is the system instruction clock (FOSC/4). TMRx increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, TxCKPS<1:0> of the TxCON register. The value of TMRx is compared to that of the Period register, PRx, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMRx to 00h on the next cycle and drives the output counter/postscaler (see Section 17.2 “Timer2/4/6 Interrupt”). Timer2/4/6 Output The unscaled output of TMRx is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSPx modules operating in SPI mode. Additional information is provided in Section 17.0 “SSP Module Overview” 17.4 Timer2/4/6 Operation During Sleep The Timerx timers cannot be operated while the processor is in Sleep mode. The contents of the TMRx and PRx registers will remain unchanged while the processor is in Sleep mode. The TMRx and PRx registers are both directly readable and writable. The TMRx register is cleared on any device Reset, whereas the PRx register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: • • • • • • • • • a write to the TMRx register a write to the TxCON register Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset Watchdog Timer (WDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction Note: 17.2 TMRx is not cleared when TxCON is written. Timer2/4/6 Interrupt Timer2/4/6 can also generate an optional device interrupt. The Timer2/4/6 output signal (TMRx-to-PRx match) provides the input for the 4-bit counter/postscaler. This counter generates the TMRx match interrupt flag which is latched in TMRxIF of the PIRx register. The interrupt is enabled by setting the TMRx Match Interrupt Enable bit, TMRxIE of the PIEx register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, TxOUTPS<3:0>, of the TxCON register. DS41364A-page 174 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 17-1: TXCON: TIMER2-TYPE TIMER CONTROL REGISTER U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMRxON TxCKPS1 TxCKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler bit 2 TMRxON: Timerx On bit 1 = Timerx is on 0 = Timerx is off bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 10 = Prescaler is 16 11 = Prescaler is 64 © 2008 Microchip Technology Inc. Preliminary DS41364A-page 175 PIC16F193X/LF193X TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 184 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 184 GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 73 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 74 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 76 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 79 INTCON PR2 Timer2 Module Period Register 173* TMR2 Holding Register for the 8-bit TMR2 Register 173* T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 175 Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information. DS41364A-page 176 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 18.0 CAPACITIVE SENSING MODULE The capacitive sensing module allows for an interaction with an end user without a mechanical interface. In a typical application, the capacitive sensing module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the capacitive sensing module. The capacitive sensing module requires software and at least one timer resource to determine the change in frequency. Key features of this module include: • • • • • Analog MUX for monitoring multiple inputs Capacitive sensing oscillator Multiple timer resources Software control Operation during Sleep FIGURE 18-1: CAPACITIVE SENSING BLOCK DIAGRAM Timer0 Module Set TMR0IF TMR0CS T0XCS FOSC/4 T0CKI 0 TMR0 0 Overflow 1 1 CPSCH<3:0>(2) CPSON(3) CPS0 CPS1 CPS2 CPS3 Timer1 Module CPS4 CPSON T1CS<1:0> CPS5 CPS6 CPS8(1) Capacitive Sensing Oscillator CPS9(1) CPSOSC CPS7 CPS10(1) CPS11 (1) FOSC FOSC/4 CPSCLK T1OSC/ T1CKI CPSOUT TMR1H:TMR1L T1GSEL<1:0> CPSRNG<1:0> (1) EN CPS12 T1G CPS13(1) (1) CPS14 SYNCC1OUT CPS15(1) CPS16(1) Note 1: 2: 3: Timer1 Gate Control Logic SYNCC2OUT Reference Register 18-2 for channels implemented on each device CPSCH3 is not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938. If CPSON = 0, disabling capacitive sensing, no channel is selected. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 177 PIC16F193X/LF193X 18.1 18.4.1 Analog MUX TIMER0 The capacitive sensing module can monitor up to 16 inputs. The capacitive sensing inputs are defined as CPS<15:0>. To determine if a frequency change has occurred the user must: To select Timer0 as the timer resource for the capacitive sensing module: • Select the appropriate CPS pin by setting the CPSCH<3:0> bits of the CPSCON1 register • Set the corresponding ANSEL bit • Set the corresponding TRIS bit • Run the software algorithm When Timer0 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for Timer0. Refer to Section 15.0 “Timer0 Module” for additional information. Selection of the CPSx pin while the module is enabled will cause the capacitive sensing oscillator to be on the CPSx pin. Failure to set the corresponding ANSEL and TRIS bits can cause the capacitive sensing oscillator to stop, leading to false frequency readings. 18.2 Capacitive Sensing Oscillator The capacitive sensing oscillator consists of a constant current source and a constant current sink, to produce a triangle waveform. The CPSOUT bit of the CPSCON0 register shows the status of the capacitive sensing oscillator, whether it is a sinking or sourcing current. The oscillator is designed to drive a capacitive load (single PCB pad) and at the same time, be a clock source to either Timer0 or Timer1. The oscillator has three different current settings as defined by CPSRNG<1:0> of the CPSCON0 register. The different current settings for the oscillator serve two purposes: • Set the T0XCS bit of the CPSCON0 register • Clear the TMR0CS bit of the OPTION register 18.4.2 To select Timer1 as the timer resource for the capacitive sensing module, set the TMR1CS<1:0> of the T1CON register to ‘11’. When Timer1 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for Timer1. Because the Timer1 module has a gate control, developing a time base for the frequency measurement can be simplified by using the Timer0 overflow flag. It is recommend that the Timer0 overflow flag, in conjunction with the Toggle mode of the Timer1 Gate, be used to develop the fixed time base required by the software portion of the capacitive sensing module. Refer to Section 16.12 “Timer1 Gate Control Register” for additional information. TABLE 18-1: TIMER1 ENABLE FUNCTION TMR1ON TMR1GE Timer1 Operation 0 0 Off 0 1 Off 1 0 On 1 1 Count Enabled by input • Maximize the number of counts in a timer for a fixed time base • Maximize the count differential in the timer during a change in frequency 18.3 TIMER1 Timer resources To measure the change in frequency of the capacitive sensing oscillator, a fixed time base is required. For the period of the fixed time base, the capacitive sensing oscillator is used to clock either Timer0 or Timer1. The frequency of the capacitive sensing oscillator is equal to the number of counts in the timer divided by the period of the fixed time base. 18.4 Fixed Time Base To measure the frequency of the capacitive sensing oscillator, a fixed time base is required. Any timer resource or software loop can be used to establish the fixed time base. It is up to the end user to determine the method in which the fixed time base is generated. Note: The fixed time base can not be generated by the timer resource that the capacitive sensing oscillator is clocking. DS41364A-page 178 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 18.5 18.5.3 Software Control The software portion of the capacitive sensing module is required to determine the change in frequency of the capacitive sensing oscillator. This is accomplished by the following: • Setting a fixed time base to acquire counts on Timer0 or Timer1 • Establishing the nominal frequency for the capacitive sensing oscillator • Establishing the reduced frequency for the capacitive sensing oscillator due to an additional capacitive load • Set the frequency threshold 18.5.1 The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. Refer to Application Note AN1103, “Software Handling for Capacitive Sensing” (DS01103) for more detailed information on the software required for capacitive sensing module. Note: For more information on general capacitive sensing refer to Application Notes: • AN1101, “Introduction to Capacitive Sensing” (DS01101) • AN1102, “Layout and Physical Design Guidelines for Capacitive Sensing” (DS01102) NOMINAL FREQUENCY (NO CAPACITIVE LOAD) To determine the nominal frequency of the capacitive sensing oscillator: • Remove any extra capacitive load on the selected CPSx pin • At the start of the fixed time base, clear the timer resource • At the end of the fixed time base save the value in the timer resource 18.6 Operation during Sleep The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep. In order for the software to determine if a frequency change has occurred, the part must be awake. However, the part does not have to be awake when the timer resource is acquiring counts. Note: The value of the timer resource is the number of oscillations of the capacitive sensing oscillator for the given time base. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed time base. 18.5.2 FREQUENCY THRESHOLD Timer0 does not operate when in Sleep, and therefore cannot be used for capacitive sense measurements in Sleep. REDUCED FREQUENCY (ADDITIONAL CAPACITIVE LOAD) The extra capacitive load will cause the frequency of the capacitive sensing oscillator to decrease. To determine the reduced frequency of the capacitive sensing oscillator: • Add a typical capacitive load on the selected CPSx pin • Use the same fixed time base as the nominal frequency measurement • At the start of the fixed time base, clear the timer resource • At the end of the fixed time base save the value in the timer resource The value of the timer resource is the number of oscillations of the capacitive sensing oscillator with an additional capacitive load. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed time base. This frequency should be less than the value obtained during the nominal frequency measurement. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 179 PIC16F193X/LF193X REGISTER 18-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPSON: Capacitive Sensing Module Enable bit 1 = Capacitive sensing module is operating 0 = Capacitive sensing module is shut off and consumes no operating current bit 6-4 Unimplemented: Read as ‘0’ bit 3-2 CPSRNG<1:0>: Capacitive Sensing Oscillator Range bits 00 = Oscillator is off 01 = Oscillator is in low range. Charge/discharge current is nominally 0.1 µA. 10 = Oscillator is in medium range. Charge/discharge current is nominally 1.2 µA. 11 = Oscillator is in high range. Charge/discharge current is nominally 18 µA. bit 1 CPSOUT: Capacitive Sensing Oscillator Status bit 1 = Oscillator is sourcing current (Current flowing out the pin) 0 = Oscillator is sinking current (Current flowing into the pin) bit 0 T0XCS: Timer0 External Clock Source Select bit If TMR0CS = 1 The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0: 1 = Timer0 clock source is the capacitive sensing oscillator 0 = Timer0 clock source is the T0CKI pin If TMR0CS = 0 Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4 DS41364A-page 180 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 18-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0/0(1, 2) R/W-0/0(1) R/W-0/0 R/W-0/0 R/W-0/0 — — — CPSCH4 CPSCH3 CPSCH2 CPSCH1 CPSCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CPSCH<3:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These bits are ignored. No channel is selected. If CPSON = 1: 0000 = channel 0, (CPS0) 0001 = channel 1, (CPS1) 0010 = channel 2, (CPS2) 0011 = channel 3, (CPS3) 0100 = channel 4, (CPS4) 0101 = channel 5, (CPS5) 0110 = channel 6, (CPS6) 0111 = channel 7, (CPS7) 1000 = channel 8, (CPS8(1)) 1001 = channel 9, (CPS9(1)) 1010 = channel 10, (CPS10(1)) 1011 = channel 11, (CPS11(1)) 1100 = channel 12, (CPS12(1)) 1101 = channel 13, (CPS13(1)) 1110 = channel 14, (CPS14(1)) 1111 = channel 15, (CPS15(1)) Note 1: 2: These channels are not implemented on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938. This bit is not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938, read as ‘0’ TABLE 18-2: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 86 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 91 ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 97 INTCON OPTION_REG GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 51 74 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 169 TxCON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMRXON TXCKPS1 TXCKPS0 175 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 86 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 91 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 97 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the capacitive sensing module. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 181 PIC16F193X/LF193X NOTES: DS41364A-page 182 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.0 CAPTURE/COMPARE/PWM MODULES (ECCP1, ECCP2, ECCP3, CCP4, CCP5) This device contains three Enhanced Capture/Compare/PWM (ECCP1, ECCP2, ECCP3) and two standard Capture/Compare/PWM module (CCP4 and CCP5). The CCP4 and CCP5 modules are identical in operation. The ECCP1, ECCP2 and ECCP3 modules may also be referred to as CCP1, CCP2, CCP3, as required. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 183 PIC16F193X/LF193X 19.1 TABLE 19-1: Capture/Compare/PWM The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. REQUIRED TIMER RESOURCES CCP Mode Timer Resource Capture Timer1 Compare Timer1 PWM Timer2 or 4 or 6 Table 19-1 shows the timer resources required by the CCP module. REGISTER 19-1: CCPXCON: CCPX CONTROL REGISTER R/W-00 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxM1(1) PxM0(1) DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits(1) If CCPxM<3:2> = 00, 01, 10: xx = PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins If CCPxM<3:2> = 11: 00 = Single output; PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 = Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCPx module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Capture mode 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF) 1001 = Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF) 1010 = Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state 1011 = Compare mode: trigger special event (ECCPx resets TMR1 or TMR3, sets CCPxIF bit, ECCP2 trigger also starts A/D conversion if A/D module is enabled)(1) CCP<5:4> only: 11xx = PWM mode ECCP<3:1> only: 1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low Note 1: These bits are not implemented on CCP<5:4>. DS41364A-page 184 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.2 CCP Clock Selection timers with auto-reload (Timer2, Timer4 and Timer6), PWM mode on the CCP modules can use any of these timers. The PIC16F193X/LF193X allows each individual CCP module to select the timer source that controls the CCP module. Each module has an independent selection. The following registers are used to select which timer is used: As the PIC16F193X/LF193X has only one 16-bit timer (Timer1), the Capture and Compare modes of the CCP modules always uses Timer1. As there are three 8-bit REGISTER 19-2: • CCP Timers Control Register 0 (CCPTMRS0) • CCP Timers Control Register 1 (CCPTMRS1) CCPTMRS0: CCP TIMERS CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C4TSEL<1:0>: CCP4 Timer Selection 00 = CCP4 is based off Timer 2 in PWM Mode 01 = CCP4 is based off Timer 4 in PWM Mode 10 = CCP4 is based off Timer 6 in PWM Mode 11 = Reserved bit 5-4 C3TSEL<1:0>: CCP3 Timer Selection 00 = CCP3 is based off Timer 2 in PWM Mode 01 = CCP3 is based off Timer 4 in PWM Mode 10 = CCP3 is based off Timer 6 in PWM Mode 11 = Reserved bit 3-2 C2TSEL<1:0>: CCP2 Timer Selection 00 = CCP2 is based off Timer 2 in PWM Mode 01 = CCP2 is based off Timer 4 in PWM Mode 10 = CCP2 is based off Timer 6 in PWM Mode 11 = Reserved bit 1-0 C1TSEL<1:0>: CCP1 Timer Selection 00 = CCP1 is based off Timer 2 in PWM Mode 01 = CCP1 is based off Timer 4 in PWM Mode 10 = CCP1 is based off Timer 6 in PWM Mode 11 = Reserved © 2008 Microchip Technology Inc. Preliminary DS41364A-page 185 PIC16F193X/LF193X REGISTER 19-3: CCPTMRS1: CCP TIMERS CONTROL REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — — — — — — C5TSEL1 C5TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 C5TSEL<1:0>: CCP5 Timer Selection 00 = CCP5 is based off Timer 2 in PWM Mode 01 = CCP5 is based off Timer 4 in PWM Mode 10 = CCP5 is based off Timer 6 in PWM Mode 11 = Reserved DS41364A-page 186 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.3 19.3.2 Capture Mode In Capture mode, the CCPRxH, CCPRxL register pair captures the 16-bit value of the TMR1 register when an event occurs on pin CCPx. An event is defined as one of the following and is configured by the CCPxM<3:0> bits of the CCPxCON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new captured value (see Figure 19-1). 19.3.1 Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. 19.3.3 Note: In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition. FIGURE 19-1: Prescaler ÷ 1, 4, 16 CAPTURE MODE OPERATION BLOCK DIAGRAM Set Flag bit CCPxIF (PIRx register) CCPx pin CCPRxH and Edge Detect TMR1H 19.3.4 Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. CCP PRESCALER There are four prescaler settings specified by the CCPxM<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler (see Example 19-1). EXAMPLE 19-1: CCPRxL CHANGING BETWEEN CAPTURE PRESCALERS BANKSEL CCP1CON CLRF MOVLW Capture Enable CCPxCON<3:0> System Clock (FOSC) SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode. CCPX PIN CONFIGURATION Also, the CCPx pin function can be moved to alternative pins using the APFCON register. Refer to Section 6.1 “Alternate Pin Function” for more details. TIMER1 MODE SELECTION TMR1L MOVWF 19.3.5 ;Set Bank bits to point ;to CCP1CON CCP1CON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP ON CCP1CON ;Load CCP1CON with this ;value CAPTURE DURING SLEEP Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. If Timer1 is clocked by FOSC/4, then Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. If Timer1 is clocked by an external clock source, then Capture mode will operate as defined in Section 19.1 “Capture/Compare/PWM”. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 187 PIC16F193X/LF193X TABLE 19-2: REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CCPxCON PxM1(1) PxM0(1) DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 184 CCPRxL Capture/Compare/PWM Register x Low Byte (LSB) CCPRxH Capture/Compare/PWM Register x High Byte (MSB) 187 187 CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 148 CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0 — — C1NCH1 C1NCH0 149 CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 148 CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0 — — C2NCH1 C2NCH0 149 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 INTCON PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 74 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 75 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 76 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 78 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 79 T1OSCEN T1SYNC — TMR1ON 169 T1GVAL T1GSS1 T1GSS0 170 PIR3 T1CON T1GCON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 165 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 165 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 86 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 91 94 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 TRISE — — — — TRISE3 TRISE2(2) TRISE1(2) TRISE0(2) 97 101 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture and Compare. Note 1: Applies to ECCP modules only. DS41364A-page 188 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.4 19.4.2 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCPx module may: • • • • • Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate a Special Event Trigger Generate a Software Interrupt All Compare modes can generate an interrupt. FIGURE 19-2: 19.4.4 CCPxCON<3:0> Mode Select Set CCPxIF Interrupt Flag (PIRx) 4 CCPRxH CCPRxL Q S R Output Logic Match TRIS Output Enable Comparator TMR1H TMR1L Special Event Trigger Special Event Trigger will: • CCP<4:1>: Reset Timer1, but not set interrupt flag bit TMR1IF. • CCP5: Reset Timer1, but not set interrupt flag bit and set bit GO/DONE (ADCON0<1>). 19.4.1 CCPX PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the associated TRIS bit. Also, the CCPx pin function can be moved to alternative pins using the APFCON register. Refer to Section 6.1 “Alternate Pin Function” for more details. Note: 19.4.3 Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the CCPx module does not assert control of the CCPx pin (see the CCP1CON register). COMPARE MODE OPERATION BLOCK DIAGRAM CCPx Pin In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. Note: The action on the pin is based on the value of the CCPxM<3:0> control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set. TIMER1 MODE SELECTION SPECIAL EVENT TRIGGER When Special Event Trigger mode is chosen (CCPxM<3:0> = 1011), the CCPx module does the following: • Resets Timer1 • Starts an ADC conversion if ADC is enabled (CCP5 only) The CCPx module does not assert control of the CCPx pin in this mode (see the CCPxCON register). The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPRxH, CCPRxL register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. The Special Event Trigger output starts an A/D conversion (if the A/D module is enabled). This feature is only available on CCP5). This allows the CCPRxH, CCPRxL register pair to effectively provide a 16-bit programmable period register for Timer1. Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. 19.4.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 189 PIC16F193X/LF193X TABLE 19-3: REGISTERS ASSOCIATED WITH COMPARE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CCPxCON PxM1(1) PxM0(1) DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 184 CCPRxL Capture/Compare/PWM Register x Low Byte (LSB) CCPRxH Capture/Compare/PWM Register x High Byte (MSB) 187 187 CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 148 CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0 — — C1NCH1 C1NCH0 149 CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 148 CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0 — — C2NCH1 C2NCH0 149 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 INTCON PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 74 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 75 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 76 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 78 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 79 T1OSCEN T1SYNC — TMR1ON 169 T1GVAL T1GSS1 T1GSS0 170 PIR3 T1CON T1GCON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 165 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 165 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 86 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 91 94 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 TRISE — — — — TRISE3 TRISE2(2) TRISE1(2) TRISE0(2) 97 101 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture and Compare. Note 1: Applies to ECCP modules only. 2: These bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’. DS41364A-page 190 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.5 FIGURE 19-3: PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCPx pin. The duty cycle, period and resolution are determined by the following registers: • • • • CCPxCON<5:4> Duty Cycle Registers PRx TxCON CCPRxL CCPxCON CCPRxL CCPRxH(2) (Slave) CCPx The ECCP modules have the following additional registers: R Comparator • ECCPxAS • PSTRxCON • PWMxCON TMRx (1) Q S TRIS In Pulse-Width Modulation (PWM) mode, the CCPx module produces up to a 10-bit resolution PWM output on the CCPx pin. Since the CCPx pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to enable the CCPx pin output driver. Note: SIMPLIFIED PWM BLOCK DIAGRAM Comparator PRx Note 1: Clearing the CCPxCON register will relinquish CCPx control of the CCPx pin. The CCPx module in PWM mode can have the PWM based off of either Timer2, Timer4 or TImer6. This is controlled by the CCPTMRS0 and CCPTMRS1 registers. Reference Section 19.2 “CCP Clock Selection” for more information. Figure 19-3 shows a simplified block diagram of PWM operation. Clear Timerx, toggle CCPx pin and latch duty cycle 2: The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPRxH is a read-only register. The PWM output (Figure 19-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 19-4: Figure 19-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 19.5.7 “Setup for PWM Operation”. CCP PWM OUTPUT Period Pulse Width TMRx = PRx TMRx\2 = CCPRxH:CCPxCON<5:4> TMRX = 0 © 2008 Microchip Technology Inc. Preliminary DS41364A-page 191 PIC16F193X/LF193X 19.5.1 PWM PERIOD 19.5.2 The PWM period is specified by the PRx register of Timerx. The PWM period can be calculated using the formula of Equation 19-1. EQUATION 19-1: PWM PERIOD PWM Period = [ ( PR2x ) + 1 ] • 4 • T OSC • (TMRx Prescale Value) Note 1: TOSC = 1/FOSC PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB<1:0> bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB<1:0> bits of the CCPxCON register contain the two LSbs. CCPRxL and DCxB<1:0> bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PRx and TMRx registers occurs). While using the PWM, the CCPRxH register is read-only. When TMRx is equal to PRx, the following three events occur on the next increment cycle: Equation 19-2 is used to calculate the PWM pulse width. • TMRx is cleared • The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is latched from CCPRxL into CCPRxH. Equation 19-3 is used to calculate the PWM duty cycle ratio. Note: EQUATION 19-2: PULSE WIDTH Pulse Width = ( CCPRxL:CCPxCON<5:4> ) • T OSC • (TMRx Prescale Value) The Timerx postscaler (see Section 17.1 “Timer2/4/6 Operation”) is not used in the determination of the PWM frequency. EQUATION 19-3: DUTY CYCLE RATIO ( CCPRxL:CCPxCON<5:4> ) Duty Cycle Ratio = ----------------------------------------------------------------------4 ( PRx + 1 ) The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMRx register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timerx prescaler is set to 1:1. When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure 19-3). DS41364A-page 192 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.5.3 PWM RESOLUTION EQUATION 19-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PRx is 255. The resolution is a function of the PRx register value as shown by Equation 19-4. TABLE 19-4: Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits) Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. 1.95 kHz 7.81 kHz 31.25 kHz 125 kHz 250 kHz 333.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits) TABLE 19-6: log [ 4 ( PRx + 1 ) ] Resolution = ------------------------------------------ bits log ( 2 ) EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz) PWM Frequency TABLE 19-5: PWM RESOLUTION 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits) © 2008 Microchip Technology Inc. 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Preliminary DS41364A-page 193 PIC16F193X/LF193X 19.5.4 OPERATION IN SLEEP MODE 19.5.7 In Sleep mode, the TMRx register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMRx will continue from its previous state. 19.5.5 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 8.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details. The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. • 19.5.6 EFFECTS OF RESET • Any Reset will force all ports to Input mode and the CCP registers to their Reset states. • 6. • • Disable the PWM pin (CCPx) output driver(s) by setting the associated TRIS bit(s). Load the PRx register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty cycle value. Configure and start Timerx: Clear the TMRxIF interrupt flag bit of the PIRx register. See Note below. Configure the TxCKPS bits of the TxCON register with the Timerx prescale value. Enable Timerx by setting the TMRxON bit of the T2CON register. Enable PWM output pin: Wait until Timerx overflows, TMRxIF bit of the PIR1 register is set. See Note below. Enable the PWM pin (CCPx) output driver(s) by clearing the associated TRIS bit(s). Note: DS41364A-page 194 SETUP FOR PWM OPERATION Preliminary In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. © 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.6 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. The Enhanced PWM mode can generate a PWM signal on up to four different output pins with up to 10-bits of resolution. It can do this through four different PWM output modes: • • • • Table 19-7 shows the pin assignments for each Enhanced PWM mode. Single PWM Half-Bridge PWM Full-Bridge PWM, Forward mode Full-Bridge PWM, Reverse mode Figure 19-5 shows an example of a simplified block diagram of the Enhanced PWM module. Note: To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal. To select an Enhanced PWM mode, the P1M bits of the CCP1CON register must be set appropriately. Note: The PWM Enhanced mode is available on the Enhanced Capture/Compare/PWM module (CCP1) only. FIGURE 19-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE Duty Cycle Registers DCxB<1:0> CCPxM<3:0> 4 PxM<1:0> 2 CCPRxL CCPx/P1A CCPx/P1A TRISx CCPRxH (Slave) P1B R Comparator Output Controller Q P1B TRISx P1C TMRx (1) S P1D Comparator Clear Timerx, toggle PWM pin and latch duty cycle PRx Note 1: P1C TRISx P1D TRISx PWMxCON The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. Note 1: The TRIS register value for each PWM output must be configured appropriately. 2: Clearing the CCPxCON register will relinquish ECCP control of all PWM output pins. 3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions. TABLE 19-7: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> CCPx/P1A Single 00 Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: P1B Yes (1) P1C Yes (1) P1D Yes(1) Pulse Steering enables outputs in Single mode. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 195 PIC16F193X/LF193X FIGURE 19-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) PxM<1:0> Signal PRX+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON<6:0>) Note 1: Dead-band delay is programmed using the PWMxCON register (Section 19.6.6 “Programmable Dead-Band Delay Mode”). DS41364A-page 196 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 19-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal PxM<1:0> PRx+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) 10 (Half-Bridge) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON<6:0>) Note 1: Dead-band delay is programmed using the PWMxCON register (Section 19.6.6 “Programmable Dead-Band Delay Mode”). © 2008 Microchip Technology Inc. Preliminary DS41364A-page 197 PIC16F193X/LF193X 19.6.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCPx/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 19-9). This mode can be used for Half-Bridge applications, as shown in Figure 19-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in Half-Bridge power devices. The value of the PDC<6:0> bits of the PWMxCON register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 19.6.6 “Programmable Dead-Band Delay Mode” for more details of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs. FIGURE 19-8: Period Period Pulse Width P1A(2) td td P1B(2) (1) (1) (1) td = Dead-Band Delay Note 1: 2: FIGURE 19-9: EXAMPLE OF HALF-BRIDGE PWM OUTPUT At this time, the TMRx register is equal to the PRx register. Output signals are shown as active-high. EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A Load FET Driver + P1B - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET Driver FET Driver P1A FET Driver Load FET Driver P1B DS41364A-page 198 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.6.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 19-10. In the Forward mode, pin CCPx/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure 19-11. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure 19-11. P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 19-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D © 2008 Microchip Technology Inc. Preliminary DS41364A-page 199 PIC16F193X/LF193X FIGURE 19-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A (2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) Note 1: 2: (1) At this time, the TMRx register is equal to the PRx register. Output signal is shown as active-high. DS41364A-page 200 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.6.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register. The following sequence occurs four Timerx cycles prior to the end of the current PWM period: • The modulated outputs (P1B and P1D) are placed in their inactive state. • The associated unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. • PWM modulation resumes at the beginning of the next period. See Figure 19-12 for an illustration of this sequence. The Full-Bridge mode does not provide dead-band delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation where dead-band delay is required. This situation occurs when both of the following conditions are true: 1. 2. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn off time of the power switch, including the power device and driver circuit, is greater than the turn on time. Figure 19-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty cycle. In this example, at time t1, the output P1A and P1D become inactive, while output P1C becomes active. Since the turn off time of the power devices is longer than the turn on time, a shoot-through current will flow through power devices QC and QD (see Figure 19-10) for the duration of ‘t’. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. 2. Reduce PWM duty cycle for one PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 19-12: EXAMPLE OF PWM DIRECTION CHANGE Period(1) Signal Period P1A (Active-High) P1B (Active-High) Pulse Width P1C (Active-High) (2) P1D (Active-High) Pulse Width Note 1: 2: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle. When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is four Timerx counts. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 201 PIC16F193X/LF193X FIGURE 19-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B PW P1C P1D PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: T = TOFF – TON All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver. DS41364A-page 202 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.6.3 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the Off state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [P1A/P1C] and [P1B/P1D]. The state of each pin pair is determined by the PSSxAC and PSSxBD bits of the CCPxAS register. Each pin pair may be placed into one of three states: • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) The CCPxM<1:0> bits of the CCPxCON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enable is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMRxIF bit of the PIRx register being set as the second PWM period begins. 19.6.4 ENHANCED PWM AUTO-SHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the CCPxAS<2:0> bits of the CCPxAS register. A shutdown event may be generated by: • A logic ‘0’ on the INT pin • Comparator Cx • Setting the CCPxASE bit in firmware A shutdown condition is indicated by the CCPxASE (Auto-Shutdown Event Status) bit of the CCPxAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state. When a shutdown event occurs, two things happen: The CCPxASE bit is set to ‘1’. The CCPxASE will remain set until cleared in firmware or an auto-restart occurs (see Section 19.6.5 “Auto-Restart Mode”). © 2008 Microchip Technology Inc. Preliminary DS41364A-page 203 PIC16F193X/LF193X REGISTER 19-4: CCPXAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCPxASE CCPxAS2 CCPxAS1 CCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCPxASE: CCPx Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; CCPx outputs are in shutdown state 0 = CCPx outputs are operating bit 6-4 CCxPAS<2:0>: CCPx Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator C1 output low(1) 010 = Comparator C2 output low(1) 011 = Either Comparator C1 or C2 low(1) 100 = VIL on INT pin 101 = VIL on INT pin or Comparator C1 low(1) 110 = VIL on INT pin or Comparator C2 low(1) 111 = VIL on INT pin or Comparator C1 or Comparator C2 low(1) bit 3-2 PSSxACx: Pins P1A and P1C Shutdown State Control bits 00 = Drive pins P1A and P1C to ‘0’ 01 = Drive pins P1A and P1C to ‘1’ 1x = Pins P1A and P1C tri-state bit 1-0 PSSxBDx: Pins P1B and P1D Shutdown State Control bits 00 = Drive pins P1B and P1D to ‘0’ 01 = Drive pins P1B and P1D to ‘1’ 1x = Pins P1B and P1D tri-state Note 1: If CxSYNC is enabled, the shutdown will be delayed by Timer1. Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the CCPxASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period. DS41364A-page 204 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 19-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0) Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow Missing Pulse (CCPxASE not clear) Timer Overflow Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event CCPxASE bit Shutdown Event Occurs 19.6.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit in the PWMxCON register. FIGURE 19-15: Shutdown Event Clears PWM Resumes CCPxASE Cleared by Firmware If auto-restart is enabled, the CCPxASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the CCPxASE bit will be cleared via hardware and normal operation will resume. PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1) Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow Missing Pulse (CCPxASE not clear) Timer Overflow Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event CCPxASE bit PWM Resumes Shutdown Event Occurs Shutdown Event Clears © 2008 Microchip Technology Inc. Preliminary CCPxASE Cleared by Hardware DS41364A-page 205 PIC16F193X/LF193X 19.6.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 19-16: In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shoot-through current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. Period Period Pulse Width P1A(2) td td P1B(2) (1) (1) (1) td = Dead-Band Delay Note 1: In Half-Bridge mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 19-16 for illustration. The lower seven bits of the associated PWMxCON register (Register 19-5) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 19-17: EXAMPLE OF HALF-BRIDGE PWM OUTPUT 2: At this time, the TMRx register is equal to the PRx register. Output signals are shown as active-high. EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + V - P1A Load FET Driver + V - P1B V- DS41364A-page 206 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 19-5: PWMxCON: ENHANCED PWM CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM bit 6-0 PxDC<6:0>: PWM Delay Count bits PxDCx = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 207 PIC16F193X/LF193X 19.6.7 PULSE STEERING MODE In Single Output mode, pulse steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCPxM<3:2> = 11 and PxM<1:0> = 00 of the CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STRx<D:A> bits of the PSTRxCON register, as shown in Table 19-7. Note: The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. While the PWM Steering mode is active, CCPxM<1:0> bits of the CCPxCON register select the PWM output polarity for the P1<D:A> pins. The PWM auto-shutdown operation also applies to PWM Steering mode as described in Section 19.6.4 “Enhanced PWM Auto-shutdown mode”. An auto-shutdown event will only affect pins that have PWM outputs enabled. PSTRXCON: PULSE STEERING CONTROL REGISTER(1) REGISTER 19-6: U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 — — — STRxSYNC STRxD STRxC STRxB STRxA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 STRxSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRxD: Steering Enable bit D 1 = P1D pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1D pin is assigned to port pin bit 2 STRxC: Steering Enable bit C 1 = P1C pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1C pin is assigned to port pin bit 1 STRxB: Steering Enable bit B 1 = P1B pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1B pin is assigned to port pin bit 0 STRxA: Steering Enable bit A 1 = P1A pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1A pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11 and PxM<1:0> = 00. DS41364A-page 208 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 19-18: SIMPLIFIED STEERING BLOCK DIAGRAM STRxA P1A Signal CCPxM1 1 PORT Data 0 P1A pin STRxB CCPxM0 1 PORT Data 0 CCPxM1 1 PORT Data 0 P1C pin TRIS STRxD PORT Data P1B pin TRIS STRxC CCPxM0 TRIS P1D pin 1 0 TRIS Note 1: Port outputs are configured as shown when the CCPxCON register bits PxM<1:0> = 00 and CCPxM<3:2> = 11. 2: Single PWM output requires setting at least one of the STRx bits. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 209 PIC16F193X/LF193X 19.6.7.1 Steering Synchronization The STRxSYNC bit of the PSTRxCON register gives the user two selections of when the steering event will happen. When the STRxSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the P1<D:A> pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin. Figures 19-19 and 19-20 illustrate the timing diagrams of the PWM steering depending on the STRXSYNC setting. When the STRxSYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will always produce a complete PWM waveform. FIGURE 19-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRXSYNC = 0) PWM Period PWM STRx P1<D:A> PORT Data PORT Data P1n = PWM FIGURE 19-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRXSYNC = 1) PWM STRx P1<D:A> PORT Data PORT Data P1n = PWM DS41364A-page 210 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 19-8: REGISTERS ASSOCIATED WITH PWM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page PxM1(1) PxM0(1) DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 184 CCPxAS CCPxASE CCPxAS2 CCPxAS1 CCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 204 CCPTMRS0 C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 185 CCPTMRS1 — — — — — — C5TSEL1 C5TSEL0 186 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 — — STRxSYNC STRxD STRxC STRxB STRxA 208 PxDC6 PxDC5 PxDC4 PxDC3 Name CCPxCON INTCON PRx Timerx Period Register PSTRxCON — PWMxCON PxRSEN TxCON TMRx — 173* TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0 PxDC2 PxDC1 PxDC0 207 TMRxON TxCKPS1 TxCKPS0 175 Timerx Module Register 173 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 91 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 94 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 97 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM. Note 1: Applies to ECCP modules only. * Page provides register information. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 211 PIC16F193X/LF193X NOTES: DS41364A-page 212 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The EUSART module includes the following capabilities: • • • • • • • • • • Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in synchronous modes • Sleep operation The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. FIGURE 20-1: The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: • Automatic detection and calibration of the baud rate • Wake-up on Break reception • 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 20-1 and Figure 20-2. EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXIF TXREG Register 8 MSb TX/CK pin LSb (8) • • • 0 Pin Buffer and Control TRMT SPEN Transmit Shift Register (TSR) TXEN Baud Rate Generator FOSC TX9 n BRG16 +1 SPBRGH ÷n SPBRG Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 © 2008 Microchip Technology Inc. TX9D Preliminary DS41364A-page 213 PIC16F193X/LF193X FIGURE 20-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC SPBRGH SPBRG x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 (8) ••• 7 1 LSb 0 START RX9 ÷n BRG16 Multiplier Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR n FERR RX9D RCREG Register FIFO 8 Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCON) These registers are detailed in Register 20-1, Register 20-2 and Register 20-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output. DS41364A-page 214 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.1 20.1.1.2 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is 8 bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 20-5 for examples of baud rate configurations. The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 20.1.1 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 20-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREG register. 20.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: Transmitting Data A transmission is initiated by writing a character to the TXREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the Stop bit of the previous character has been transmitted. The pending character in the TXREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREG. 20.1.1.3 Transmit Interrupt Flag The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREG. The TXIF flag bit is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXREG. • TXEN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. Note 1: The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 215 PIC16F193X/LF193X 20.1.1.4 TSR Status 20.1.1.6 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 20.1.1.5 1. 2. 3. The TSR register is not mapped in data memory, so it is not available to the user. 4. Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set the EUSART will shift 9 bits out for each character transmitted. The TX9D bit of the TXSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the 8 Least Significant bits into the TXREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG is written. 5. 6. 7. Asynchronous Transmission Set-up: Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 20.3 “EUSART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the 8 Least Significant data bits are an address when the receiver is set for address detection. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission. A special 9-bit Address mode is available for use with multiple receivers. See Section 20.1.2.7 “Address Detection” for more information on the address mode. FIGURE 20-3: ASYNCHRONOUS TRANSMISSION Write to TXREG BRG Output (Shift Clock) Word 1 TX/CK pin Start bit FIGURE 20-4: bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) bit 0 1 TCY Word 1 Transmit Shift Reg. ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG BRG Output (Shift Clock) Word 1 TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 2 Start bit bit 0 1 TCY bit 1 Word 1 bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. DS41364A-page 216 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 20-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 224 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 74 PIR1 77 Name BAUDCON INTCON TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 223 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 225* SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 225* TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 94 SYNC SENDB BRGH TRMT TX9D TRISC TXREG TXSTA EUSART Transmit Data Register CSRC TX9 TXEN 215* 222 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission. * Page provides register information. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 217 PIC16F193X/LF193X 20.1.2 EUSART ASYNCHRONOUS RECEIVER 20.1.2.2 The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 20-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. 20.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: • CREN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the RX/DT I/O pin as an input. Note: When the SPEN bit is set the TX/CK I/O pin is automatically configured as an output, regardless of the state of the corresponding TRIS bit and whether or not the EUSART transmitter is enabled. The PORT latch is disconnected from the output driver so it is not possible to use the TX/CK pin as a general purpose output. Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 20.1.2.4 “Receive Framing Error” for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREG register. Note: 20.1.2.3 If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 20.1.2.5 “Receive Overrun Error” for more information on overrun errors. Receive Interrupts The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: • RCIE interrupt enable bit of the PIE1 register • PEIE peripheral interrupt enable bit of the INTCON register • GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. DS41364A-page 218 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.1.2.4 Receive Framing Error 20.1.2.7 Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the EUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 20.1.2.5 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 20.1.2.6 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 219 PIC16F193X/LF193X 20.1.2.8 1. 2. 3. 4. 5. 6. 7. 8. 9. Asynchronous Reception Set-up: 20.1.2.9 Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 20.3 “EUSART Baud Rate Generator (BRG)”). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Enable reception by setting the CREN bit. The RCIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. Read the RCSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. FIGURE 20-5: Rcv Shift Reg Rcv Buffer Reg. RCIDL This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 20.3 “EUSART Baud Rate Generator (BRG)”). 2. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 3. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 4. Enable 9-bit reception by setting the RX9 bit. 5. Enable address detection by setting the ADDEN bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 8. Read the RCSTA register to get the error flags. The ninth data bit will always be set. 9. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin 9-bit Address Detection Mode Set-up bit 1 bit 7/8 Stop bit Start bit bit 0 Word 1 RCREG bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS41364A-page 220 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 20-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 224 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 74 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 RCREG EUSART Receive Data Register Name BAUDCON INTCON PIE1 218* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 223 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 225* SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 225* TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 94 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 222 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception. * Page provides register information. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 221 PIC16F193X/LF193X 20.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 20-1: The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 8.5 “Internal Clock Modes” for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 20.3.1 “Auto-Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS41364A-page 222 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) REGISTER 20-2: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 223 PIC16F193X/LF193X REGISTER 20-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the RB7/TX/CK pin 0 = Transmit non-inverted data to the RB7/TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care DS41364A-page 224 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.3 EXAMPLE 20-1: EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: F OS C Desired Baud Rate = --------------------------------------------------------------------64 ( [SPBRGH:SPBRG] + 1 ) Solving for SPBRGH:SPBRG: FOSC --------------------------------------------Desired Baud Rate X = --------------------------------------------- – 1 64 The SPBRGH, SPBRG register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXSTA register and the BRG16 bit of the BAUDCON register. In Synchronous mode, the BRGH bit is ignored. Table 20-3 contains the formulas for determining the baud rate. Example 20-1 provides a sample calculation for determining the baud rate and baud rate error. CALCULATING BAUD RATE ERROR 16000000 -----------------------9600 = ------------------------ – 1 64 = [ 25.042 ] = 25 16000000 Calculated Baud Rate = --------------------------64 ( 25 + 1 ) Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in Table 20-3. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. = 9615 Calc. Baud Rate – Desired Baud Rate Error = -------------------------------------------------------------------------------------------Desired Baud Rate ( 9615 – 9600 ) = ---------------------------------- = 0.16% 9600 Writing a new value to the SPBRGH, SPBRG register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 225 PIC16F193X/LF193X TABLE 20-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 FOSC/[16 (n+1)] 1 Legend: FOSC/[4 (n+1)] x = Don’t care, n = value of SPBRGH, SPBRG register pair TABLE 20-4: Name BAUDCON REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 224 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 223 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 225* SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 225* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 222 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator. * Page provides register information. DS41364A-page 226 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 20-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 © 2008 Microchip Technology Inc. Preliminary DS41364A-page 227 PIC16F193X/LF193X TABLE 20-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 — 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz Actual Rate FOSC = 20.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 18.432 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 11.0592 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 71 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — DS41364A-page 228 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 20-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 0.00 26666 6666 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 832 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — — © 2008 Microchip Technology Inc. Preliminary DS41364A-page 229 PIC16F193X/LF193X 20.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDCON register starts the auto-baud calibration sequence (Figure 20-6). While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPBRG begins counting up using the BRG counter clock as shown in Table 20-6. The fifth rising edge will occur on the RX pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPBRGH, SPBRG register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag is set. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the SPBRG register did not overflow by checking for 00h in the SPBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 20-6. During ABD, both the SPBRGH and SPBRG registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPBRGH FIGURE 20-6: Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 20.3.3 “Auto-Wake-up on Break”). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the auto-baud counter starts counting at 1. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPBRGH:SPBRG register pair. TABLE 20-6: BRG COUNTER CLOCK RATES BRG16 BRGH BRG Base Clock BRG ABD Clock 0 0 FOSC/64 FOSC/512 0 1 FOSC/16 FOSC/128 1 0 FOSC/16 FOSC/128 1 FOSC/4 FOSC/32 1 Note: During the ABD sequence, SPBRG and SPBRGH registers are both used as a 16-bit counter, independent of BRG16 setting. AUTOMATIC BAUD RATE CALIBRATION XXXXh BRG Value and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. RX pin 0000h 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRG XXh 1Ch SPBRGH XXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. DS41364A-page 230 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.3.2 AUTO-BAUD OVERFLOW 20.3.3.1 During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRG register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX pin. Upon detecting the fifth RX edge, the hardware will set the RCIF interrupt flag and clear the ABDEN bit of the BAUDCON register. The RCIF flag can be subsequently cleared by reading the RCREG register. The ABDOVF flag of the BAUDCON register can be cleared by software directly. To terminate the auto-baud process before the RCIF flag is set, clear the ABDEN bit then clear the ABDOVF bit of the BAUDCON register. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. 20.3.3 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 20-7), and asynchronously if the device is in Sleep mode (Figure 20-8). The interrupt condition is cleared by reading the RCREG register. Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all ‘0’s. This must be 10 or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Startup Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 231 PIC16F193X/LF193X FIGURE 20-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set. FIGURE 20-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line Note 1 RCIF Sleep Command Executed Note 1: 2: Sleep Ends Cleared due to User Read of RCREG If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. DS41364A-page 232 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.3.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. 5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted. 20.3.5 The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The first method to detect a Break character uses the FERR bit of the RCSTA register and the Received data as indicated by RCREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. The TRMT bit of the TXSTA register indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 20-9 for the timing of the Break character sequence. A Break character has been received when; 20.3.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. FIGURE 20-9: Write to TXREG RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. • RCIF bit is set • FERR bit is set • RCREG = 00h The second method uses the Auto-Wake-up feature described in Section 20.3.3 “Auto-Wake-up on Break”. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCON register before placing the EUSART in Sleep mode. SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit) © 2008 Microchip Technology Inc. Preliminary DS41364A-page 233 PIC16F193X/LF193X 20.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. 20.4.1 SYNCHRONOUS MASTER MODE Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock. 20.4.1.3 Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: The TSR register is not mapped in data memory, so it is not available to the user. 20.4.1.4 Synchronous Master Transmission Set-up: The following bits are used to configure the EUSART for Synchronous Master operation: • • • • • SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. 20.4.1.1 20.4.1.2 2. 3. 4. 5. 6. Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. Synchronous Master Transmission 7. 8. Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 20.3 “EUSART Baud Rate Generator (BRG)”). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXREG register. Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. DS41364A-page 234 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 20-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. FIGURE 20-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 2 bit 1 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 20-7: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 ABDOVF GIE PIE1 PIR1 BAUDCON INTCON Bit 2 Bit 1 Bit 0 Register on Page BRG16 — WUE ABDEN 224 IOCIE TMR0IF INTF IOCIF 73 TXIE SSPIE CCP1IE TMR2IE TMR1IE 74 TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 Bit 5 Bit 4 Bit 3 RCIDL — SCKP PEIE TMR0IE INTE TMR1GIE ADIE RCIE TMR1GIF ADIF RCIF RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 223 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 225* SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 225* TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISC TXREG TXSTA Legend: * EUSART Transmit Data Register CSRC TX9 TXEN 94 215* SYNC SENDB BRGH TRMT TX9D 222 x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Transmission. Page provides register information. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 235 PIC16F193X/LF193X 20.4.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are unread characters in the receive FIFO. 20.4.1.6 Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. 20.4.1.7 Receive Overrun Error set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. 20.4.1.8 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift 9-bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. 20.4.1.9 Synchronous Master Reception Set-up: 1. Initialize the SPBRGH, SPBRG register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set bit RX9. 6. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 7. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is DS41364A-page 236 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 20-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 224 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 74 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 RCREG EUSART Receive Data Register RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 223 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 225* SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 225* TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 94 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 222 Name BAUDCON INTCON 218* Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception. * Page provides register information. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 237 PIC16F193X/LF193X 20.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. 20.4.2.1 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 5. 20.4.2.2 1. EUSART Synchronous Slave Transmit The operation of the Synchronous Master and Slave modes are identical (see Section 20.4.1.3 “Synchronous Master Transmission”), except in the case of the Sleep mode. 2. 3. 4. 5. 6. 7. TABLE 20-9: Name BAUDCON The first character will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. Synchronous Slave Transmission Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the CREN and SREN bits. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant 8 bits to the TXREG register. REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 ABDOVF Bit 2 Bit 1 Bit 0 Register on Page BRG16 — WUE ABDEN 224 IOCIE TMR0IF INTF IOCIF 73 74 Bit 5 Bit 4 Bit 3 RCIDL — SCKP INTE GIE PEIE TMR0IE PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 223 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 94 INTCON TXREG TXSTA EUSART Transmit Data Register CSRC TX9 TXEN 215* SYNC SENDB BRGH TRMT TX9D 222 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. * Page provides register information. DS41364A-page 238 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.4.2.3 EUSART Synchronous Slave Reception 20.4.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 20.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 1. 2. 3. 4. 5. 6. 7. 8. Synchronous Slave Reception Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name BAUDCON Bit 7 Bit 6 ABDOVF Bit 2 Bit 1 Bit 0 Register on Page BRG16 — WUE ABDEN 224 IOCIE TMR0IF INTF IOCIF 73 74 Bit 5 Bit 4 Bit 3 RCIDL — SCKP INTE GIE PEIE TMR0IE PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF RCREG EUSART Receive Data Register INTCON 77 218* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 223 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 94 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 222 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception. * Page provides register information. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 239 PIC16F193X/LF193X 20.5 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 20.5.1 SYNCHRONOUS RECEIVE DURING SLEEP To receive during Sleep, all the following conditions must be met before entering Sleep mode: • RCSTA and TXSTA Control registers must be configured for Synchronous Slave Reception (see Section 20.4.2.4 “Synchronous Slave Reception Set-up:”). • If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. • The RCIF interrupt flag must be cleared by reading RCREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set. Thereby, waking the processor from Sleep. 20.5.2 SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: • RCSTA and TXSTA Control registers must be configured for Synchronous Slave Transmission (see Section 20.4.2.2 “Synchronous Slave Transmission Set-up:”). • The TXIF interrupt flag must be cleared by writing the output data to the TXREG, thereby filling the TSR and transmit buffer. • If interrupts are desired, set the TXIE bit of the PIE1 register and the PEIE bit of the INTCON register. • Interrupt enable bits TXIE of the PIE1 register and PEIE of the INTCON register must set. Upon entering Sleep mode, the device will be ready to accept clocks on TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and the TXIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXREG is available to accept another character for transmission, which will clear the TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE global interrupt enable bit is also set then the Interrupt Service Routine at address 0004h will be called. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE global interrupt enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. DS41364A-page 240 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.0 LIQUID CRYSTAL DISPLAY (LCD) DRIVER MODULE The Liquid Crystal Display (LCD) driver module generates the timing control to drive a static or multiplexed LCD panel. In the PIC16F193X/LF193X device, the module drives the panels of up to four commons and up to 24 segments. The LCD module also provides control of the LCD pixel data. • Segment pins up to: - 16 (PIC16F1933/1936/1938/ PIC16LF1933/1936/1938) - 24 (PIC16F1934/1937/1939/ PIC16LF1934/1937/1939) • Static, 1/2 or 1/3 LCD Bias Note: The LCD driver module supports: • Direct driving of LCD panel • Three LCD clock sources with selectable prescaler • Up to four common pins: - Static (1 common) - 1/2 multiplex (2 commons) - 1/3 multiplex (3 commons) - 1/4 multiplex (4 commons) FIGURE 21-1: 21.1 COM3 and SEG15 share the same physical pin on the PIC16F1933/1936/1938/ PIC16LF1933/1936/1938, therefore SEG15 is not available when using 1/4 multiplex displays. LCD Registers The module contains the following registers: • • • • • LCD Control register (LCDCON) LCD Phase register (LCDPS) LCD Reference Ladder register (LCDRL) LCD Contrast Control register (LCDCST) LCD Reference Voltage Control register (LCDREF) • Up to 3 LCD Segment Enable registers (LCDSEn) • Up to 12 LCD data registers (LCDDATAn) LCD DRIVER MODULE BLOCK DIAGRAM Data Bus SEG<23:0>(1, 3) LCDDATAx To I/O Pads(1) MUX Registers Timing Control LCDCON COM<3:0>(3) LCDPS To I/O Pads(1) LCDSEn FOSC/256 T1OSC LFINTOSC Note 1: 2: 3: Clock Source Select and Prescaler These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of the LCD module. SEG<23:0> on PIC16F1934/1937/1939, SEG<15:0> on PIC16F1933/1936/1938/ PIC16LF1933/1936/1938. COM3 and SEG15 share the same physical pin on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938, therefore SEG15 is not available when using 1/4 multiplex displays. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 241 PIC16F193X/LF193X TABLE 21-1: LCD SEGMENT AND DATA REGISTERS # of LCD Registers Device Segment Enable Data PIC16F1933/1936/1938/ PIC16LF1933/1936/1938 2 8 PIC16F1934/1937/1939/ PIC16LF1934/1937/1939 3 12 The LCDCON register (Register 21-1) controls the operation of the LCD driver module. The LCDPS register (Register 21-2) configures the LCD clock source prescaler and the type of waveform; Type-A or Type-B. The LCDSE registers (Register 21-5) configure the functions of the port pins. The following LCDSE registers are available: • LCDSE0 SE<7:0> • LCDSE1 SE<15:8> • LCDSE2 SE<23:16>(1) Note 1: PIC16F1934/1937/1939/ PIC16LF1934/1937/1939 only. Once the module is initialized for the LCD panel, the individual bits of the LCDDATA<11:0> registers are cleared/set to represent a clear/dark pixel, respectively: • • • • • • • • • • • • LCDDATA0 LCDDATA1 LCDDATA2 LCDDATA3 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7 LCDDATA8 LCDDATA9 LCDDATA10 LCDDATA11 SEG<7:0>COM0 SEG<15:8>COM0 SEG<23:16>COM0(1) SEG<7:0>COM1 SEG<15:8>COM1 SEG<23:16>COM1(1) SEG<7:0>COM2 SEG<15:8>COM2 SEG<23:16>COM2(1) SEG<7:0>COM3 SEG<15:8>COM3 SEG<23:16>COM3(1) Note 1: PIC16F1934/1937/1939/ PIC16LF1934/1937/1939 only. As an example, Register 21-6. LCDDATAx is detailed in Once the module is configured, the LCDEN bit of the LCDCON register is used to enable or disable the LCD module. The LCD panel can also operate during Sleep by clearing the SLPEN bit of the LCDCON register. DS41364A-page 242 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 21-1: LCDCON: LIQUID CRYSTAL DISPLAY (LCD) CONTROL REGISTER R/W-0/0 R/W-0/0 R/C-0/0 U-0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7 LCDEN: LCD Driver Enable bit 1 = LCD driver module is enabled 0 = LCD driver module is disabled bit 6 SLPEN: LCD Driver Enable in Sleep Mode bit 1 = LCD driver module is disabled in Sleep mode 0 = LCD driver module is enabled in Sleep mode bit 5 WERR: LCD Write Failed Error bit 1 = LCDDATAx register written while the WA bit of the LCDPS register = 0 (must be cleared in software) 0 = No LCD write error bit 4 Unimplemented: Read as ‘0’ bit 3-2 CS<1:0>: Clock Source Select bits 00 = FOSC/256 01 = T1OSC (Timer1) 1x = LFINTOSC (31 kHz) bit 1-0 LMUX<1:0>: Commons Select bits Maximum Number of Pixels LMUX<1:0> Multiplex PIC16F1933/1936/1938/ PIC16LF1933/1936/1938 PIC16F1934/1937/1939/ PIC16LF1934/1937/1939 Bias 00 Static (COM0) 16 24 Static 01 1/2 (COM<1:0>) 32 48 1/2 or 1/3 10 1/3 (COM<2:0>) 48 72 1/2 or 1/3 96 1/3 11 Note 1: 1/4 (COM<3:0>) 60 (1) On these devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 64 pixels. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 243 PIC16F193X/LF193X REGISTER 21-2: LCDPS: LCD PHASE REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7 WFT: Waveform Type bit 1 = Type-B phase changes on each frame boundary 0 = Type-A phase changes within each common type bit 6 BIASMD: Bias Mode Select bit When LMUX<1:0> = 00: 0 = Static Bias mode (do not set this bit to ‘1’) When LMUX<1:0> = 01: 1 = 1/2 Bias mode 0 = 1/3 Bias mode When LMUX<1:0> = 10: 1 = 1/2 Bias mode 0 = 1/3 Bias mode When LMUX<1:0> = 11: 0 = 1/3 Bias mode (do not set this bit to ‘1’) bit 5 LCDA: LCD Active Status bit 1 = LCD driver module is active 0 = LCD driver module is inactive bit 4 WA: LCD Write Allow Status bit 1 = Write into the LCDDATAx registers is allowed 0 = Write into the LCDDATAx registers is not allowed bit 3-0 LP<3:0>: LCD Prescaler Selection bits 1111 = 1:16 1110 = 1:15 1101 = 1:14 1100 = 1:13 1011 = 1:12 1010 = 1:11 1001 = 1:10 1000 = 1:9 0111 = 1:8 0110 = 1:7 0101 = 1:6 0100 = 1:5 0011 = 1:4 0010 = 1:3 0001 = 1:2 0000 = 1:1 DS41364A-page 244 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 21-3: LCDREF: LCD REFERENCE VOLTAGE CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 LCDIRE LCDIRS LCDIRI — VLCD3PE VLCD2PE VLCD1PE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7 LCDIRE: LCD Internal Reference Enable bit 1 = Internal LCD Reference is enabled and connected to the Internal Contrast Control circuit 0 = Internal LCD Reference is disabled bit 6 LCDIRS: LCD Internal Reference Source bit If LCDIRE = 1: 0 = Internal LCD Contrast Control is powered by VDD 1 = Internal LCD Contrast Control is powered by a 3.072V output of the FVR. If LCDIRE = 0: Internal LCD Contrast Control is unconnected. LCD bandgap buffer is disabled. bit 5 LCDIRI: LCD Internal Reference Ladder Idle Enable bit Allows the Internal FVR buffer to shut down when the LCD Reference Ladder is in power mode ‘B’ 1 = When the LCD Reference Ladder is in power mode ‘B’, the LCD Internal FVR buffer is disabled. 0 = The LCD Internal FVR Buffer ignores the LCD Reference Ladder Power mode. bit 4 Unimplemented: Read as ‘0’ bit 3 VLCD3PE: VLCD3 Pin Enable bit 1 = The VLCD3 pin is connected to the internal bias voltage LCDBIAS3(1) 0 = The VLCD3 pin is not connected bit 2 VLCD2PE: VLCD2 Pin Enable bit 1 = The VLCD2 pin is connected to the internal bias voltage LCDBIAS2(1) 0 = The VLCD2 pin is not connected bit 1 VLCD1PE: VLCD1 Pin Enable bit 1 = The VLCD1 pin is connected to the internal bias voltage LCDBIAS1(1) 0 = The VLCD1 pin is not connected bit 0 Unimplemented: Read as ‘0’ Note 1: Normal pin controls of TRISx and ANSELx are unaffected. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 245 PIC16F193X/LF193X REGISTER 21-4: LCDCST: LCD CONTRAST CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — — LCDCST2 LCDCST1 LCDCST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LCDCST<2:0>: LCD Contrast Control bits Selects the resistance of the LCD contrast control resistor ladder Bit Value = Resistor ladder 000 = Minimum Resistance (Maximum contrast). Resistor ladder is shorted. 001 = Resistor ladder is at 1/7th of maximum resistance 010 = Resistor ladder is at 2/7th of maximum resistance 011 = Resistor ladder is at 3/7th of maximum resistance 100 = Resistor ladder is at 4/7th of maximum resistance 101 = Resistor ladder is at 5/7th of maximum resistance 110 = Resistor ladder is at 6/7th of maximum resistance 111 = Resistor ladder is at maximum resistance (Minimum contrast). DS41364A-page 246 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 21-5: LCDSEn: LCD SEGMENT ENABLE REGISTERS R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SEn SEn SEn SEn SEn SEn SEn SEn bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SEn: Segment Enable bits 1 = Segment function of the pin is enabled 0 = I/O function of the pin is enabled REGISTER 21-6: R/W-x/u LCDDATAx: LCD DATA REGISTERS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SEGx-COMy: Pixel On bits 1 = Pixel on (dark) 0 = Pixel off (clear) © 2008 Microchip Technology Inc. Preliminary DS41364A-page 247 PIC16F193X/LF193X 21.2 LCD Clock Source Selection Using bits CS<1:0> of the LCDCON register can select any of these clock sources. The LCD module has 3 possible clock sources: 21.2.1 • FOSC/256 • T1OSC • LFINTOSC LCD PRESCALER A 4-bit counter is available as a prescaler for the LCD clock. The prescaler is not directly readable or writable; its value is set by the LP<3:0> bits of the LCDPS register, which determine the prescaler assignment and prescale ratio. The first clock source is the system clock divided by 256 (FOSC/256). This divider ratio is chosen to provide about 1 kHz output when the system clock is 8 MHz. The divider is not programmable. Instead, the LCD prescaler bits LP<3:0> of the LCDPS register are used to set the LCD frame clock rate. The prescale values are selectable from 1:1 through 1:16. The second clock source is the T1OSC. This also gives about 1 kHz when a 32.768 kHz crystal is used with the Timer1 oscillator. To use the Timer1 oscillator as a clock source, the T1OSCEN bit of the T1CON register should be set. The third clock source is the 31 kHz LFINTOSC, which provides approximately 1 kHz output. The second and third clock sources may be used to continue running the LCD while the processor is in Sleep. FOSC LCD CLOCK GENERATION To Reference Ladder Control ÷256 T1OSC 32 kHz Crystal Osc. Static ÷2 1/2 5 4-bit Prog Prescaler ÷32 ÷1, 2, 3, 4 Ring Counter 1/3, 1/4 LFINTOSC Nominal = 31 kHz LP<3:0> (LCDPS<3:0>) CS<1:0> (LCDCON<3:2>) DS41364A-page 248 ÷4 COM0 COM1 COM2 COM3 FIGURE 21-2: LMUX<1:0> (LCDCON<1:0>) LMUX<1:0> (LCDCON<1:0>) Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.3 TABLE 21-2: LCD Bias Voltage Generation The LCD module can be configured for one of three bias types: • Static Bias (2 voltage levels: VSS and VLCD) • 1/2 Bias (3 voltage levels: VSS, 1/2 VLCD and VLCD) • 1/3 Bias (4 voltage levels: VSS, 1/3 VLCD, 2/3 VLCD and VLCD) FIGURE 21-3: LCD BIAS VOLTAGES Static Bias 1/2 Bias 1/3 Bias LCD Bias 0 VSS VSS VSS LCD Bias 1 — 1/2 VDD 1/3 VDD LCD Bias 2 — 1/2 VDD 2/3 VDD LCD Bias 3 VLCD3 VLCD3 VLCD3 So that the user is not forced to place external components and use up to three pins for bias voltage generation, internal contrast control and an internal reference ladder are provided internally to the PIC16F193X/LF193X. Both of these features may be used in conjunction with the external VLCD<3:1> pins, to provide maximum flexibility. Refer to Figure 21-3. LCD BIAS VOLTAGE GENERATION BLOCK DIAGRAM LCDIRE LCDIRS LCDA VDD 1.024V from FVR 3.072V x3 LCDRLP1 LCDRLP0 LCDIRE LCDIRS LCDA LCDCST<2:0> VLCD3PE LCDA VLCD3 lcdbias3 VLCD2PE VLCD2 lcdbias2 BIASMD VLCD1PE VLCD1 lcdbias1 lcdbias0 © 2008 Microchip Technology Inc. Preliminary DS41364A-page 249 PIC16F193X/LF193X 21.4 21.4.2 LCD Bias Internal Reference Ladder The internal reference ladder can be used to divide the LCD bias voltage two or three equally spaced voltages that will be supplied to the LCD segment pins. To create this, the reference ladder consists of three matched resistors. Refer to Figure 21-3. POWER MODES The internal reference ladder may be operated in one of three power modes. This allows the user to trade off LCD contrast for power in the specific application. The larger the LCD glass, the more capacitance is present on a physical LCD segment, requiring more current to maintain the same contrast level. When in 1/2 Bias mode (BIASMD = 1), then the middle resistor of the ladder is shorted out so that only two voltages are generated. The current consumption of the ladder is higher in this mode, with the one resistor removed. Three different power modes are available, LP, MP and HP. The internal reference ladder can also be turned off for applications that wish to provide an external ladder or to minimize power consumption. Disabling the internal reference ladder results in all of the ladders being disconnected, allowing external voltages to be supplied. TABLE 21-3: Whenever the LCD module is inactive (LCDA = 0), the internal reference ladder will be turned off. 21.4.1 Power Mode BIAS MODE INTERACTION LCD INTERNAL LADDER POWER MODES (1/3 BIAS) Nominal Resistance of Entire Ladder Nominal IDD 3 Mohm 300 kohm 30 kohm 1 µA 10 µA 100 µA Low Medium High DS41364A-page 250 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.4.3 AUTOMATIC POWER MODE SWITCHING The LCDLAD register allows switching between two power modes, designated ‘A’ and ‘B’. ‘A’ Power mode is active for a programmable time, beginning at the time win the LCD segments transition. ‘B’ Power mode is the remaining time before the segments or commons change again. The LRLAT<2:0> bits select how long, if any, that the ‘A’ Power mode is active. Refer to Figure 21-4. As an LCD segment is electrically only a capacitor, current is drawn only during the interval where the voltage is switching. To minimize total device current, the LCD internal reference ladder can be operated in a different power mode for the transition portion of the duration. This is controlled by the LCDRL Register (Register 21-7). FIGURE 21-4: To implement this, the 5-bit prescaler used to divide the 32 kHz clock down to the LCD controller’s 1 kHz base rate is used to select the power mode. LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE A Single Segment Time 32kHz_clk cnt[4:0] ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F ‘H00 ‘H01 lcd_clk ‘H3 LRLAT[2:0] Segment Data LRLAT<2:0> Power Mode FIGURE 21-5: Power Mode A Power Mode B Mode A LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE B Single Segment Time 32kHz_clk cnt[4:0] ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H1E ‘H1F ‘H00 ‘H01 lcd_clk ‘H3 LRLAT[2:0] Segment Data LRLAT<2:0> Power Mode Power Mode A © 2008 Microchip Technology Inc. Power Mode B Preliminary Mode A DS41364A-page 251 PIC16F193X/LF193X REGISTER 21-7: LCDRL: LCD REFERENCE LADDER CONTROL REGISTERS R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 LRLAP1 LRLAP0 LRLBP1 LRLBP0 — LRLAT2 LRLAT1 LRLAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits During Time interval A (Refer to Figure 21-4): 00 = Internal LCD Reference Ladder is powered down and unconnected 01 = Internal LCD Reference Ladder is powered in low-power mode 10 = Internal LCD Reference Ladder is powered in medium-power mode 11 = Internal LCD Reference Ladder is powered in high-power mode bit 5-4 LRLBP<1:0>: LCD Reference Ladder B Time Power Control bits During Time interval B (Refer to Figure 21-4): 00 = Internal LCD Reference Ladder is powered down and unconnected 01 = Internal LCD Reference Ladder is powered in low-power mode 10 = Internal LCD Reference Ladder is powered in medium-power mode 11 = Internal LCD Reference Ladder is powered in high-power mode bit 3 Unimplemented: Read as ‘0’ bit 2-0 LRLAT<2:0>: LCD Reference Ladder A Time interval control bits Sets the number of 32 kHz clocks that the A Time interval power mode is active For type A waveforms (WFT = 0): 000 = Internal LCD Reference Ladder is always in ‘B’ power mode 001 = Internal LCD Reference Ladder is in ‘A’ power mode for 1 clock and ‘B’ power mode for 15 clocks 010 = Internal LCD Reference Ladder is in ‘A’ power mode for 2 clocks and ‘B’ power mode for 14 clocks 011 = Internal LCD Reference Ladder is in ‘A’ power mode for 3 clocks and ‘B’ power mode for 13 clocks 100 = Internal LCD Reference Ladder is in ‘A’ power mode for 4 clocks and ‘B’ power mode for 12 clocks 101 = Internal LCD Reference Ladder is in ‘A’ power mode for 5 clocks and ‘B’ power mode for 11 clocks 110 = Internal LCD Reference Ladder is in ‘A’ power mode for 6 clocks and ‘B’ power mode for 10 clocks 111 = Internal LCD Reference Ladder is in ‘A’ power mode for 7 clocks and ‘B’ power mode for 9 clocks For type B waveforms (WFT = 1): 000 = Internal LCD Reference Ladder is always in ‘B’ power mode. 001 = Internal LCD Reference Ladder is in ‘A’ power mode for 1 clock and ‘B’ power mode for 31 clocks 010 = Internal LCD Reference Ladder is in ‘A’ power mode for 2 clocks and ‘B’ power mode for 30 clocks 011 = Internal LCD Reference Ladder is in ‘A’ power mode for 3 clocks and ‘B’ power mode for 29 clocks 100 = Internal LCD Reference Ladder is in ‘A’ power mode for 4 clocks and ‘B’ power mode for 28 clocks 101 = Internal LCD Reference Ladder is in ‘A’ power mode for 5 clocks and ‘B’ power mode for 27 clocks 110 = Internal LCD Reference Ladder is in ‘A’ power mode for 6 clocks and ‘B’ power mode for 26 clocks 111 = Internal LCD Reference Ladder is in ‘A’ power mode for 7 clocks and ‘B’ power mode for 25 clocks DS41364A-page 252 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.4.4 CONTRAST CONTROL The LCD contrast control circuit consists of a seven-tap resistor ladder, controlled by the LCDCST bits. Refer to Figure 21-6. FIGURE 21-6: The contrast control circuit is used to decrease the output voltage of the signal source by a total of approximately 10%, when LCDCST = 111. Whenever the LCD module is inactive (LCDA = 0), the contrast control ladder will be turned off (open). INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM VDDIO 7 Stages R R R R 3.072V Analog MUX From FVR Buffer 7 To top of Reference Ladder 0 LCDCST<2:0> 3 Internal Reference 21.4.5 Contrast control 21.4.6 INTERNAL REFERENCE Under firmware control, an internal reference for the LCD bias voltages can be enabled. When enabled, the source of this voltage can be either VDDIO or a voltage 3 times the main fixed voltage reference (3.072V). When no internal reference is selected, the LCD contrast control circuit is disabled and LCD bias must be provided externally. Whenever the LCD module is inactive (LCDA = 0), the internal reference will be turned off. When the internal reference is enabled and the Fixed Voltage Reference is selected, the LCDIRI bit can be used to minimize power consumption by tieing into the LCD reference ladder automatic power mode switching. When LCDIRI = 1, the power mode that the internal LCD reference ladder enables the buffer when in power mode ‘A’ and disables it when in power mode ‘B’. VLCD<3:1> PINS The VLCD<3:1> pins provide the ability for an external LCD bias network to be used instead of the internal ladder. Use of the VLCD<3:1> pins does not prevent use of the internal ladder. Each VLCD pin has an independent control in the LCDREF register (Register 21-3), allowing access to any or all of the LCD Bias signals. This architecture allows for maximum flexibility in different applications For example, the VLCD<3:1> pins may be used to add capacitors to the internal reference ladder, increasing the drive capacity. For applications where the internal contrast control is insufficient, the firmware can choose to only enable the VLCD3 pin, allowing an external contrast control circuit to use the internal reference divider. . Note: The LCD module automatically turns on the fixed voltage reference when needed. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 253 PIC16F193X/LF193X 21.5 TABLE 21-5: LCD Multiplex Types The LCD driver module can be configured into one of four multiplex types: • • • • Static (only COM0 is used) 1/2 multiplex (COM<1:0> are used) 1/3 multiplex (COM<2:0> are used) 1/4 multiplex (COM<3:0> are used) If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. If the pin is a COM drive, then the TRIS setting of that pin is overridden. TABLE 21-4: COMMON PIN USAGE LMUX Multiplex <1:0> COM3 COM2 Multiplex Frame Frequency = Static Clock source/(4 x 1 x (LP<3:0> + 1)) 1/2 Clock source/(2 x 2 x (LP<3:0> + 1)) 1/3 Clock source/(1 x 3 x (LP<3:0> + 1)) 1/4 The LMUX<1:0> bit setting of the LCDCON register decides which of the LCD common pins are used (see Table 21-4 for details). FRAME FREQUENCY FORMULAS Note: Clock source/(1 x 4 x (LP<3:0> + 1)) Clock source is FOSC/256, T1OSC or LFINTOSC. TABLE 21-6: APPROXIMATE FRAME FREQUENCY (IN Hz) USING FOSC @ 8 MHz, TIMER1 @ 32.768 kHz OR LFINTOSC LP<3:0> Static 1/2 1/3 1/4 COM1 2 85 85 114 85 64 64 85 64 Static 00 Unused Unused Unused 3 1/2 01 Unused Unused Active 4 51 51 68 51 43 43 57 43 1/3 10 Unused Active Active 5 1/4 11 Active Active Active 6 37 37 49 37 7 32 32 43 32 21.6 Segment Enables The LCDSEn registers are used to select the pin function for each segment pin. The selection allows each pin to operate as either an LCD segment driver or as one of the pin’s alternate functions. To configure the pin as a segment pin, the corresponding bits in the LCDSEn registers must be set to ‘1’. If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. Any bit set in the LCDSEn registers overrides any bit settings in the corresponding TRIS register. Note: 21.7 On a Power-on Reset, these pins are configured as normal I/O, not LCD pins. Pixel Control The LCDDATAx registers contain bits which define the state of each pixel. Each bit defines one unique pixel. Register 21-6 shows the correlation of each bit in the LCDDATAx registers to the respective common and segment signals. Any LCD pixel location not being used for display can be used as general purpose RAM. 21.8 LCD Frame Frequency The rate at which the COM and SEG outputs change is called the LCD frame frequency. DS41364A-page 254 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 21-7: LCD Function LCD SEGMENT MAPPING WORKSHEET COM0 LCDDATAx Address COM1 LCD Segment LCDDATAx Address COM2 LCD Segment LCDDATAx Address COM3 LCD Segment LCDDATAx Address SEG0 LCDDATA0, 0 LCDDATA3, 0 LCDDATA6, 0 LCDDATA9, 0 SEG1 LCDDATA0, 1 LCDDATA3, 1 LCDDATA6, 1 LCDDATA9, 1 SEG2 LCDDATA0, 2 LCDDATA3, 2 LCDDATA6, 2 LCDDATA9, 2 SEG3 LCDDATA0, 3 LCDDATA3, 3 LCDDATA6, 3 LCDDATA9, 3 SEG4 LCDDATA0, 4 LCDDATA3, 4 LCDDATA6, 4 LCDDATA9, 4 SEG5 LCDDATA0, 5 LCDDATA3, 5 LCDDATA6, 5 LCDDATA9, 5 SEG6 LCDDATA0, 6 LCDDATA3, 6 LCDDATA6, 6 LCDDATA9, 6 SEG7 LCDDATA0, 7 LCDDATA3, 7 LCDDATA6, 7 LCDDATA9, 7 SEG8 LCDDATA1, 0 LCDDATA4, 0 LCDDATA7, 0 LCDDATA10, 0 SEG9 LCDDATA1, 1 LCDDATA4, 1 LCDDATA7, 1 LCDDATA10, 1 SEG10 LCDDATA1, 2 LCDDATA4, 2 LCDDATA7, 2 LCDDATA10, 2 SEG11 LCDDATA1, 3 LCDDATA4, 3 LCDDATA7, 3 LCDDATA10, 3 SEG12 LCDDATA1, 4 LCDDATA4, 4 LCDDATA7, 4 LCDDATA10, 4 SEG13 LCDDATA1, 5 LCDDATA4, 5 LCDDATA7, 5 LCDDATA10, 5 SEG14 LCDDATA1, 6 LCDDATA4, 6 LCDDATA7, 6 LCDDATA10, 6 SEG15 LCDDATA1, 7 LCDDATA4, 7 LCDDATA7, 7 LCDDATA10, 7 SEG16 LCDDATA2, 0 LCDDATA5, 0 LCDDATA8, 0 LCDDATA11, 0 SEG17 LCDDATA2, 1 LCDDATA5, 1 LCDDATA8, 1 LCDDATA11, 1 SEG18 LCDDATA2, 2 LCDDATA5, 2 LCDDATA8, 2 LCDDATA11, 2 SEG19 LCDDATA2, 3 LCDDATA5, 3 LCDDATA8, 3 LCDDATA11, 3 SEG20 LCDDATA2, 4 LCDDATA5, 4 LCDDATA8, 4 LCDDATA11, 4 SEG21 LCDDATA2, 5 LCDDATA5, 5 LCDDATA8, 5 LCDDATA11, 5 SEG22 LCDDATA2, 6 LCDDATA5, 6 LCDDATA8, 6 LCDDATA11, 6 SEG23 LCDDATA2, 7 LCDDATA5, 7 LCDDATA8, 7 LCDDATA11, 7 © 2008 Microchip Technology Inc. Preliminary LCD Segment DS41364A-page 255 PIC16F193X/LF193X 21.9 LCD Waveform Generation LCD waveforms are generated so that the net AC voltage across the dark pixel should be maximized and the net AC voltage across the clear pixel should be minimized. The net DC voltage across any pixel should be zero. The COM signal represents the time slice for each common, while the SEG contains the pixel data. The pixel signal (COM-SEG) will have no DC component and it can take only one of the two RMS values. The higher RMS value will create a dark pixel and a lower RMS value will create a clear pixel. The LCDs can be driven by two types of waveform: Type-A and Type-B. In Type-A waveform, the phase changes within each common type, whereas in Type-B waveform, the phase changes on each frame boundary. Thus, Type-A waveform maintains 0 VDC over a single frame, whereas Type-B waveform takes two frames. Note 1: If Sleep has to be executed with LCD Sleep disabled (LCDCON<SLPEN> is ‘1’), then care must be taken to execute Sleep only when VDC on all the pixels is ‘0’. 2: When the LCD clock source is FOSC/256, if Sleep is executed, irrespective of the LCDCON<SLPEN> setting, the LCD immediately goes into Sleep. Thus, take care to see that VDC on all pixels is ‘0’ when Sleep is executed. As the number of commons increases, the delta between the two RMS values decreases. The delta represents the maximum contrast that the display can have. Figure 21-7 through Figure 21-17 provide waveforms for static, half-multiplex, 1/3-multiplex and 1/4-multiplex drives for Type-A and Type-B waveforms. FIGURE 21-7: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE V1 COM0 V0 COM0 V1 SEG0 V0 V1 SEG1 V0 V1 V0 COM0-SEG0 -V1 COM0-SEG1 V0 DS41364A-page 256 SEG1 SEG0 SEG2 SEG7 SEG6 SEG5 SEG4 SEG3 1 Frame Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 21-8: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM1 V2 COM1 COM0 V1 V0 V2 V1 SEG0 V0 V2 V1 SEG1 V2 SEG1 SEG0 SEG2 SEG3 V0 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame © 2008 Microchip Technology Inc. Preliminary DS41364A-page 257 PIC16F193X/LF193X FIGURE 21-9: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 V1 COM0 COM1 V0 COM0 V2 COM1 V1 V0 V2 SEG0 V1 SEG1 SEG0 SEG2 SEG3 V0 V2 SEG1 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames DS41364A-page 258 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 21-10: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 COM1 V0 V3 COM0 V2 COM1 V1 V0 V3 V2 SEG0 V1 V0 SEG1 SEG0 SEG2 SEG3 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame © 2008 Microchip Technology Inc. Preliminary -V3 DS41364A-page 259 PIC16F193X/LF193X FIGURE 21-11: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 COM1 V0 V3 COM0 V2 COM1 V1 V0 V3 V2 SEG0 V1 V0 SEG1 SEG0 SEG2 SEG3 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames DS41364A-page 260 Preliminary -V3 © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 21-12: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 V2 COM2 COM1 V1 V0 COM1 V2 COM0 COM2 V1 V0 V2 SEG0 SEG2 V1 V0 V2 V1 SEG0 SEG1 SEG2 SEG1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame © 2008 Microchip Technology Inc. Preliminary DS41364A-page 261 PIC16F193X/LF193X FIGURE 21-13: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM2 V2 COM1 V1 COM1 V0 COM0 V2 COM2 V1 V0 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 V2 SEG1 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames DS41364A-page 262 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 21-14: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 SEG2 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 -V3 1 Frame © 2008 Microchip Technology Inc. Preliminary DS41364A-page 263 PIC16F193X/LF193X FIGURE 21-15: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 -V3 2 Frames DS41364A-page 264 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 21-16: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 SEG0 SEG1 COM0 1 Frame © 2008 Microchip Technology Inc. Preliminary DS41364A-page 265 PIC16F193X/LF193X FIGURE 21-17: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 SEG0 SEG1 COM0 2 Frames DS41364A-page 266 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.10 LCD Interrupts The LCD module provides an interrupt in two cases. An interrupt when the LCD controller goes from active to inactive controller. An interrupt also provides unframe boundaries for Type B waveform. The LCD timing generation provides an interrupt that defines the LCD frame timing. 21.10.1 LCD INTERRUPT ON MODULE SHUTDOWN An LCD interrupt is generated when the module completes shutting down (LCDA goes from ‘1’ to ‘0’). 21.10.2 LCD FRAME INTERRUPTS A new frame is defined to begin at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes accessing all pixel data required for a frame. This will occur at a fixed interval before the frame boundary (TFINT), as shown in Figure 21-18. The LCD controller will begin to access data for the next frame within the interval from the interrupt to when the controller begins to access data after the interrupt (TFWR). New data must be written within TFWR, as this is when the LCD controller will begin to access the data for the next frame. When the LCD driver is running with Type-B waveforms and the LMUX<1:0> bits are not equal to ‘00’ (static drive), there are some additional issues that must be addressed. Since the DC voltage on the pixel takes two frames to maintain zero volts, the pixel data must not change between subsequent frames. If the pixel data were allowed to change, the waveform for the odd frames would not necessarily be the complement of the waveform generated in the even frames and a DC component would be introduced into the panel. Therefore, when using Type-B waveforms, the user must synchronize the LCD pixel updates to occur within a subframe after the frame interrupt. To correctly sequence writing while in Type-B, the interrupt will only occur on complete phase intervals. If the user attempts to write when the write is disabled, the WERR bit of the LCDCON register is set and the write does not occur. Note: The LCD frame interrupt is not generated when the Type-A waveform is selected and when the Type-B with no multiplex (static) is selected. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 267 PIC16F193X/LF193X FIGURE 21-18: WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE (EXAMPLE – TYPE-B, NON-STATIC) LCD Interrupt Occurs Controller Accesses Next Frame Data COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 V3 V2 V1 V0 COM3 2 Frames TFINT Frame Boundary Frame Boundary TFWR Frame Boundary TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2 TFINT = (TFWR/2 – (2 TCY + 40 ns)) → minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns) (TFWR/2 – (1 TCY + 40 ns)) → maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns) DS41364A-page 268 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.11 Operation During Sleep The LCD module can operate during Sleep. The selection is controlled by bit SLPEN of the LCDCON register. Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep. If a SLEEP instruction is executed and SLPEN = 1, the LCD module will cease all functions and go into a very low-current Consumption mode. The module will stop operation immediately and drive the minimum LCD voltage on both segment and common lines. Figure 21-19 shows this operation. The LCD module can be configured to operate during Sleep. The selection is controlled by bit SLPEN of the LCDCON register. Clearing SLPEN and correctly configuring the LCD module clock will allow the LCD module to operate during Sleep. Setting SLPEN and correctly executing the LCD module shutdown will disable the LCD module during Sleep and save power. If a SLEEP instruction is executed and SLPEN = 1, the LCD module will immediately cease all functions, drive the outputs to Vss and go into a very low-current mode. The SLEEP instruction should only be executed after the LCD module has been disabled and the current cycle completed, thus ensuring that there are no DC voltages on the glass. To disable the LCD module, clear the LCDEN bit. The LCD module will complete the disabling process after the current frame, clear the LCDA bit and optionally cause an interrupt. The steps required to properly enter Sleep with the LCD disabled are: • Clear LCDEN • Wait for LCDA = 0 either by polling or by interrupt • Execute SLEEP If SLPEN = 0 and SLEEP is executed while the LCD module clock source is FOSC/4, then the LCD module will halt with the pin driving the last LCD voltage pattern. Prolonged exposure to a fixed LCD voltage pattern will cause damage to the LCD glass. To prevent LCD glass damage, either perform the proper LCD module shutdown prior to Sleep, or change the LCD module clock to allow the LCD module to continue operation during Sleep. If a SLEEP instruction is executed and SLPEN = 0 and the LCD module clock is either T1OSC or LFINTOSC, the module will continue to display the current contents of the LCDDATA registers. While in Sleep, the LCD data cannot be changed. If the LCDIE bit is set, the device will wake from Sleep on the next LCD frame boundary. The LCD module current consumption will not decrease in this mode; however, the overall device power consumption will be lower due to the shutdown of the CPU and other peripherals. © 2008 Microchip Technology Inc. Table 21-8 shows the status of the LCD module during a Sleep while using each of the three available clock sources. Note: When the LCDEN bit is cleared, the LCD module will be disabled at the completion of frame. At this time, the port pins will revert to digital functionality. To minimize power consumption due to floating digital inputs, the LCD pins should be driven low using the PORT and TRIS registers. If a SLEEP instruction is executed and SLPEN = 0, the module will continue to display the current contents of the LCDDATA registers. To allow the module to continue operation while in Sleep, the clock source must be either the LFINTOSC or T1OSC external oscillator. While in Sleep, the LCD data cannot be changed. The LCD module current consumption will not decrease in this mode; however, the overall consumption of the device will be lower due to shut down of the core and other peripheral functions. Table 21-8 shows the status of the LCD module during Sleep while using each of the three available clock sources: TABLE 21-8: Clock Source T1OSC LFINTOSC FOSC/4 Note: LCD MODULE STATUS DURING SLEEP SLPEN Operational During Sleep 0 Yes 1 No 0 Yes 1 No 0 No 1 No The LFINTOSC or external T1OSC oscillator must be used to operate the LCD module during Sleep. If LCD interrupts are being generated (Type-B waveform with a multiplex mode not static) and LCDIE = 1, the device will awaken from Sleep on the next frame boundary. Preliminary DS41364A-page 269 PIC16F193X/LF193X FIGURE 21-19: SLEEP ENTRY/EXIT WHEN SLPEN = 1 V3 V2 V1 COM0 V0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 SEG0 2 Frames SLEEP Instruction Execution DS41364A-page 270 Preliminary Wake-up © 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.12 Configuring the LCD Module 21.14 LCD Current Consumption The following is the sequence of steps to configure the LCD module. When using the LCD module the current consumption consists of the following three factors: 1. • Oscillator Selection • LCD Bias Source • Capacitance of the LCD segments 2. 3. 4. 5. 6. 7. Select the frame clock prescale using bits LP<3:0> of the LCDPS register. Configure the appropriate pins to function as segment drivers using the LCDSEn registers. Configure the LCD module for the following using the LCDCON register: - Multiplex and Bias mode, bits LMUX<1:0> - Timing source, bits CS<1:0> - Sleep mode, bit SLPEN Write initial values to pixel data registers, LCDDATA0 through LCDDATA11 (LCDDATA23 on PIC16F1938). Clear LCD Interrupt Flag, LCDIF bit of the PIR2 register and if desired, enable the interrupt by setting bit LCDIE of the PIE2 register. Configure bias voltages by setting the LCDRL, LCDREF and the associated ANSELx registers as needed. Enable the LCD module by setting bit LCDEN of the LCDCON register. 21.13 Disabling the LCD Module To disable the LCD module, write all ‘0’s to the LCDCON register. © 2008 Microchip Technology Inc. The current consumption of just the LCD module can be considered negligible compared to these other factors. 21.14.1 OSCILLATOR SELECTION The current consumed by the clock source selected must be considered when using the LCD module. See Section 28.0 “Electrical Specifications” for oscillator current consumption information. 21.14.2 LCD BIAS SOURCE The LCD bias source, internal or external, can contribute significantly to the current consumption. Use the highest possible resistor values while maintaining contrast to minimize current. 21.14.3 CAPACITANCE OF THE LCD SEGMENTS The LCD segments which can be modeled as capacitors which must be both charged and discharged every frame. The size of the LCD segment and its technology determines the segment’s capacitance. Preliminary DS41364A-page 271 PIC16F193X/LF193X TABLE 21-9: Name REGISTERS ASSOCIATED WITH LCD OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 LCDCON LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 243 LCDCST — — — — — LCDCST2 LCDCST1 LCDCST0 246 LCDDATA0 SEG7 COM0 SEG6 COM0 SEG5 COM0 SEG4 COM0 SEG3 COM0 SEG2 COM0 SEG1 COM0 SEG0 COM0 247 LCDDATA1 SEG15 COM0 SEG14 COM0 SEG13 COM0 SEG12 COM0 SEG11 COM0 SEG10 COM0 SEG9 COM0 SEG8 COM0 247 LCDDATA2 SEG23 COM0 SEG22 COM0 SEG21 COM0 SEG20 COM0 SEG19 COM0 SEG18 COM0 SEG17 COM0 SEG16 COM0 247 LCDDATA3 SEG7 COM1 SEG6 COM1 SEG5 COM1 SEG4 COM1 SEG3 COM1 SEG2 COM1 SEG1 COM1 SEG0 COM1 247 LCDDATA4 SEG15 COM1 SEG14 COM1 SEG13 COM1 SEG12 COM1 SEG11 COM1 SEG10 COM1 SEG9 COM1 SEG8 COM1 247 LCDDATA5 SEG23 COM1 SEG22 COM1 SEG21 COM1 SEG20 COM1 SEG19 COM1 SEG18 COM1 SEG17 COM1 SEG16 COM1 247 LCDDATA6 SEG7 COM2 SEG6 COM2 SEG5 COM2 SEG4 COM2 SEG3 COM2 SEG2 COM2 SEG1 COM2 SEG0 COM2 247 LCDDATA7 SEG15 COM2 SEG14 COM2 SEG13 COM2 SEG12 COM2 SEG11 COM2 SEG10 COM2 SEG9 COM2 SEG8 COM2 247 LCDDATA8 SEG23 COM2 SEG22 COM2 SEG21 COM2 SEG20 COM2 SEG19 COM2 SEG18 COM2 SEG17 COM2 SEG16 COM2 247 LCDDATA9 SEG7 COM3 SEG6 COM3 SEG5 COM3 SEG4 COM3 SEG3 COM3 SEG2 COM3 SEG1 COM3 SEG0 COM3 247 LCDDATA10 SEG15 COM3 SEG14 COM3 SEG13 COM3 SEG12 COM3 SEG11 COM3 SEG10 COM3 SEG9 COM3 SEG8 COM3 247 LCDDATA11 SEG23 COM3 SEG22 COM3 SEG21 COM3 SEG20 COM3 SEG19 COM3 SEG18 COM3 SEG17 COM3 SEG16 COM3 247 WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 244 LCDPS LCDREF LCDIRE LCDIRS LCDIRI — VLCD3PE VLCD2PE VLCD1PE — 245 LCDRL LRLAP1 LRLAP0 LRLBP1 LRLBP0 — LRLAT2 LRLAT1 LRLAT0 252 LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 247 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 247 LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 247 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 75 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 78 T1SYNC — TMR1ON 169 PIR2 T1CON Legend: TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the LCD module. DS41364A-page 272 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 22.1 Master SSP (MSSP) Module Overview Figure 22-1 is a block diagram of the SPI interface module. The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) The SPI interface supports the following modes and features: • • • • • Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy chain connection of Slave devices FIGURE 22-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPBUF Reg SDI SSPSR Reg SDO bit 0 SS SS Control Enable Shift Clock 2 (CKP, CKE) Clock Select Edge Select SSPM<3:0> 4 SCK Edge Select TRIS bit © 2008 Microchip Technology Inc. Preliminary ( TMR22Output ) Prescaler TOSC 4, 16, 64 Baud rate generator (SSPADD) DS41364A-page 273 PIC16F193X/LF193X The I2C interface supports the following modes and features: • • • • • • • • • • • • • Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 22-2 is a block diagram of the I2C interface module in Master mode. Figure 22-3 is a diagram of the I2C interface module in Slave mode. MSSP BLOCK DIAGRAM (I2C™ MASTER MODE) Internal data bus Read [SSPM 3:0] Write SSPBUF Baud rate generator (SSPADD) SDA in Receive Enable (RCEN) SCL SCL in Bus Collision DS41364A-page 274 LSb Start bit, Stop bit, Acknowledge Generate (SSPCON2) Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Preliminary Clock Cntl SSPSR MSb (Hold off clock source) Shift Clock SDA Clock arbitrate/BCOL detect FIGURE 22-2: Set/Reset: S, P, SSPSTAT, WCOL, SSPOV Reset SEN, PEN (SSPCON2) Set SSPIF, BCLIF © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 22-3: MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPBUF Reg SCL Shift Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect Addr Match SSPADD Reg Start and Stop bit Detect 22.2 Set, Reset S, P bits (SSPSTAT Reg) MSSP Control Registers The MSSP module has seven associated registers: • • • • • • • MSSP STATUS register (SSPSTAT) MSSP Control Register 1 (SSPCON1) MSSP Control Register 2 (SSPCON2) MSSP Control Register 3 (SSPCON3) MSSP Address Masking register (SSPMSK) MSSP Data Buffer register (SSPBUF) MSSP Address register (SSPADD) © 2008 Microchip Technology Inc. Preliminary DS41364A-page 275 PIC16F193X/LF193X REGISTER 22-1: SSPSTAT: SSP STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) CKP = 0: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty DS41364A-page 276 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 22-2: SSPCON1: SSP CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register (must be cleared in software). 0 = No overflow 2 In I C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C Slave mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2C Master mode: Unused in this mode bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSPADD+1)) 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: 2: 3: 4: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. When enabled, these pins must be properly configured as input or output. When enabled, the SDA and SCL pins must be configured as inputs. SSPADD values of 0, 1 or 2 are not supported for I2C Mode. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 277 PIC16F193X/LF193X REGISTER 22-3: SSPCON2: SSP CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCK Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). DS41364A-page 278 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 22-4: SSPCON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the SSPCON1 register is set, and the buffer is not updated In I2C Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSPBUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the SSPCON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSPCON1 register and SCL is held low. 0 = Data holding is disabled Note 1: 2: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 279 PIC16F193X/LF193X REGISTER 22-5: SSPMSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) REGISTER 22-6: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode — Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode — Least Significant Address byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. DS41364A-page 280 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.3 SPI Mode 22.3.2 The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four clock modes of SPI are supported in both Master and Slave modes. To accomplish communication, typically three pins are used: • Serial Data Out (SDO) • Serial Data In (SDI) • Serial Clock (SCK) Additionally, a fourth pin may be used when in a Slave mode of operation: • Slave Select (SS) Figure 22-1 shows the block diagram of the MSSP module when operating in SPI mode. 22.3.1 REGISTERS The MSSP module has five registers for SPI mode operation. These are: • • • • • • MSSP STATUS register (SSPSTAT) MSSP Control Register 1 (SSPCON1) MSSP Control Register 3 (SSPCON3) MSSP Data Buffer register (SSPBUF) MSSP Address register (SSPADD) MSSP Shift register (SSPSR) (Not directly accessible) SSPCON1 and SSPSTAT are the control and STATUS registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. In one SPI master mode, SSPADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 22.7 “Baud Rate Generator”. SSPSR is the shift register used for shifting data in and out. SSPBUF provides indirect access to the SSPSR register. SSPBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPSR and SSPBUF together create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. © 2008 Microchip Technology Inc. OPERATIONS When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • • • • Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) • Clock Edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full Detect bit, BF of the SSPSTAT register, and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored and the write collision detect bit WCOL of the SSPCON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPBUF register to complete successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The Buffer Full bit, BF of the SSPSTAT register, indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the SSPSTAT register indicates the various Status conditions. Preliminary DS41364A-page 281 PIC16F193X/LF193X 22.3.3 22.3.4 ENABLING SPI I/O To enable the serial port, SSP Enable bit, SSPEN of the SSPCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCONx registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: • SDI must have corresponding TRIS bit set • SDO must have corresponding TRIS bit cleared • SCK (Master mode) must have corresponding TRIS bit cleared • SCK (Slave mode) must have corresponding TRIS bit set • SS must have corresponding TRIS bit set TYPICAL CONNECTION Figure 22-4 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: • Master sends data (Slave sends dummy data) • Master sends data (Slave sends data) • Master sends dummy data (Slave sends data) Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 22-4: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx = 1010 SPI Slave SSPM<3:0> = 010x SDO SDI Serial Input Buffer (SSPBUF) SDI Shift Register (SSPSR) MSb Serial Input Buffer (SSPBUF) LSb General I/O DS41364A-page 282 Shift Register (SSPSR) MSb SCK Processor 1 SDO Serial Clock Slave Select (optional) Preliminary LSb SCK SS Processor 2 © 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 22-4) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPCON1 register and the CKE bit of the SSPSTAT register. This then, would give waveforms for SPI communication as shown in Figure 22-5, Figure 22-6 and Figure 22-7, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • • • • • FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 Fosc/(4 * (SSPADD + 1)) Figure 22-5 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 22-5: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF © 2008 Microchip Technology Inc. Preliminary DS41364A-page 283 PIC16F193X/LF193X 22.3.6 SLAVE MODE 22.3.7 SLAVE SELECT SYNCHRONIZATION In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON1<3:0> = 0100). Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPCON1 register. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 22.3.6.1 When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON1<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. Buffer Overwrite Enable In SPI daisy-chained configurations only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSPCON3 register will enable writes to the SSPBUF register, even if the previous byte has not been read. Allowing the software to ignore data that may not apply to it. FIGURE 22-6: 3: While operated in SPI Slave mode the SMP bit of the SSPSTAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. SLAVE SELECT SYNCRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Shift register SSPSR and bit count are reset SSPBUF to SSPSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF DS41364A-page 284 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 22-7: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF Write Collision detection active FIGURE 22-8: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF Write Collision detection active © 2008 Microchip Technology Inc. Preliminary DS41364A-page 285 PIC16F193X/LF193X 22.3.8 OPERATION IN POWER-MANAGED MODES If an exit from Sleep or Idle mode is not desired, MSSP interrupts should be disabled. In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted. In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. Special care must be taken by the user when the MSSP clock is much faster than the system clock. When MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller: • from Sleep, in Slave mode • from Idle, in Slave or Master mode TABLE 22-1: Name In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. REGISTERS ASSOCIATED WITH SPI OPERATION Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 APFCON — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL 84 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 74 PIR1 TMR1GIf ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 281* SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 279 SSPSTAT SMP CKE D/A P S R/W UA BF 276 277 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 86 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 94 Legend: * Shaded cells are not used by the MSSP in SPI mode. Page provides register information. DS41364A-page 286 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.4 I2C MODE TABLE 22-2: All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and 2 interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 22.4.1 SDA AND SCL PINS Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note: Data is tied to output zero when an I2C mode is enabled. 22.4.2 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a Master to a Slave or vice-versa, followed by an Acknowledge bit sent back. After the 8th falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 22.4.3 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Phillips I2C specification. © 2008 Microchip Technology Inc. TERM I2C BUS TERMS Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Slave device that has received a Addressed Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSPADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state. Preliminary DS41364A-page 287 PIC16F193X/LF193X 22.4.4 22.4.6 START CONDITION The I2C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 22-8 shows wave forms for Start and Stop conditions. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. Note: The Philips I2C Specification states that a bus collision cannot occur on a Start, and should occur during the address sequence. 22.4.5 STOP CONDITION A Stop condition is a transition of the SDA line from low to high state while the SCL line is high. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. FIGURE 22-9: RESTART CONDITION A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully address, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained. Until a Stop condition, a high address with R/W clear, or high address match fails. 22.4.7 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPCON3 register can enable the generation of an interrupt in Slave mode. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. I2C START AND STOP CONDITIONS SDA SCL S Start P Change of Change of Data Allowed Data Allowed Condition DS41364A-page 288 Stop Condition Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 22-10: I2C RESTART CONDITION Sr Change of Change of Data Allowed Data Allowed Restart Condition © 2008 Microchip Technology Inc. Preliminary DS41364A-page 289 PIC16F193X/LF193X 22.4.8 22.5 ACKNOWLEDGE SEQUENCE The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit of the SSPCON2 register. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPCON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSPCON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSPSTAT register or the SSPOV bit of the SSPCON1 register are set when a byte is received. I2C SLAVE MODE OPERATION The MSSP Slave mode operates in one of four modes selected in the SSPM bits of SSPCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operated the same as the other modes with SSPIF additionally getting set upon detection of a Start, Restart, or Stop condition. 22.5.1 SLAVE MODE ADDRESSES The SSPADD register (Register 22-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches the value is loaded into the SSPBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSP Mask register (Register 22-5) affects the address matching process. See Section 22.5.9 “SSP Mask Register” for more information. 22.5.1.1 I2C Slave 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 22.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPADD with the low address. The low address byte is clocked in and all 8 bits are compared to the low address value in SSPADD. Even if there is not an address match; SSPIF and UA are set, and SCL is held low until SSPADD is updated to receive a high byte again. When SSPADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS41364A-page 290 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.5.2 22.5.2.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF bit of the SSPSTAT register is set, or bit SSPOV bit of the SSPCON1 register is set. The BOEN bit of the SSPCON3 register modifies this operation. For more information see Register 22-4. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSPIF, must be cleared by software. When the SEN bit of the SSPCON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPCON1 register, except sometimes in 10-bit mode. See Section 22.3.5 “Master Mode” for more detail. 22.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C Slave in 7-bit Addressing mode. All decisions made by hardware or software and their effect on reception. Figure 22-10 and Figure 22-11 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSPIF bit. Software clears the SSPIF bit. Software reads received address from SSPBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSPIF bit. Software clears SSPIF. Software reads the received byte from SSPBUF clearing BF. Steps 8-12 are repeated for all received bytes from the Master. Master sends Stop condition, setting P bit of SSPSTAT, and the bus goes idle. © 2008 Microchip Technology Inc. 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBus™ that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communcation. Figure 22-12 displays a module using both address and data holding. Figure 22-13 includes the operation with the SEN bit of the SSPCON2 register set. 1. S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPIF is set and CKP cleared after the 8th falling edge of SCL. 3. Slave clears the SSPIF. 4. Slave can look at the ACKTIM bit of the SSPCON3 register to determine if the SSPIF was after or before the ACK. 5. Slave reads the address value from SSPBUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSPIF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPIF. Note: SSPIF is still set after the 9th falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to Master is SSPIF not set 11. SSPIF set and CKP cleared after 8th falling edge of SCL for a received data byte. 12. Slave looks at ACKTIM bit of SSPCON3 to determine the source of the interrupt. 13. Slave reads the received data from SSPBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. Preliminary DS41364A-page 291 DS41364A-page 292 Preliminary SSPOV BF SSPIF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSPBUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 SSPOV set because SSPBUF is still full. ACK is not sent. Cleared by software 3 D5 Receiving Data From Slave to Master 8 D0 9 P SSPIF set on 9th falling edge of SCL ACK = 1 FIGURE 22-11: SCL SDA Receiving Address Bus Master sends Stop condition PIC16F193X/LF193X I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) © 2008 Microchip Technology Inc. © 2008 Microchip Technology Inc. Preliminary CKP SSPOV BF SSPIF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSPBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPBUF 6 D2 7 D1 SSPOV set because SSPBUF is still full. ACK is not sent. Cleared by software 2 D6 CKP is written to 1 in software, releasing SCL 1 D7 Receive Data 8 D0 9 ACK SCL is not held low because ACK= 1 falling edge of SCL SSPIF set on 9th P FIGURE 22-12: SDA Receive Address Bus Master sends Stop condition PIC16F193X/LF193X I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS41364A-page 293 DS41364A-page 294 Preliminary P S ACKTIM CKP ACKDT BF SSPIF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPIF is set 4 ACKTIM set by hardware on 8th falling edge of SCL When AHEN=1: CKP is cleared by hardware and SCL is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCL When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL SSPIF is set on 9th falling edge of SCL, after ACK 1 8 ACK D7 D6 D5 D4 D3 D2 D1 D0 Received Data 1 2 4 5 6 ACKTIM set by hardware on 8th falling edge of SCL CKP set by software, SCL is released 8 Slave software sets ACKDT to not ACK 7 Cleared by software 3 D7 D6 D5 D4 D3 D2 D1 D0 Data is read from SSPBUF 9 ACK 9 P No interrupt after not ACK from Slave ACK=1 Master sends Stop condition FIGURE 22-13: SCL SDA Master Releases SDA to slave for ACK sequence PIC16F193X/LF193X I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) © 2008 Microchip Technology Inc. © 2008 Microchip Technology Inc. Preliminary P S ACKTIM CKP ACKDT BF SSPIF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSPBUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCL 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCL When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared Received data is available on SSPBUF Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK Receive Data 1 3 4 5 6 7 8 Set by software, release SCL Slave sends not ACK SSPBUF can be read any time before next byte is loaded 2 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK CKP is not cleared if not ACK No interrupt after if not ACK from Slave P Master sends Stop condition FIGURE 22-14: SCL SDA R/W = 0 Master releases SDA to slave for ACK sequence PIC16F193X/LF193X I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) DS41364A-page 295 PIC16F193X/LF193X 22.5.3 SLAVE TRANSMISSION 22.5.3.1 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register, and an ACK pulse is sent by the slave on the ninth bit. A Master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 22-14 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see Section 22.5.6 “Clock Stretching” for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. 1. The transmit data must be loaded into the SSPBUF register which also loads the SSPSR register. Then the SCL pin should be released by setting the CKP bit of the SSPCON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit of the SSPCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared by software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. Master sends a Start condition on SDA and SCL. 2. S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSPIF bit. 4. Slave hardware generates an ACK and sets SSPIF. 5. SSPIF bit is cleared by user. 6. Software reads the received address from SSPBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSPBUF. 9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. 10. SSPIF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSPIF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSPIF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. DS41364A-page 296 Preliminary © 2008 Microchip Technology Inc. © 2008 Microchip Technology Inc. Preliminary P S D/A R/W ACKSTAT CKP BF SSPIF S Receiving Address 1 2 5 6 7 8 Indicates an address has been received R/W is copied from the matching address byte 9 R/W = 1 Automatic ACK Received address is read from SSPBUF 4 When R/W is set SCL is always held low after 9th SCL falling edge 3 A7 A6 A5 A4 A3 A2 A1 Transmitting Data Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSPBUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 Masters not ACK is copied to ACKSTAT BF is automatically cleared after 8th falling edge of SCL 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P FIGURE 22-15: SCL SDA Master sends Stop condition PIC16F193X/LF193X I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) DS41364A-page 297 PIC16F193X/LF193X 22.5.3.2 7-bit TRANSMISSION WITH Address Hold Enabled Setting the AHEN bit of the SSPCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure 22-15 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle. Master sends Start condition; the S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCL line the CKP bit is cleared and SSPIF interrupt is generated. 4. Slave software clears SSPIF. 5. Slave software reads ACKTIM bit of SSPCON3 register, and R/W and D/A of the SSPSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSPCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPIF after the ACK if the R/W bit is set. 11. Slave software clears SSPIF. 12. Slave loads value to transmit to the master into SSPBUF setting the BF bit. Note: SSPBUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. DS41364A-page 298 Preliminary © 2008 Microchip Technology Inc. © 2008 Microchip Technology Inc. Preliminary D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPIF S Receiving Address 2 3 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPBUF 4 When AHEN = 1; CKP is cleared by hardware after receiving matching address. 1 A7 A6 A5 A4 A3 A2 A1 3 4 5 6 Cleared by software 2 Set by software, releases SCL Data to transmit is loaded into SSPBUF 1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK ACKTIM is cleared on 9th rising edge of SCL Automatic Transmitting Data 1 3 4 5 6 7 after not ACK CKP not cleared Master’s ACK response is copied to SSPSTAT BF is automatically cleared after 8th falling edge of SCL 2 8 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P Master sends Stop condition FIGURE 22-16: SCL SDA Master releases SDA to slave for ACK sequence PIC16F193X/LF193X I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) DS41364A-page 299 PIC16F193X/LF193X 22.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 22.5.5 This section describes a standard sequence of events for the MSSP module configured as an I2C Slave in 10-bit Addressing mode. Figure 22-16 and is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSPSTAT register is set. Slave sends ACK and SSPIF is set. Software clears the SSPIF bit. Software reads received address from SSPBUF clearing the BF flag. Slave loads low address into SSPADD, releasing SCL. Master sends matching low address byte to the Slave; UA bit is set. 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 22-17 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 22-18 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. Note: Updates to the SSPADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPIF is set. Note: If the low address does not match, SSPIF and UA are still set so that the slave software can set SSPADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPIF. 11. Slave reads the received matching address from SSPBUF clearing BF. 12. Slave loads high address into SSPADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCL pulse; SSPIF is set. 14. If SEN bit of SSPCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPIF. 16. Slave reads the received byte from SSPBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS41364A-page 300 Preliminary © 2008 Microchip Technology Inc. © 2008 Microchip Technology Inc. Preliminary CKP UA BF SSPIF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCL is held low If address matches SSPADD it is loaded into SSPBUF 3 1 Receive First Address Byte 9 ACK 1 3 4 5 6 7 8 Software updates SSPADD and releases SCL 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSPBUF SCL is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte Receive address is read from SSPBUF Cleared by software 2 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data P FIGURE 22-17: SCL SDA Master sends Stop condition PIC16F193X/LF193X I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS41364A-page 301 DS41364A-page 302 Preliminary ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCL If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSPADD is not allowed until 9th falling edge of SCL SSPBUF can be read anytime before the next received byte Cleared by software 1 A7 Receive Second Address Byte 8 A0 9 ACK UA 2 D6 3 D5 4 D4 6 D2 Set CKP with software releases SCL 7 D1 Update of SSPADD, clears UA and releases SCL 5 D3 Receive Data Cleared by software 1 D7 8 9 2 Received data is read from SSPBUF 1 D6 D5 Receive Data D0 ACK D7 FIGURE 22-18: SSPIF 1 SCL S 1 SDA Receive First Address Byte PIC16F193X/LF193X I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) © 2008 Microchip Technology Inc. © 2008 Microchip Technology Inc. Preliminary D/A R/W ACKSTAT CKP UA BF SSPIF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSPADD must be updated SSPBUF loaded with received address 2 8 9 1 SCL S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSPADD is updated, UA is cleared and SCL is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from the matching address byte When R/W = 1; CKP is cleared on 9th falling edge of SCL High address is loaded back into SSPADD Received address is read from SSPBUF Sr 1 1 1 1 0 A9 A8 Receive First Address Byte 9 ACK 2 3 4 5 6 7 8 Masters not ACK is copied Set by software releases SCL Data to transmit is loaded into SSPBUF 1 D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data Byte 9 P Master sends Stop condition ACK = 1 Master sends not ACK FIGURE 22-19: SDA Master sends Restart event PIC16F193X/LF193X I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) DS41364A-page 303 PIC16F193X/LF193X 22.5.6 CLOCK STRETCHING 22.5.6.2 Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. The CKP bit of the SSPCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 22.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSPSTAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPBUF with data to transfer to the master. If the SEN bit of SSPCON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPBUF was read before the 9th falling edge of SCL. 2: Previous versions of the module did not stretch the clock for a transmission if SSPBUF was loaded before the 9th falling edge of SCL. It is now always cleared for read requests. FIGURE 22-20: 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is releases immediately after a write to SSPADD. Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 22.5.6.3 Byte NACKing When AHEN bit of SSPCON3 is set; CKP is cleared by hardware after the 8th falling edge of SCL for a received matching address byte. When DHEN bit of SSPCON3 is set; CKP is cleared after the 8th falling edge of SCL for received data. Stretching after the 8th falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. 22.5.7 CLOCK SYNCHRONIZATION AND THE CKP BIT Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 22-19). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX ‚ – 1 DX SCL CKP Master device asserts clock Master device releases clock WR SSPCON1 DS41364A-page 304 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. If the AHEN bit of the SSPCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of SCL. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPBUF and respond. Figure 22-20 shows a General Call reception sequence. FIGURE 22-21: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 SCL S 1 2 3 4 5 6 7 8 9 1 9 SSPIF BF (SSPSTAT<0>) Cleared by software SSPBUF is read GCEN (SSPCON2<7>) ’1’ 22.5.9 SSP MASK REGISTER An SSP Mask (SSPMSK) register (Register 22-5) is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPMSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: • 7-bit Address mode: address compare of A<7:1>. • 10-bit Address mode: address compare of A<7:0> only. The SSP mask has no effect during the reception of the first (high) byte of the address. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 305 PIC16F193X/LF193X 22.6 I2C MASTER MODE 22.6.1 Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPCON1 register and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are set as inputs and are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (SSP interrupt, if enabled): • • • • • Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur I2C MASTER MODE OPERATION The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic ‘0’. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See Section 22.7 “Baud Rate Generator” for more detail. 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. DS41364A-page 306 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 22-22). FIGURE 22-22: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX ‚ – 1 DX SCL deasserted but slave holds SCL low (clock arbitration) SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 22.6.3 WCOL STATUS FLAG If the user writes the SSPBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). Any time the WCOL bit is set it indicates that an action on SSPBUF was attempted while the module was not Idle. Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the Start condition is complete. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 307 PIC16F193X/LF193X 22.6.4 I2C MASTER MODE START ister will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit of the SSPSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPCON2 reg- FIGURE 22-23: Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2C Specification states that a bus collision cannot occur on a Start. FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here At completion of Start bit, hardware clears SEN bit and sets SSPIF bit SDA = 1, SCL = 1 TBRG TBRG Write to SSPBUF occurs here SDA 1st bit 2nd bit TBRG SCL S DS41364A-page 308 Preliminary TBRG © 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.6.5 I2C MASTER MODE REPEATED SSPCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPSTAT register will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit of the SSPCON2 register is programmed high and the Master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the FIGURE 22-24: Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPCON2 occurs here SDA = 1, SCL (no change) At completion of Start bit, hardware clears RSEN bit and sets SSPIF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSPBUF occurs here TBRG SCL Sr TBRG Repeated Start © 2008 Microchip Technology Inc. Preliminary DS41364A-page 309 PIC16F193X/LF193X 22.6.6 I2C MASTER MODE TRANSMISSION 22.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 22-24). After the write to the SSPBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. 22.6.6.1 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSPCON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 22.6.6.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. BF Status Flag Typical transmit sequence: The user generates a Start condition by setting the SEN bit of the SSPCON2 register. SSPIF is set by hardware on completion of the Start. SSPIF is cleared by software. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPBUF with the slave address to transmit. Address is shifted out the SDA pin until all 8 bits are transmitted. Transmission begins as soon as SSPBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. The user loads the SSPBUF with eight bits of data. Data is shifted out the SDA pin until all 8 bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPCON2 register. Interrupt is generated once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPSTAT register is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 22.6.6.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared by software before the next transmission. DS41364A-page 310 Preliminary © 2008 Microchip Technology Inc. © 2008 Microchip Technology Inc. S Preliminary R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written by software Cleared by software service routine from SSP interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address From slave, clear ACKSTAT bit SSPCON2<6> P Cleared by software 9 ACK ACKSTAT in SSPCON2 = 1 FIGURE 22-25: SEN = 0 Write SSPCON2<0> SEN = 1 Start condition begins PIC16F193X/LF193X I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) DS41364A-page 311 PIC16F193X/LF193X 22.6.7 I2C MASTER MODE RECEPTION 22.6.7.4 Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSPCON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag bit is set, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSPCON2 register. 22.6.7.1 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read. 11. 22.6.7.2 12. SSPOV Status Flag In receive operation, the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 22.6.7.3 WCOL Status Flag 13. 14. 15. If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). DS41364A-page 312 Preliminary Typical Receive Sequence: The user generates a Start condition by setting the SEN bit of the SSPCON2 register. SSPIF is set by hardware on completion of the Start. SSPIF is cleared by software. User writes SSPBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all 8 bits are transmitted. Transmission begins as soon as SSPBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. User sets the RCEN bit of the SSPCON2 register and the Master clocks in a byte from the slave. After the 8th falling edge of SCL, SSPIF and BF are set. Master clears SSPIF and reads the received byte from SSPUF, clears BF. Master sets ACK value sent to slave in ACKDT bit of the SSPCON2 register and initiates the ACK by setting the ACKEN bit. Masters ACK is clocked out to the Slave and SSPIF is set. User clears SSPIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. © 2008 Microchip Technology Inc. © 2008 Microchip Technology Inc. Preliminary RCEN ACKEN SSPOV BF (SSPSTAT<0>) SDA = 0, SCL = 1 while CPU responds to SSPIF SSPIF S 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 A1 8 ACK 2 3 5 6 7 8 D0 9 ACK 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSPIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDA = ACKDT = 0 Cleared in software Set SSPIF at end of receive 9 ACK is not sent ACK P Set SSPIF interrupt at end of Acknowledge sequence Bus master terminates transfer Set P bit (SSPSTAT<4>) and SSPIF PEN bit = 1 written here SSPOV is set because SSPBUF is still full 8 D0 RCEN cleared automatically D7 D6 D5 D4 D3 D2 D1 RCEN cleared automatically Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 Receiving Data from Slave RCEN = 1, start next receive ACK from Master SDA = ACKDT = 0 Last bit is shifted into SSPSR and contents are unloaded into SSPBUF Cleared by software Set SSPIF interrupt at end of receive 4 Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 Receiving Data from Slave RCEN cleared automatically Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) 9 R/W = 0 ACK from Slave Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) FIGURE 22-26: SCL SDA SEN = 0 Write to SSPBUF occurs here, start XMIT Write to SSPCON2<0> (SEN = 1), begin Start condition Write to SSPCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 PIC16F193X/LF193X I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) DS41364A-page 313 PIC16F193X/LF193X 22.6.8 ACKNOWLEDGE SEQUENCE TIMING 22.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit of the SSPSTAT register is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 22-27). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSPCON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 22-26). 22.6.8.1 22.6.9.1 WCOL Status Flag If the user writes the SSPBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL Status Flag If the user writes the SSPBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 22-27: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA ACK D0 SCL 8 9 SSPIF SSPIF set at the end of receive Cleared in software SSPIF set at the end of Acknowledge sequence Cleared in software Note: TBRG = one Baud Rate Generator period. FIGURE 22-28: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set. Write to SSPCON2, set PEN PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS41364A-page 314 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.6.10 SLEEP OPERATION 22.6.13 2 While in Sleep mode, the I C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 22.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 22.6.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPSTAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLIF bit. The states where arbitration can be lost are: • • • • • Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high and another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the I2C port to its Idle state (Figure 22-28). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 22-29: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data doesn’t match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLIF) BCLIF © 2008 Microchip Technology Inc. Preliminary DS41364A-page 315 PIC16F193X/LF193X 22.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 22-29). SCL is sampled low before SDA is asserted low (Figure 22-30). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 22-31). If, however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as ‘0’ during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: • the Start condition is aborted, • the BCLIF flag is set and • the MSSP module is reset to its Idle state (Figure 22-29). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 22-30: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSP module reset into Idle state. SEN BCLIF SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared by software S SSPIF SSPIF and BCLIF are cleared by software DS41364A-page 316 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 22-31: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared by software S ’0’ ’0’ SSPIF ’0’ ’0’ FIGURE 22-32: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSPIF TBRG SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN BCLIF Set SEN, enable Start sequence if SDA = 1, SCL = 1 ’0’ S SSPIF SDA = 0, SCL = 1, set SSPIF © 2008 Microchip Technology Inc. Preliminary Interrupts cleared by software DS41364A-page 317 PIC16F193X/LF193X 22.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 22-32). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’. If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start condition, see Figure 22-33. When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. FIGURE 22-33: If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared by software S ’0’ SSPIF ’0’ FIGURE 22-34: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCLIF SCL goes low before SDA, set BCLIF. Release SDA and SCL. Interrupt cleared by software RSEN ’0’ S SSPIF DS41364A-page 318 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 22-34). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure 22-35). Bus collision occurs during a Stop condition if: a) b) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is deasserted, SCL is sampled low before SDA goes high. FIGURE 22-35: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ’0’ SSPIF ’0’ FIGURE 22-36: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, set BCLIF Assert SDA SCL PEN BCLIF P ’0’ SSPIF ’0’ © 2008 Microchip Technology Inc. Preliminary DS41364A-page 319 PIC16F193X/LF193X 22.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPADD register (Register 22-6). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. Table 22-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD. EQUATION 22-1: FOSC FCLOCK = ---------------------------------------------( SSPADD + 1 ) ( 4 ) An internal signal “Reload” in Figure 22-36 triggers the value from SSPADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module FIGURE 22-37: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPM<3:0> Reload SCL Control SSPADD<7:0> Reload BRG Down Counter SSPCLK FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 22-3: Note 1: 2: MSSP CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz(1) 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz 4 MHz 1 MHz 00h 250 kHz(2) 2 2 The I C interface does not conform to the 400 kHz I C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. SPI mode only. DS41364A-page 320 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 23.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL 23.1 The Data EEPROM and Flash program memory are readable and writable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs). There are six SFRs used to access these memories: • • • • • • EECON1 EECON2 EEDATL EEDATH EEADRL EEADRH EEADRL and EEADRH Registers The EEADRL and EEADRH registers can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the EEADRH register and the LSB is written to the EEADRL register. When selecting a EEPROM address value, only the LSB of the address is written to the EEADRL register. 23.1.1 EECON1 AND EECON2 REGISTERS EECON1 is the control register for EE memory accesses. When interfacing the data memory block, EEDATL holds the 8-bit data for read/write, and EEADRL holds the address of the EEDATL location being accessed. These devices have 256 bytes of data EEPROM with an address range from 0h to 0FFh. When accessing the program memory block of the PIC16F1936/PIC16F1937 devices, the EEDATL and EEDATH registers form a 2-byte word that holds the 14-bit data for read/write, and the EEADRL and EEADRH registers form a 2-byte word that holds the 15-bit address of the program memory location being read. The EEPROM data memory allows byte read and write. An EEPROM byte write automatically erases the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. Depending on the setting of the Flash Program Memory Self Write Enable bits WRT<1:0> of the Configuration Word Register 2, the device may or may not be able to write certain blocks of the program memory. However, reads from the program memory are always allowed. Control bit EEPGD determines if the access will be a program or data memory access. When clear, any subsequent operations will operate on the EEPROM memory. When set, any subsequent operations will operate on the program memory. On Reset, EEPROM is selected by default. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. Interrupt flag bit EEIF of the PIR2 register is set when write is complete. It must be cleared in the software. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the data EEPROM write sequence. To enable writes, a specific pattern must be written to EECON2. When the device is code-protected, the device programmer can no longer access data or program memory. When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 321 PIC16F193X/LF193X REGISTER 23-1: EEDATL: EEPROM DATA REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEDATL<7:0>: 8 Least Significant data bits of data EEPROM or Read from program memory REGISTER 23-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 EEDATH<5:0>: 6 Most Significant Data bits from program memory REGISTER 23-3: EEADRL: EEPROM ADDRESS REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEADRL<7:0>: 8 Least Significant Address bits for EEPROM or program memory REGISTER 23-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — EEADRH6 EEADRH5 EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-0 EEADRH<6:0>: Specifies the 7 Most Significant Address bits or high bits for program memory reads DS41364A-page 322 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 23-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 EEPGD CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = bit is cleared by hardware bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Accesses program space Flash memory 0 = Accesses data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration, User ID and Device ID Registers 0 = Accesses Flash Program or data EEPROM Memory bit 5 LWLO: Load Write Latches Only bit If EEPGD = 1 or CFGS = 1: (accessing program Flash) 1 = The next WR command does not initiate a write to the PFM; only the program memory latches are updated. 0 = The next WR command writes a value from EEDATH:EEDATL into program memory latches and initiates a write to the PFM of all the data stored in the program memory latches. If EEPGD = 0 and CFGS = 1: (Accessing data EEPROM) LWLO is ignored. The next WR command initiates a write to the data EEPROM. bit 4 FREE: Program Flash Erase Enable bit If EEPGD = 1 or CFGS = 1: (accessing program Flash) 1 = Perform an program Flash erase operation on the next WR command (cleared by hardware after completion of erase). 0 = Perform a program Flash write operation on the next WR command. If EEPGD = 0 and CFGS = 0: (Accessing data EEPROM) FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle. bit 3 WRERR: EEPROM Error Flag bit 1 = Condition could indicate an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘1’) of the WR bit. 0 = The program or erase operation completed normally. bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash and data EEPROM bit 1 WR: Write Control bit 1 = Initiates a program Flash or data EEPROM program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash or data EEPROM is complete and inactive. bit 0 RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash or data EEPROM data read. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 323 PIC16F193X/LF193X REGISTER 23-6: EECON2: EEPROM CONTROL 2 REGISTER R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 EEUNLK7 EEUNLK6 EEUNLK5 EEUNLK4 EEUNLK3 EEUNLK2 EEUNLK1 EEUNLK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEUNLK<7:0>: Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. Refer to Section 23.1.3 “Writing to the Data EEPROM Memory” for more information. DS41364A-page 324 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 23.1.2 READING THE DATA EEPROM MEMORY 23.1.3 WRITING TO THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the EEADRL register, clear the EEPGD and CFGS control bits of the EECON1 register, and then set control bit RD. The data is available at the very next cycle, in the EEDATL register; therefore, it can be read in the next instruction. EEDATL will hold this value until another read or until it is written to by the user (during a write operation). To write an EEPROM data location, the user must first write the address to the EEADRL register and the data to the EEDATL register. Then the user must follow a specific sequence to initiate the write for each byte. EXAMPLE 23-1: Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. DATA EEPROM READ BANKSEL EEADRL ; MOVLW DATA_EE_ADDR ; MOVWF EEADRL ;Data Memory ;Address to read BCF EECON1, CFGS ;Deselect Config space BCF EECON1, EEPGD;Point to DATA memory BSF EECON1, RD ;EE Read MOVF EEDATL, W ;W = EEDATL BCF STATUS, RP1 ;Bank 0 Note: Data EEPROM can be read regardless of the setting of the CPD bit. Required Sequence EXAMPLE 23-2: The write will not initiate if the above sequence is not followed exactly (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. Interrupts should be disabled during this code segment. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. DATA EEPROM WRITE BANKSEL MOVLW MOVWF MOVLW MOVWF BCF BCF BSF EEADRL DATA_EE_ADDR EEADRL DATA_EE_DATA EEDATL EECON1, CFGS EECON1, EEPGD EECON1, WREN ; ; ;Data Memory Address to write ; ;Data Memory Value to write ;Deselect Configuration space ;Point to DATA memory ;Enable writes BCF BTFSC GOTO MOVLW MOVWF MOVLW MOVWF BSF INTCON, GIE INTCON, GIE $-2 55h EECON2 AAh EECON2 EECON1, WR ;Disable INTs. ;SEE AN576 BCF BTFSC GOTO EECON1, WREN EECON1, WR $-2 ;Disable writes ;Wait for write to complete ;Done © 2008 Microchip Technology Inc. ; ;Write 55h ; ;Write AAh ;Set WR bit to begin write Preliminary DS41364A-page 325 PIC16F193X/LF193X 23.1.4 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. Write the Least and Most Significant address bits to the EEADRL and EEADRH registers. Clear the CFGS bit of the EECON1 register. Set the EEPGD control bit of the EECON1 register. Then, set control bit RD of the EECON1 register. 2. 3. 4. EEDATL and EEDATH registers will hold this value until another read or until it is written to by the user. Note 1: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set. 2: Data EEPROM can be read regardless of the setting of the CPD bit. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF EECON1,RD” instruction to be ignored. The data is available in the very next cycle, in the EEDATL and EEDATH registers; therefore, it can be read as two bytes in the following instructions. Required Sequence EXAMPLE 23-3: BANKSEL MOVLW MOVWF MOVLW MOVWF BANKSEL BSF BSF FLASH PROGRAM READ EEADRL MS_PROG_EE_ADDR EEADRH LS_PROG_EE_ADDR EEADRL EECON1 EECON1, EEPGD EECON1, RD ; ; ;MS Byte of Program Address to read ; ;LS Byte of Program Address to read ; ;Point to PROGRAM memory ;EE Read ; ;First instruction after BSF EECON1,RD executes normally NOP NOP ;Any instructions here are ignored as program ;memory is read in second cycle after BSF EECON1,RD ; BANKSEL EEDATL MOVF EEDATL, W MOVWF LOWPMBYTE MOVF EEDATH, W MOVWF HIGHPMBYTE BCF STATUS, RP1 DS41364A-page 326 ; ;W = LS Byte of Program Memory ; ;W = MS Byte of Program EEDATL ; ;Bank 0 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X EXAMPLE 23-4: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL EEADRL PROG_ADDR_LO EEADRL PROG_ADDR_HI EEADRH ; Select Bank for EEPROM registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF BCF BSF NOP NOP BSF EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,RD INTCON,GIE ; ; ; ; ; ; ; Select Configuration Space Select Program Memory Disable interrupts Initiate read Executed (Figure 23-1) Ignored (Figure 23-1) Restore interrupts MOVF MOVWF MOVF MOVWF EEDATL,W PROG_DATA_LO EEDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location FIGURE 23-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Flash ADDR Flash Data PC PC + 1 INSTR (PC) INSTR(PC - 1) executed here EEADRH,EEADRL INSTR (PC + 1) BSF EECON1,RD executed here PC +3 PC+3 EEDATH,EEDATL INSTR(PC + 1) executed here PC + 5 PC + 4 INSTR (PC + 3) Forced NOP executed here INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit EEDATH EEDATL Register EERHLT © 2008 Microchip Technology Inc. Preliminary DS41364A-page 327 PIC16F193X/LF193X 23.2 Erasing Program Memory While executing code, program memory can only be erased by rows. A row consists of 32 words where the EEADRL<4:0> = 0000. To erase a row: 1. 2. 3. 4. 5. 6. Load the EEADRH and EEADRL registers with the address of new row to be erased. Clear the CFGS bit of the EECON1 register. Set the EEPGD bit of the EECON1 register. Set the FREE bit of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence). Set control bit WR of the EECON1 register to begin the write operation. 23.3 Writing to Flash Program Memory Before writing, program memory should be erased using the Erase Program Memory command. No automatic erase occurs upon the initiation of the write; if the program Flash needs to be erased before writing, the row (32 words) must be erased previously. Up to eight buffer register locations can be written to with correct data. If less than eight words are being written to in the block of eight words, then the data for the unprogrammed words should be set to all ones. After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the erase/write operation. The user must place two NOP instructions after the WR bit is set. Since data is being written to buffer registers, the writing of the first seven words of the block appears to occur immediately. The processor will halt internal operations for the typical 2 ms, only during the cycle in which the erase takes place (i.e., the last word of the sixteen-word block erase). This is not Sleep mode as the clocks and peripherals will continue to run. After the eight-word write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. An example of the complete eight-word write sequence is shown in Example 23-5. The initial address is loaded into the EEADRH and EEADRL register pair; the eight words of data are loaded using indirect addressing. Flash program memory may only be written to if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT<1:0> of the Configuration Word Register 2. Flash program memory must be written in eight-word blocks. See Figure 23-2 for more details. A block consists of eight words with sequential addresses, with a lower boundary defined by an address, where EEADRL<2:0> = 000. All block writes to program memory are done as 32-word erase by eight-word write operations. The write operation is edge-aligned and cannot occur across boundaries. When the LWLO bit is ‘1’, the write sequence will only load the buffer register and will not actually initiate the write to program Flash: 1. 2. 3. Set the EEPGD, WREN and LWLO bits of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence). Set control bit WR of the EECON1 register to begin the write operation. To write program data, it must first be loaded into the buffer registers (see Figure 23-1). This is accomplished by first writing the destination address to EEADRL and EEADRH and then writing the data to EEDATA and EEDATH. After the address and data have been set up, then the following sequence of events must be executed: 1. 2. 3. 4. Set the EEPGD control bit of the EECON1 register. Set the LWLO bit of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming sequence). Set the WR control bit of the EECON1 register. DS41364A-page 328 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 23-2: BLOCK WRITES TO 8K FLASH PROGRAM MEMORY 7 5 0 0 7 EEDATH EEDATA 6 8 14 14 First word of block to be written 14 EEADRL<2:0> = 000 EEADRL<2:0> = 010 EEADRL<2:0> = 001 Buffer Register Buffer Register Buffer Register 14 EEADRL<2:0> = 111 Buffer Register Program Memory © 2008 Microchip Technology Inc. Preliminary DS41364A-page 329 PIC16F193X/LF193X EXAMPLE 23-5: ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. A valid starting address (the least significant bits = 00)is loaded in ADDRH:ADDRL 2. The 8 bytes of data are loaded, starting at the address in DATADDR 3. ADDRH, ADDRL and DATADDR are all located in shared data memory 0x70 - 0x7f Required Sequence LOOP BANKSEL MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF EEADRH ADDRH,W EEADRH ADDRL,W EEADRL DATAADDRL,W FSR0L DATAADDRH,W FSR0H ; ; ; ; ; ; ; ; ; MOVIW MOVWF MOVIW MOVWF BSF BCF BSF BSF INDF0++ EEDATL INDF0++ EEDATH EECON1,EEPGD EECON1,CFGS EECON1,WREN EECON1,LWLO ; ; ; ; ; ; ; ; Load first data byte into lower MOVLW MOVWF MOVLW MOVWF BSF 55h EECON2 AAh EECON2 EECON1,WR ; ; ; ; ; Start of required write sequence: Write 55h ; ; ; ; Any instructions here are ignored as processor halts to begin write sequence processor will stop here and wait for write complete after write processor continues with 3rd instruction NOP NOP MOVF EEADR,W XORLW 0x08 ANDLW 0x08 BTFSC STATUS,Z GOTO START_WRITE INCF GOTO Required Sequence START_WRITE BCF MOVLW MOVWF MOVLW MOVWF BSF Load initial data address Load second data byte into upper Point to program memory Not configuration space Enable writes Only Load Write Latches Write AAh Set WR bit to begin write ; Check if lower two bits of address are ‘00’ ; Check if we’re on the last of 8 addresses ; ; Exit if last of eight words, ; ; Still loading latches Increment address ; Write next latches EECON1,LWLO ; No more Latches only; Actually start write 55h EECON2 AAh EECON2 EECON1,WR ; ; ; ; ; Start of required write sequence: Write 55h EECON1,WREN ; ; ; ; ; Any instructions here are ignored as processor halts to begin write sequence processor will stop here and wait for write complete after write processor continues with 3rd instruction Disable writes NOP DS41364A-page 330 Load initial data address EEADR,F LOOP NOP BCF Bank 3 Load initial address Write AAh Set WR bit to begin write Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 23.4 Configuration Word and Device ID Access Instead of accessing program memory or EEPROM data memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 23-1. TABLE 23-1: When read access is initiated on an unallowed address, the EEDATH:EEDATL registers are cleared. Writes can be disabled via the WRT Configuration bits. Refer to the Configuration Word 2 register. PFM AND FUSE ACCESS VIA EECON1/EEDATH:EEDATL REGISTERS (WHEN CFGS = 1) Address Function Read Access Write Access 8000h-8003h 8006h 8007h-8008h User IDs Device ID/Revision ID Configuration Words 1 and 2 Yes Yes Yes Yes No No EXAMPLE 23-3: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL EEADRL PROG_ADDR_LO EEADRL PROG_ADDR_HI EEADRH ; Select Bank 2 ; ; Store LSB of address ; ; Store MSB of address BCF BSF BCF BSF NOP NOP BSF EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,RD INTCON,GIE ; ; ; ; ; ; ; Deselect Configuration Space Select Program Memory Disable interrupts Initiate read Executed (Figure 23-1) Ignored (Figure 23-1) Restore interrupts MOVF MOVWF MOVF MOVWF EEDATL,W PROG_DATA_LO EEDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location © 2008 Microchip Technology Inc. Preliminary DS41364A-page 331 PIC16F193X/LF193X 23.5 Write Verify 23.6 Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example 23-6) to the desired value to be written. EXAMPLE 23-6: WRITE VERIFY XORWF BTFSS GOTO : 23.5.1 ; ;EEDATL not changed ;from previous write EECON1, RD ;YES, Read the ;value written EEDATL, W ; STATUS, Z ;Is data the same WRITE_ERR ;No, handle error ;Yes, continue • Brown-out • Power Glitch • Software Malfunction 23.7 USING THE DATA EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM (specification D124) without exceeding the total number of write cycles to a single byte (specifications D120 and D120A). If this is the case, then a refresh of the array must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. TABLE 23-2: There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: BANKSEL EEDATL MOVF EEDATL, W BSF Protection Against Spurious Write Data EEPROM Operation During Code-Protect Data memory can be code-protected by programming the CPD bit in the Configuration Word Register 1 (Register 10-1) to ‘0’. When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 323 EECON2 EEPROM Control Register 2 (not a physical register) EEADRL EEADRH EEDATL EEDATH INTCON 324* EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 — 322 EEADRH6 EEADRH5 EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 322 EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDALT1 EEDATL0 322 — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 322 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 75 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 78 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by data EEPROM module. * Page provides register information. DS41364A-page 332 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 24.0 POWER-DOWN MODE (SLEEP) The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • • • • • • WDT will be cleared but keeps running. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. Oscillator driver is turned off. Timer1 oscillator is unaffected I/O ports maintain the status they had before SLEEP was executed (driving high, low or highimpedance). address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. The SLEEP instruction is completely executed. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin. I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. Enabled Resets remain functional during Sleep. 24.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. 2. 3. 4. 5. External Reset input on MCLR pin, if enabled. BOR Reset, if enabled. Watchdog Timer wake-up (if WDT was enabled). Any external interrupt. Certain peripheral interrupts (see individual peripheral for more information). The first two events will cause a device Reset. The last three events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. Certain peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt © 2008 Microchip Technology Inc. Preliminary DS41364A-page 333 PIC16F193X/LF193X 24.2 Wake-up Using Interrupts When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. • If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. FIGURE 24-1: Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1(1) TOST(2) CLKOUT(4) INT pin INTF flag (INTCON reg.) Interrupt Latency (3) GIE bit (INTCON reg.) Processor in Sleep Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: PC PC + 1 Inst(PC) = Sleep Inst(PC - 1) PC + 2 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) Dummy Cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) XT, HS or LP Oscillator mode assumed. TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference. TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 104 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 104 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 104 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 74 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 75 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 PIR2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 78 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode. DS41364A-page 334 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 25.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) Note: ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS 25.2 Entry into the Low-Voltage ICSP Program/Verify modes requires the following steps: MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. 1. 2. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. High-voltage Programming Mode The device is placed into high-voltage Program/Verify mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. FIGURE 25-1: Low-Voltage Programming Mode The Low-Voltage Programming mode allows the PIC16F193X/LF193X devices to be programmed using VDD only, without high voltage. When the LVP bit of the Configuration Word 2 register is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. In Program/Verify mode the Program Memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “PIC16193X/PIC16LF193X Memory Programming Specification” (DS41360A) 25.1 The ICD 2 produces a VPP voltage greater than the maximum VPP specification of the PIC16F193X/LF193X. When using this programmer, an external circuit is required to keep the VPP voltage within the device specifications. TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming Signals Device to be Programmed VDD VDD VDD 10k VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). © 2008 Microchip Technology Inc. Preliminary DS41364A-page 335 PIC16F193X/LF193X NOTES: DS41364A-page 336 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 26.0 INSTRUCTION SET SUMMARY 26.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. The literal and control category contains the most varied instruction word format. TABLE 26-1: Each PIC16 instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories. Table 26-3 lists the instructions recognized by the MPASMTM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: • Subroutine takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) • Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) • One additional instruction cycle will be used when any instruction references an indirect file register and the MSb of the appropriate file select register is set. One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. OPCODE FIELD DESCRIPTIONS Field f Description Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. n FSR or INDF number. (0-1) mm Pre-post increment-decrement mode selection TABLE 26-2: ABBREVIATION DESCRIPTIONS Field Program Counter TO Time-out bit C DC Z PD © 2008 Microchip Technology Inc. Description PC Preliminary Carry bit Digit carry bit Zero bit Power-down bit DS41364A-page 337 PIC16F193X/LF193X FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal) k = 11-bit immediate value MOVLP instruction only 13 OPCODE 7 6 0 k (literal) k = 7-bit immediate value MOVLB instruction only 13 OPCODE 5 4 0 k (literal) k = 5-bit immediate value BRA instruction only 13 OPCODE 9 8 0 k (literal) k = 9-bit immediate value FSR Offset instructions 13 OPCODE 7 6 n 5 0 k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 OPCODE 3 2 1 0 n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE DS41364A-page 338 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 26-3: PIC16F193X/LF193X ENHANCED INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ INCFSZ f, d f, d Decrement f, Skip if 0 Increment f, Skip if 0 BCF BSF f, b f, b Bit Clear f Bit Set f 1(2) 1(2) 00 00 1, 2 1, 2 1011 dfff ffff 1111 dfff ffff BIT-ORIENTED FILE REGISTER OPERATIONS 1 1 01 01 00bb bfff ffff 01bb bfff ffff 2 2 1, 2 1, 2 BIT-ORIENTED SKIP OPERATIONS BTFSC BTFSS f, b f, b Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 (2) 1 (2) 01 01 10bb bfff ffff 11bb bfff ffff 1 1 1 1 1 1 1 1 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 LITERAL OPERATIONS ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW k k k k k k k k Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z Z Z C, DC, Z Z Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 339 PIC16F193X/LF193X TABLE 26-3: PIC16F193X/LF193X ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPTION_REG register with W Software device Reset Go into Standby mode Load TRIS register with W ADDFSR MOVIW n, k mm n n mm k[n] mm n n mm k[n] Add Literal to FSRn Move INDFn to W, with pre/post inc/dec Move INDFn to W, with pre/post inc/dec Move INDFn to W, Indexed Indirect. Move W to INDFn, with pre/post inc/dec Move W to INDFn, with pre/post inc/dec Move W to INDFn, Indexed Indirect. 2 2 2 2 2 2 2 2 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 TO, PD 0000 0010 0001 0011 TO, PD 01kk 0001 0000 0000 1111 0000 0000 1111 0nkk 0001 0001 0nkk 0001 0001 1nkk kkkk 0mmn Z 0nmm Z kkkk Z 1mmn 1nmm kkkk INHERENT OPERATIONS 1 1 1 1 1 1 C-COMPILER OPTIMIZED MOVWI 1 1 1 1 1 1 1 11 00 00 11 00 00 11 2 2 2 2 2 2 Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. DS41364A-page 340 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 26.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR n, k Syntax: [ label ] ANDLW Operands: -32 ≤ k ≤ 31 n ∈ [ 0, 1] Operands: 0 ≤ k ≤ 255 Operation: (W) .AND. (k) → (W) Operation: FSR(n) + k → FSR(n) Status Affected: Z Status Affected: None Description: Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. The contents of W register are AND’ed with the eight-bit literal ‘k’. The result is placed in the W register. AND W with f k FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds will cause the FSR to wrap around. ADDLW Add literal and W ANDWF Syntax: [ label ] ADDLW Syntax: [ label ] ANDWF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .AND. (f) → (destination) k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. ADDWF Add W and f f,d Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ASRF Arithmetic Right Shift Syntax: [ label ] ADDWF Syntax: [ label ] ASRF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) + (f) → (destination) Operation: (f<7>)→ dest<7> (f<7:1>) → dest<6:0>, (f<0>) → C, f,d Status Affected: C, DC, Z Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWFC ADD W and CARRY bit to f Syntax: [ label ] ADDWFC Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) + (f) + (C) → dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. © 2008 Microchip Technology Inc. f {,d} Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. register f C f {,d} Preliminary DS41364A-page 341 PIC16F193X/LF193X BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 ≤ f ≤ 127 0≤b≤7 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operands: Operation: 0 → (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA Syntax: [ label ] BTFSS f,b Operands: -256 ≤ k ≤ 255 Operands: Operation: (PC) + k → PC 0 ≤ f ≤ 127 0≤b<7 Status Affected: None Operation: skip if (f<b>) = 1 Description: Add the signed 9-bit literal ‘k’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a two-cycle instruction. Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. k BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W) → PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a two-cycle instruction. BSF Bit Set f Syntax: [ label ] BSF Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 1 → (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. DS41364A-page 342 f,b Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 ≤ k ≤ 2047 Operands: None Operation: (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Operation: Status Affected: None 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. CALLW Subroutine Call With W COMF Complement f Syntax: [ label ] CALLW Syntax: [ label ] COMF Operands: None Operands: Operation: (PC) +1 → TOS, (W) → PC<7:0>, (PCLATH<6:0>) → PC<14:8> 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (destination) Status Affected: Z Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DECF Decrement f Syntax: [ label ] DECF f,d f,d Status Affected: None Description: Subroutine call with W. First, the return address (PC + 1) is pushed onto the return stack. Then, the contents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a two-cycle instruction. CLRF Clear f Syntax: [ label ] CLRF Operands: 0 ≤ f ≤ 127 Operands: Operation: 00h → (f) 1→Z 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are cleared and the Z bit is set. Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW f Operands: None Operation: 00h → (W) 1→Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 343 PIC16F193X/LF193X DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a NOP is executed instead, making it a 2-cycle instruction. Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, a NOP is executed instead, making it a 2-cycle instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] Syntax: [ label ] GOTO k INCFSZ f,d IORLW k Operands: 0 ≤ k ≤ 2047 Operands: 0 ≤ k ≤ 255 Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> Operation: (W) .OR. k → (W) Status Affected: Z Status Affected: None Description: Description: GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. The contents of the W register are OR’ed with the eight-bit literal ‘k’. The result is placed in the W register. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (destination) Operation: (W) .OR. (f) → (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. DS41364A-page 344 INCF f,d Preliminary IORWF f,d © 2008 Microchip Technology Inc. PIC16F193X/LF193X LSLF Logical Left Shift MOVF Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<7>) → C (f<6:0>) → dest<7:1> 0 → dest<0> Operation: (f) → (dest) f {,d} Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. C register f 0 Z Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. Words: 1 Cycles: 1 Logical Right Shift Syntax: [ label ] LSLF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: 0 → dest<7> (f<7:1>) → dest<6:0>, (f<0>) → C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. A ‘0’ is shifted into the MSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2008 Microchip Technology Inc. MOVF FSR, 0 After Instruction W = value in FSR register Z = 1 LSRF f {,d} register f MOVF f,d Status Affected: Example: 0 Move f C Preliminary DS41364A-page 345 PIC16F193X/LF193X MOVIW Move INDFn to W MOVLP Syntax: [ label ] MOVIW ++INDFn [ label ] MOVIW --INDFn [ label ] MOVIW INDFn++ [ label ] MOVIW INDFn-[ label ] MOVIW [k]INDFn [ label ] MOVIW INDFn Syntax: [ label ] MOVLP k Operands: 0 ≤ k ≤ 127 Operands: n ∈ [0,1] mm ∈ [00, 01, 10, 11]. -32 ≤ k ≤ 31 If not present, k = 0. Operation: INDFn → W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) • Unchanged Move literal to PCLATH Operation: k → PCLATH Status Affected: None Description: The seven-bit literal ‘k’ is loaded into the PCLATH register. MOVLW Move literal to W Syntax: [ label ] MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W) Status Affected: None Description: The eight-bit literal ‘k’ is loaded into W register. The “don’t cares” will assemble as ‘0’s. Words: 1 Cycles: 1 Status Affected: Z mm Mode Syntax 00 Preincrement ++INDFn 01 Predecrement --INDFn 10 Postincrement INDFn++ MOVWF Move W to f 11 Postdecrement INDFn-- Syntax: [ label ] Description: This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Example: FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap around. Move literal to BSR Syntax: [ label ] MOVLB k Operands: 0 ≤ k ≤ 15 Operation: k → BSR Status Affected: None Description: The five-bit literal ‘k’ is loaded into the Bank Select Register (BSR). DS41364A-page 346 0x5A 0x5A MOVWF Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) f Status Affected: None Description: Move data from W register to register ‘f’. Words: 1 Cycles: 1 Example: The increment/decrement operation on FSRn WILL NOT affect any Status bits. MOVLB MOVLW After Instruction W = Preliminary MOVWF OPTION Before Instruction OPTION W After Instruction OPTION W = = 0xFF 0x4F = = 0x4F 0x4F © 2008 Microchip Technology Inc. PIC16F193X/LF193X MOVWI Move W to INDFn NOP No Operation Syntax: [ label ] MOVWI ++INDFn [ label ] MOVWI --INDFn [ label ] MOVWI INDFn++ [ label ] MOVWI INDFn-[ label ] MOVWI [k]INDFn [ label ] MOVWI INDFn Syntax: [ label ] Operands: None n ∈ [0,1] mm ∈ [00, 01, 10, 11]. -32 ≤ k ≤ 31 If not present, k = 0. Description: No operation. Words: 1 Cycles: 1 Operands: Operation: W → INDFn Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) Unchanged Status Affected: None mm Mode 00 Preincrement ++INDFn 01 Predecrement --INDFn 10 Postincrement INDFn++ 11 Postdecrement INDFn-- Description: Syntax This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. NOP Operation: No operation Status Affected: None Example: NOP OPTION Load OPTION_REG Register with W Syntax: [ label ] OPTION Operands: None Operation: (W) → OPTION_REG Status Affected: None Description: Move data from W register to OPTION_REG register. RESET Software Reset Syntax: [ label ] RESET Operands: None Operation: Execute a device Reset. Resets the nRI flag of the PCON register. Status Affected: None Description: This instruction provides a way to execute a hardware Reset by software. FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap around. The increment/decrement operation on FSRn WILL NOT affect any Status bits. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 347 PIC16F193X/LF193X RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] None RETFIE RETURN Operands: None Operands: Operation: TOS → PC, 1 → GIE Operation: TOS → PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = GIE = TOS 1 Return with literal in W RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: k → (W); TOS → PC 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Status Affected: None Status Affected: C Description: The W register is loaded with the eight bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Words: 1 Cycles: 2 RETLW Example: TABLE RETLW k C CALL TABLE;W contains table ;offset value • ;W now has table value • • ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ; End of table Before Instruction W = After Instruction W = DS41364A-page 348 RLF Words: 1 Cycles: 1 Example: RLF f,d Register f REG1,0 Before Instruction REG1 C After Instruction REG1 W C = = 1110 0110 0 = = = 1110 0110 1100 1100 1 0x07 value of k8 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. RRF f,d C SUBLW k Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) Register f C=0 W>k C=1 W≤k DC = 0 W<3:0> > k<3:0> DC = 1 W<3:0> ≤ k<3:0> SLEEP Enter Sleep mode SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (destination) Status Affected: C, DC, Z Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f. SLEEP Operands: None Operation: 00h → WDT, 0 → WDT prescaler, 1 → TO, 0 → PD Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. © 2008 Microchip Technology Inc. SUBWF f,d C=0 W>f C=1 W≤f DC = 0 W<3:0> > f<3:0> DC = 1 W<3:0> ≤ f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) – (W) – (B) → dest f {,d} Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Preliminary DS41364A-page 349 PIC16F193X/LF193X SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. Operation: SWAPF f,d XORLW k Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. TRIS Load TRIS Register with W XORWF Exclusive OR W with f Syntax: [ label ] TRIS f Syntax: [ label ] Operands: 5≤f≤7 Operands: Operation: (W) → TRIS register ‘f’ 0 ≤ f ≤ 127 d ∈ [0,1] Status Affected: None Operation: (W) .XOR. (f) → (destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: DS41364A-page 350 Move data from W register to TRIS register. When ‘f’ = 5, TRISA is loaded. When ‘f’ = 6, TRISB is loaded. When ‘f’ = 7, TRISC is loaded. Preliminary XORWF f,d © 2008 Microchip Technology Inc. PIC16F193X/LF193X 27.0 DEVELOPMENT SUPPORT 27.1 The PIC® microcontrollers are supported with a full range of hardware and software development tools: • Integrated Development Environment - MPLAB® IDE Software • Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debugger - MPLAB ICD 2 • Device Programmers - PICSTART® Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Visual device initializer for easy register initialization • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 351 PIC16F193X/LF193X 27.2 MPASM Assembler 27.5 The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 27.6 27.3 MPLAB C18 and MPLAB C30 C Compilers The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip’s PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 27.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. MPLAB ASM30 Assembler, Linker and Librarian MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS41364A-page 352 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 27.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 27.9 The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were chosen to best make these features available in a simple, unified application. 27.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. 27.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 353 PIC16F193X/LF193X 27.11 PICSTART Plus Development Programmer 27.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. 27.12 PICkit 2 Development Programmer The PICkit™ 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip’s baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH’s PICC™ Lite C compiler, and is designed to help get up to speed quickly using PIC® microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip’s powerful, mid-range Flash memory family of microcontrollers. DS41364A-page 354 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 28.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16F193X ............................................................................. -0.3V to +6.5V Voltage on VDD with respect to VSS, PIC16LF193X ........................................................................... -0.3V to +4.0V Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ...................................................................................................................... 95 mA Maximum current into VDD pin ......................................................................................................................... 70 mA Clamp current, IK (VPIN < 0 or VPIN > VDD)................................................................................................................± 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by all ports(2), -40°C ≤ TA ≤ +85°C for industrial ........................................................ 200 mA Maximum current sunk by all ports(2), -40°C ≤ TA ≤ +125°C for extended........................................................ 90 mA Maximum current sourced by all ports(2), 40°C ≤ TA ≤ +85°C for industrial ................................................... 140 mA Maximum current sourced by all ports(2), -40°C ≤ TA ≤ +125°C for extended................................................... 65 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 355 PIC16F193X/LF193X PIC16F193X VOLTAGE FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 28-1: VDD (V) 5.5 3.6 2.5 2.3 2.0 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 28-1 for each Oscillator mode’s supported frequencies. PIC16LF193X VOLTAGE FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C VDD (V) FIGURE 28-2: 3.6 2.5 2.3 2.0 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 28-1 for each Oscillator mode’s supported frequencies. DS41364A-page 356 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 28-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 + 5% Temperature (°C) 85 60 ± 2% 25 0 -20 + 5% -40 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2008 Microchip Technology Inc. Preliminary DS41364A-page 357 PIC16F193X/LF193X 28.1 DC Characteristics: PIC16F193X/LF193X-I/E (Industrial, Extended) PIC16LF193X Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended PIC16F193X Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param. No. D001 Sym. VDD D001 D002* VDR D002* Characteristic Min. Typ† Max. Units PIC16LF193X 1.8 2.3 — — 3.6 3.6 V V FOSC ≤ 16 MHz: FOSC ≤ 32 MHz (NOTE 2) PIC16F193X 1.8 2.3 — — 5.5 5.5 V V FOSC ≤ 16 MHz: FOSC ≤ 32 MHz (NOTE 2) Supply Voltage RAM Data Retention Voltage(1) PIC16LF193X 1.5 — — V Device in Sleep mode PIC16F193X 1.7 — — V Device in Sleep mode — 1.6 — V PIC16LF193X — 0.8 — V Device in Sleep mode PIC16F193X — 1.7 — V Device in Sleep mode 0.984 0.974 1.968 1.938 3.966 3.936 1.024 1.064 1.064 2.158 2.148 4.226 4.226 V FVRV = 00 (1x), VDD ≥ 2.5V 125°C FVRV = 01 (2x), VDD ≥ 2.5V 125°C FVRV = 10 (4x), VDD ≥ 4.75V 125°C 0.984 0.974 1.968 1.938 3.966 3.936 1.024 1.064 1.064 2.158 2.148 4.226 4.226 V FVRV = 00 (1x), VDD ≥ 2.5V 125°C FVRV = 01 (2x), VDD ≥ 2.5V 125°C FVRV = 10 (4x), VDD ≥ 4.75V 125°C 0.984 0.974 1.024 1.064 1.064 V FVRV = 00 (1x), VDD ≥ 2.5V 125°C 0.05 — — V/ms VPOR* Power-on Reset Release Voltage VPORR* Power-on Reset Rearm Voltage VADFVR VCDAFVR Fixed Voltage Reference Voltage for ADC (calibrated) Fixed Voltage Reference Voltage for Comparator and DAC VFVR_REF Fixed Voltage Reference Voltage for LCD Bias D004* SVDD Conditions VDD Rise Rate to ensure internal Power-on Reset signal 2.048 4.096 2.048 4.096 See Section 3.2 “Power-on Reset (POR)” for details. * † Note These parameters are characterized but not tested. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: PLL required for 32 MHz operation. DS41364A-page 358 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 28-4: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 μs typical. TVLOW 2.7 μs typical. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 359 PIC16F193X/LF193X 28.2 DC Characteristics: PIC16F193X/LF193X-I/E (Industrial, Extended) PIC16LF193X Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended PIC16F193X Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max. Units VDD Note Supply Current (IDD)(1, 2) D009 LDO Regulator D010 D010 D011* D011* — 350 TBD μA — HS, EC OR INTOSC/INTOSCIO (8-16 MHZ) Clock modes with all VCAP pins disabled — 50 TBD μA — All VCAP pins disabled — 30 TBD μA — VCAP enabled on RA0, RA5 or RA6 — 5 TBD μA — LP Clock mode and Sleep (requires FVR and BOR to be disabled) — 7.0 TBD μA 1.8 — 9.0 TBD μA 3.0 FOSC = 32 kHz LP Oscillator mode (Note 4), -40°C ≤ TA ≤ +85°C — 9.5 TBD μA 1.8 — 12.5 TBD μA 3.0 — 13.5 TBD μA 5.0 — 7.0 TBD μA 1.8 — 9.0 TBD μA 3.0 — 9.5 TBD μA 1.8 — 12.5 TBD μA 3.0 — 13.5 TBD μA 5.0 D011A* — 150 TBD μA 1.8 — 270 TBD μA 3.0 D011A* — 160 TBD μA 1.8 — 280 TBD μA 3.0 — 390 TBD μA 5.0 — 430 TBD μA 1.8 — 750 TBD μA 3.0 — 450 TBD μA 1.8 — 770 TBD μA 3.0 D012 D012 D013* — 930 TBD μA 5.0 — 180 TBD μA 1.8 — 350 TBD μA 3.0 FOSC = 32 kHz LP Oscillator mode (Note 4), -40°C ≤ TA ≤ +85°C FOSC = 32 kHz LP Oscillator mode FOSC = 32 kHz LP Oscillator mode (Note 4) FOSC = 1 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode (Note 5) FOSC = 4 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode (Note 5) FOSC = 1 MHz EC Oscillator mode * These parameters are characterized but not tested. Legend: TBD = To Be Determined Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in kΩ. 4: FVR and BOR are disabled. 5: 0.1 μF capacitor on VCAP (RA0). DS41364A-page 360 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 28.2 DC Characteristics: PIC16F193X/LF193X-I/E (Industrial, Extended) (Continued) PIC16LF193X Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended PIC16F193X Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Conditions Device Characteristics Min. Typ† Max. Units VDD — 200 TBD μA 1.8 — 370 TBD μA 3.0 — 450 TBD μA 5.0 D014 — 450 TBD μA 1.8 — 830 TBD μA 3.0 D014 — 475 TBD μA 1.8 — 850 TBD μA 3.0 D013* Supply Current (IDD) Note FOSC = 1 MHz EC Oscillator mode (Note 5) (1, 2) D015 D015 D016* D016* — 980 TBD μA 5.0 — 130 TBD μA 1.8 — 190 TBD μA 3.0 — 150 TBD μA 1.8 — 210 TBD μA 3.0 — 270 TBD μA 5.0 — 980 TBD μA 1.8 — 1780 TBD μA 3.0 — 1.0 TBD mA 1.8 — 1.8 TBD mA 3.0 TBD mA 5.0 TBD mA 1.8 — 2.0 D017 — 1.5 — 2.8 TBD mA 3.0 D017 — 1.7 TBD mA 1.8 — 2.9 TBD mA 3.0 — 3.1 TBD mA 5.0 D018 — 410 TBD μA 1.8 — 710 TBD μA 3.0 D018 — 430 TBD μA 1.8 — 730 TBD μA 3.0 D019 — 860 TBD μA 5.0 — 5.3 TBD mA 3.0 — 6.0 TBD mA 3.6 FOSC = 4 MHz EC Oscillator mode FOSC = 4 MHz EC Oscillator mode (Note 5) FOSC = 500 kHz MFINTOSC mode FOSC = 500 kHz MFINTOSC mode (Note 5) FOSC = 8 MHz HFINTOSC mode FOSC = 8 MHz HFINTOSC mode (Note 5) FOSC = 16 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode (Note 5) FOSC = 4 MHz EXTRC mode (Note 3, Note 5) FOSC = 4 MHz EXTRC mode (Note 3, Note 5) FOSC = 32 MHz HS Oscillator mode * These parameters are characterized but not tested. Legend: TBD = To Be Determined Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in kΩ. 4: FVR and BOR are disabled. 5: 0.1 μF capacitor on VCAP (RA0). © 2008 Microchip Technology Inc. Preliminary DS41364A-page 361 PIC16F193X/LF193X 28.2 DC Characteristics: PIC16F193X/LF193X-I/E (Industrial, Extended) (Continued) PIC16LF193X Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended PIC16F193X Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Characteristics D019 Conditions Min. Typ† Max. Units VDD — 5.3 TBD mA 3.0 — 6.0 TBD mA 5.0 Note FOSC = 32 MHz HS Oscillator mode (Note 5) * These parameters are characterized but not tested. Legend: TBD = To Be Determined Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in kΩ. 4: FVR and BOR are disabled. 5: 0.1 μF capacitor on VCAP (RA0). DS41364A-page 362 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 28.3 DC Characteristics: PIC16F193X/LF193X-I/E (Power-Down) PIC16LF193X Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended PIC16F193X Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Characteristics Power-down Base Current Min. Typ† Conditions Max. +85°C Max. +125°C Units μA VDD D020 — 0.06 TBD TBD — 0.08 TBD TBD μA 3.0 D020 — 3.1 TBD TBD μA 1.8 — 3.6 TBD TBD μA 3.0 — 4.5 TBD TBD μA 5.0 — 0.5 TBD TBD μA 1.8 — 0.8 TBD TBD μA 3.0 — 3.8 TBD TBD μA 1.8 — 4.3 TBD TBD μA 3.0 D021 D021 D021A D021A 1.8 — 5.3 TBD TBD μA 5.0 — 8.5 TBD TBD μA 1.8 — 8.5 TBD TBD μA 3.0 — 32 TBD TBD μA 1.8 — 39 TBD TBD μA 3.0 — 70 TBD TBD mA 5.0 D022 — — TBD TBD μA 1.8 — 7.5 TBD TBD μA 3.0 D022 — — TBD TBD μA 1.8 — 34 TBD TBD μA 3.0 — 67 TBD TBD μA 5.0 — 0.6 TBD TBD μA 1.8 — 1.8 TBD TBD μA 3.0 — 4.5 TBD TBD μA 1.8 — 6 TBD TBD μA 3.0 — 7 TBD TBD μA 5.0 D026 D026 * † Legend: Note 1: 2: 3: 4: 5: Note (IPD)(2) WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive LPWDT Current (Note 1) LPWDT Current (Note 1) FVR current (Note 3) FVR current (Note 3, Note 5) BOR Current (Note 1, Note 3) BOR Current (Note 1, Note 3, Note 5) T1OSC Current (Note 1) T1OSC Current (Note 1) These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TBD = To Be Determined The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. Fixed Voltage Reference is automatically enabled whenever the BOR is enabled. A/D oscillator source is FRC. 0.1 μF capacitor on VCAP (RA0). © 2008 Microchip Technology Inc. Preliminary DS41364A-page 363 PIC16F193X/LF193X 28.3 DC Characteristics: PIC16F193X/LF193X-I/E (Power-Down) (Continued) PIC16LF193X Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended PIC16F193X Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Characteristics Min. Power-down Base Current (IPD) D027 D027 Typ† Conditions Max. +85°C Max. +125°C Units VDD Note A/D Current (Note 1, Note 4), no conversion in progress (2) — 0.1 TBD TBD μA 1.8 — 0.1 TBD TBD μA 3.0 — 3.5 TBD TBD μA 1.8 — 4 TBD TBD μA 3.0 — 4.5 TBD TBD μA 5.0 D027A — 250 TBD TBD μA 1.8 — 250 TBD TBD μA 3.0 D027A — 280 TBD TBD μA 1.8 — 280 TBD TBD μA 3.0 — 280 TBD TBD μA 5.0 — 3.5 TBD TBD μA 1.8 — 7 TBD TBD μA 3.0 — 3.5 TBD TBD μA 1.8 — 7 TBD TBD μA 3.0 D028 D028 D029 D029 * † Legend: Note 1: 2: 3: 4: 5: A/D Current (Note 1, Note 4), no conversion in progress A/D Current (Note 1, Note 4), conversion in progress A/D Current (Note 1, Note 4, Note 5), conversion in progress Cap Sense Cap Sense — 32 TBD TBD μA 5.0 — 1 TBD TBD μA 3.6 LCD Bias Ladder, Low-power — 10 TBD TBD μA 3.6 LCD Bias Ladder, Medium-power — 100 TBD TBD μA 3.6 LCD Bias Ladder, High-power — 1 TBD TBD μA 5.0 LCD Bias Ladder, Low-power — 10 TBD TBD μA 5.0 LCD Bias Ladder, Medium-power — 100 TBD TBD μA 5.0 LCD Bias Ladder, High-power These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TBD = To Be Determined The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. Fixed Voltage Reference is automatically enabled whenever the BOR is enabled. A/D oscillator source is FRC. 0.1 μF capacitor on VCAP (RA0). DS41364A-page 364 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 28.4 DC Characteristics: PIC16F193X/LF193X-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min. Typ† Max. Units — — with Schmitt Trigger buffer with I2C™ levels Conditions — 0.8 V 4.5V ≤ VDD ≤ 5.5V — 0.15 VDD V 1.8V ≤ VDD ≤ 4.5V — — 0.2 VDD V 2.0V ≤ VDD ≤ 5.5V — — 0.3 VDD V Input Low Voltage I/O PORT: D030 with TTL buffer D030A D031 D032 D033A VIH — — 0.8 V — — 0.2 VDD V OSC1 (HS mode) — — 0.3 VDD V — — 2.0 — — V 4.5V ≤ VDD ≤ 5.5V 0.25 VDD + 0.8 — — V 1.8V ≤ VDD ≤ 4.5V with Schmitt Trigger buffer 0.8 VDD — — V 2.0V ≤ VDD ≤ 5.5V with I2C™ levels 0.7 VDD — — V Input High Voltage I/O ports: D040 with TTL buffer D040A D041 2.7V ≤ VDD ≤ 5.5V with SMBus™ levels MCLR, OSC1 (RC mode)(1) with SMBus™ levels 2.7V ≤ VDD ≤ 5.5V 2.1 — — V D042 MCLR 0.8 VDD — — V D043A OSC1 (HS mode) 0.7 VDD — — V D043B OSC1 (RC mode) 0.9 VDD — — V (Note 1) VSS ≤ VPIN ≤ VDD, Pin at highimpedance 125°C IIL Input Leakage Current(2) D060 I/O ports — ±5 ± 100 nA ±5 ± 1000 nA D061 MCLR(3) — ± 50 ± 200 nA VSS ≤ VPIN ≤ VDD D063 OSC1 — ± 50 ± 100 nA VSS ≤ VPIN ≤ VDD, XT, HS and LP oscillator configuration 25 25 100 140 200 300 μA VDD = 3.3V, VPIN = VSS VDD = 5.0V, VPIN = VSS — — 0.6 V IOH = 8mA, VDD = 5V IOH = 6mA, VDD = 3.3V IOH = 3mA, VDD = 1.8V IPUR Weak Pull-up Current D070* VOL D080 Output Low Voltage(4) I/O ports Legend: * † Note 1: 2: 3: 4: TBD = To Be Determined These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 365 PIC16F193X/LF193X 28.4 DC Characteristics: PIC16F193X/LF193X-I/E (Continued) DC CHARACTERISTICS Param No. Sym. VOH D090 Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min. Typ† Max. Units VDD - 0.7 — — V — — 15 pF — — 50 pF Conditions Output High Voltage(4) I/O ports IOH = 3.5mA, VDD = 5V IOH = 3mA, VDD = 3.3V IOH = 2mA, VDD = 1.8V Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin D101A* CIO All I/O pins In XT, HS and LP modes when external clock is used to drive OSC1 VCAP Capacitor Charging D102 Charging current — 200 — μA D102A Source/sink capability when charging complete — 0.0 — mA Legend: * † Note 1: 2: 3: 4: TBD = To Be Determined These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode. DS41364A-page 366 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 28.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP/RE3 pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA VDD for Bulk Erase 2.7 — VDD max. V D112 D113 VPEW VDD for Write or Row Erase VDD min. — VDD max. V D114 IPPPGM Current on MCLR/VPP during Erase/ Write — — 1.0 mA D115 IDDPGM Current on VDD during Erase/Write — 5.0 mA D116 ED Byte Endurance D117 VDRW VDD for Read/Write D118 TDEW (Note 3, Note 4) Data EEPROM Memory — 100K — E/W VDD min. — VDD max. V Erase/Write Cycle Time — 4.0 5.0 ms D119 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D120 TREF 1M 10M — E/W -40°C to +85°C D121 EP Cell Endurance — 10K — E/W -40°C to +85°C (Note 1) D122 VPR VDD for Read VDD min. — VDD max. V D123 TIW Self-timed Write Cycle Time — 2 2.5 ms D124 TRETD Characteristic Retention 40 — — Year Number of Total Erase/Write Cycles before Refresh(2) -40°C to +85°C Program Flash Memory Provided no other specifications are violated † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Refer to Section 23.5.1 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. 4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD 2. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 367 PIC16F193X/LF193X 28.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic θJA Thermal Resistance Junction to Ambient θJC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 60 °C/W 28-pin SPDIP package 80 °C/W 28-pin SOIC package 90 °C/W 28-pin SSOP package 27.5 °C/W 28-pin QFN 6x6mm package 47.2 °C/W 40-pin PDIP package 46 °C/W 44-pin TQFP package 24.4 °C/W 44-pin QFN 8x8mm package 31.4 °C/W 28-pin SPDIP package 24 °C/W 28-pin SOIC package 24 °C/W 28-pin SSOP package 24 °C/W 28-pin QFN 6x6mm package 24.7 °C/W 40-pin PDIP package 14.5 °C/W 44-pin TQFP package 20 °C/W 44-pin QFN 8x8mm package 150 °C — W PD = PINTERNAL + PI/O — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O = Σ (IOL * VOL) + Σ (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/θJA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature 3: TJ = Junction Temperature DS41364A-page 368 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 28.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 28-5: T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins, 15 pF for OSC2 output © 2008 Microchip Technology Inc. Preliminary DS41364A-page 369 PIC16F193X/LF193X 28.8 AC Characteristics: PIC16F193X/LF193X-I/E FIGURE 28-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 28-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) OS02 TOSC External CLKIN Period(1) Oscillator Period(1) OS03 TCY Instruction Cycle Time(1) OS04* TosH, TosL External CLKIN High, External CLKIN Low TosR, TosF External CLKIN Rise, External CLKIN Fall OS05* Min. Typ† Max. Units Conditions DC — 1 MHz EC Oscillator mode (low) DC — 4 MHz EC Oscillator mode (medium) DC — 32 MHz EC Oscillator mode (high) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 4 MHz HS Oscillator mode, VDD ≤ 2.3V 1 — 20 MHz HS Oscillator mode, VDD > 2.3V DC — 4 MHz RC Oscillator mode 27 — ∞ μs LP Oscillator mode 250 — ∞ ns XT Oscillator mode 50 — ∞ ns HS Oscillator mode 31.25 — ∞ ns EC Oscillator mode — 30.5 — μs LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode 200 TCY DC ns TCY = 4/FOSC 2 — — μs LP oscillator 100 — — ns XT oscillator 20 — — ns HS oscillator 0 — ∞ ns LP oscillator 0 — ∞ ns XT oscillator 0 — ∞ ns HS oscillator * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. DS41364A-page 370 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 28-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. OS08 Sym. HFOSC OS08A MFOSC OS10* Freq. Tolerance Characteristic Min. Typ† Max. Units Conditions Internal Calibrated HFINTOSC Frequency(2) ±2% — 16.0 — MHz 0°C ≤ TA ≤ +85°C ±5% — 16.0 — MHz -40°C ≤ TA ≤ +125°C Internal Calibrated MFINTOSC Frequency(2) ±2% — 500 — kHz 0°C ≤ TA ≤ +85°C ±5% — 500 — kHz -40°C ≤ TA ≤ +125°C — — 5 7 μs VDD = 2.0V, -40°C to +85°C — — 5 7 μs VDD = 3.0V, -40°C to +85°C — — 5 7 μs VDD = 5.0V, -40°C to +85°C TIOSC ST HFINTOSC and MFINTOSC Wake-up from Sleep Start-up Time * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. 3: By design. TABLE 28-3: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V) Sym. Characteristic Min. F10 FOSC Oscillator Frequency Range F11 FSYS On-Chip VCO System Frequency F12 TRC PLL Start-up Time (Lock Time) F13* ΔCLK CLKOUT Stability (Jitter) Typ† Max. Units 4 — 8 MHz 16 — 32 MHz — — 2 ms -0.25% — +0.25% % Conditions * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 371 PIC16F193X/LF193X FIGURE 28-7: Cycle CLKOUT AND I/O TIMING Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS16 OS13 OS18 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 DS41364A-page 372 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 28-4: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions — — 70 ns VDD = 3.3-5.0V — — 72 ns VDD = 3.3-5.0V FOSC↑ to CLKOUT↓ (1) OS11 TosH2ckL OS12 TosH2ckH FOSC↑ to CLKOUT↑ (1) (1) OS13 TckL2ioV CLKOUT↓ to Port out valid OS14 OS15 OS16 TioV2ckH TosH2ioV TosH2ioI OS17 TioV2osH OS18 TioR Port input valid before CLKOUT↑(1) Fosc↑ (Q1 cycle) to Port out valid Fosc↑ (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to Fosc↑ (Q2 cycle) (I/O in setup time) Port output rise time(2) OS19 TioF Port output fall time(2) — — 20 ns TOSC + 200 ns — 50 — 50 — — 70* — ns ns ns 20 — — ns — — — — 25 25 40 15 28 15 — — 72 32 55 30 — — ns OS20* Tinp OS21* Tioc INT pin input high or low time Interrupt-on-change new input level time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Includes OSC2 in CLKOUT mode. FIGURE 28-8: ns VDD = 3.3-5.0V VDD = 3.3-5.0V VDD = 1.8V VDD = 3.3-5.0V VDD = 1.8V VDD = 3.3-5.0V ns ns RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 34 31 34 I/O pins Note 1: Asserted low. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 373 PIC16F193X/LF193X FIGURE 28-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2 ms delay if PWRTE = 0 and VREGEN = 1. DS41364A-page 374 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 28-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic MCLR Pulse Width (low) Min. Typ† Max. Units Conditions 2 5 — — — — μs μs VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 10 10 18 18 27 33 ms ms VDD = 3.3V-5V, -40°C to +85°C VDD = 3.3V-5V 30 TMCL 31 TWDTLP Low-Power Watchdog Timer Time-out Period (No Prescaler) 32 TOST Oscillator Start-up Timer Period(1), (2) — 1024 — Tosc (Note 3) 33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low or Watchdog Timer Reset — — 2.0 μs 35 VBOR Brown-out Reset Voltage 2.40 1.80 2.5 1.9 2.60 2.00 V 36* VHYST Brown-out Reset Hysteresis 25 50 75 100 mV -40°C to +85°C -40°C to 125°C 37* TBORDC Brown-out Reset DC Response Time 1 3 5 10 μs VDD ≤ VBOR, -40°C to +85°C VDD ≤ VBOR * † Note 1: 2: 3: 4: BORV=2.5V BORV=1.9V These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. By design. Period of the slower clock. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 375 PIC16F193X/LF193X FIGURE 28-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 28-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler TT0L T0CKI Low Pulse Width No Prescaler TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler — — ns — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or TCY + 40 N — — ns 0.5 TCY + 20 — — ns 15 — — ns Asynchronous TT1L 46* T1CKI Low Time 30 — — ns Synchronous, No Prescaler 0.5 TCY + 20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Greater of: 30 or TCY + 40 N — — ns 47* TT1P T1CKI Input Synchronous Period 48 FT1 Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment Asynchronous * † Units 10 With Prescaler 42* Max. 0.5 TCY + 20 With Prescaler 41* Typ† 60 — — ns 32.4 32.768 33.1 kHz 2 TOSC — 7 TOSC — Conditions N = prescale value (2, 4, ..., 256) N = prescale value (1, 2, 4, 8) Timers in Sync mode These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41364A-page 376 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 28-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 28.5 for load conditions. TABLE 28-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym. No. Characteristic CC01* TccL CCPx Input Low Time CC02* TccH CCPx Input High Time CC03* TccP * † Min. Typ† Max. Units 0.5TCY + 20 — — ns With Prescaler 20 — — ns No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns 3TCY + 40 N — — ns No Prescaler CCPx Input Period Conditions N = prescale value (1, 4 or 16) These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 28-8: PIC16F193X/LF193X A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 AD02 EIL Integral Error — — ±1 LSb VREF = 3.0V AD03 EDL Differential Error — — ±1 LSb No missing codes VREF = 3.0V AD04 EOFF Offset Error — — ±3 LSb VREF = 3.0V AD05 EGN LSb VREF = 3.0V AD06 VREF Reference Voltage(3) AD07 VAIN Full-Scale Range AD08 ZAIN AD09* IREF * † Note 1: 2: 3: 4: Gain Error bit — — ±3 1.8 — VDD VSS — VREF Recommended Impedance of Analog Voltage Source — — 50 VREF Input Current(3) 10 — 1000 μA During VAIN acquisition. Based on differential of VHOLD to VAIN. — — 10 μA During A/D conversion cycle. V V kΩ Can go higher if external 0.01μF capacitor is present on input pin. These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Total Absolute Error includes integral, differential, offset and gain errors. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. ADC VREF is from external VREF, VDD pin or FVREF, whichever is selected as reference input. When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 377 PIC16F193X/LF193X TABLE 28-9: PIC16F193X/LF193X A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic AD130* TAD AD131 TCNV AD132* TACQ Min. Typ† Max. Units Conditions A/D Clock Period 1.0 — 9.0 μs TOSC-based A/D Internal RC Oscillator Period 1.0 1.6 6.0 μs ADCS<1:0> = 11 (ADRC mode) Conversion Time (not including Acquisition Time)(1) — 10.5 — TAD Set GO/DONE bit to conversion complete Acquisition Time — 9.5 — μs * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. FIGURE 28-12: PIC16F193X/LF193X A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 3 OLD_DATA ADRES 1 0 NEW_DATA 1 TCY ADIF GO Sample 2 DONE AD132 Sampling Stopped Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. DS41364A-page 378 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 28-13: PIC16F193X/LF193X A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample AD132 Sampling Stopped Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 379 PIC16F193X/LF193X TABLE 28-10: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param No. Sym. Characteristics Min. Typ. Max. Units CM01 VIOFF Input Offset Voltage — ±7.5 ±15 mV CM02 VICM Input Common Mode Voltage 0 — VDD V CM03 CMRR Common Mode Rejection Ratio 55 — — dB CM04 TRESP Response Time — 150 400 ns CM05 TMC2OV Comparator Mode Change to Output Valid* — — 10 μs * Note 1: Comments Note 1 These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. TABLE 28-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param No. Sym. Characteristics Min. Typ. Max. Units — VDD/32 — V CLSB Step Size(2) DAC02* CACC Absolute Accuracy — — ± 1/2 LSb DAC03* CR Unit Resistor Value (R) — TBD — Ω CST Time(1) — — 10 μs DAC01* DAC04* Settling Comments * These parameters are characterized but not tested. Legend: TBD = To Be Determined Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’. TABLE 28-12: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). VR Voltage Reference Specifications Param No. VR01 Sym. VFVR Characteristics Fixed Voltage Reference Voltage (calibrated) Voltage drift temperature coefficient Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Min. Typ. Max. Units Comments 0.984 0.974 1.968 1.938 3.966 3.936 1.024 1.064 1.064 2.158 2.148 4.226 4.226 V FVRV = 00 (1x), VDD ≥ 2V 125°C FVRV = 01 (2x), VDD ≥ 2.5V 125°C FVRV = 10 (4x), VDD ≥ 4.75V 125°C — TBD TBD ppm/°C 2.048 4.096 VR02 TCVOUT VR03 ΔVROUT/ Voltage drift with respect to ΔVDD VDD regulation — TBD — μV/V VR04 TSTABLE — TBD TBD μs Settling Time Legend: TBD = To Be Determined * These parameters are characterized but not tested. DS41364A-page 380 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 28-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 28-5 for load conditions. TABLE 28-13: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param. No. Symbol Characteristic Min. Max. Units US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V — 80 ns 1.8-5.5V — 100 ns US121 TCKRF Clock out rise time and fall time (Master mode) 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns Data-out rise time and fall time 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns US122 TDTRF FIGURE 28-15: Conditions USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 28-5 for load conditions. TABLE 28-14: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param. No. Symbol Characteristic US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK ↓ (DT hold time) US126 TCKL2DTL Data-hold after CK ↓ (DT hold time) © 2008 Microchip Technology Inc. Preliminary Min. Max. Units 10 — ns 15 — ns Conditions DS41364A-page 381 PIC16F193X/LF193X FIGURE 28-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 28-5 for load conditions. FIGURE 28-17: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SP78 SDO MSb bit 6 - - - - - -1 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 28-5 for load conditions. DS41364A-page 382 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 28-18: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 28-5 for load conditions. FIGURE 28-19: SS SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 MSb SDO bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 28-5 for load conditions. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 383 PIC16F193X/LF193X TABLE 28-15: SPI MODE REQUIREMENTS Param No. Symbol Characteristic SP70* TSSL2SCH, SS↓ to SCK↓ or SCK↑ input TSSL2SCL Min. Typ† Max. Units Conditions TCY — — ns SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns SP73* TDIV2SCH, Setup time of SDI data input to SCK edge TDIV2SCL 100 — — ns SP74* TSCH2DIL, TSCL2DIL Hold time of SDI data input to SCK edge 100 — — ns SP75* TDOR SDO data output rise time — 10 25 ns SP76* TDOF SDO data output fall time 3.0-5.5V 1.8-5.5V — 25 50 ns — 10 25 ns SP77* TSSH2DOZ SS↑ to SDO output high-impedance 10 — 50 ns SP78* TSCR SCK output rise time (Master mode) 3.0-5.5V — 10 25 ns 1.8-5.5V — 25 50 ns SP79* TSCF SCK output fall time (Master mode) — 10 25 ns 3.0-5.5V — — 50 ns 1.8-5.5V — — 145 ns SP81* TDOV2SCH, SDO data output setup to SCK edge TDOV2SCL Tcy — — ns SP82* TSSL2DOV — — 50 ns 1.5TCY + 40 — — ns SP80* TSCH2DOV, SDO data output valid after TSCL2DOV SCK edge SDO data output valid after SS↓ edge SP83* TSCH2SSH, SS ↑ after SCK edge TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 28-20: I2C™ BUS START/STOP BITS TIMING SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note: Refer to Figure 28-5 for load conditions. DS41364A-page 384 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 28-16: I2C™ BUS START/STOP BITS REQUIREMENTS Param No. Symbol Characteristic SP90* TSU:STA SP91* THD:STA SP92* TSU:STO SP93 THD:STO Stop condition Start condition Typ 4700 — Max. Units — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time Hold time * 100 kHz mode Min. 400 kHz mode 600 — — 100 kHz mode 4000 — — 400 kHz mode 600 — — Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated ns ns These parameters are characterized but not tested. FIGURE 28-21: I2C™ BUS DATA TIMING SP103 SP100 SP102 SP101 SCL SP90 SP106 SP107 SP92 SP91 SDA In SP110 SP109 SP109 SDA Out Note: Refer to Figure 28-5 for load conditions. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 385 PIC16F193X/LF193X TABLE 28-17: I2C™ BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a minimum of 10 MHz SSP module SP101* TLOW Clock low time SSP module SP102* TR SP103* TF SP90* SP91* TSU:STA THD:STA SP106* THD:DAT SP107* TSU:DAT SP92* TSU:STO SP109* TAA SP110* SP111 * Note 1: 2: TBUF CB Conditions 1.5TCY — SDA and SCL rise time 100 kHz mode — 1000 ns 400 kHz mode 0.1CB 300 ns SDA and SCL fall time 100 kHz mode — 250 ns 400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from 10-400 pF Only relevant for Repeated Start condition 20 + 100 kHz mode 4.7 — μs 400 kHz mode 0.6 — μs Start condition hold 100 kHz mode time 400 kHz mode 4.0 — μs 0.6 — μs Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 μs 100 kHz mode 250 — ns 400 kHz mode 100 — ns Start condition setup time Data input setup time Stop condition setup time Output valid from clock Bus free time 100 kHz mode 4.7 — μs 400 kHz mode 0.6 — μs 100 kHz mode — 3500 ns 400 kHz mode — — ns 100 kHz mode 4.7 — μs 400 kHz mode 1.3 — μs — 400 pF Bus capacitive loading CB is specified to be from 10-400 pF After this period the first clock pulse is generated (Note 2) (Note 1) Time the bus must be free before a new transmission can start These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS41364A-page 386 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 28-18: CAP SENSE OSCILLATOR SPECIFICATIONS Param. No. CS01 CS02 Symbol ISRC ISNK Characteristic Current Source Current Sink Min. Typ† Max. Units High — -5.8 — μs Medium — -1.1 — μs Low — -0.2 — μs High — 6.6 — μs Medium — 1.3 — μs Low — 0.24 — μs CS03 VCTH Cap Threshold High — 0.8 — μs CS04 VCTL Cap Threshold Low — 0.4 — μs Conditions * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 28-22: CAP SENSE OSCILLATOR VCTH VCTL ISRC Enabled © 2008 Microchip Technology Inc. ISNK Enabled Preliminary DS41364A-page 387 PIC16F193X/LF193X NOTES: DS41364A-page 388 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 29.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 389 PIC16F193X/LF193X NOTES: DS41364A-page 390 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 28-Lead SPDIP Example PIC16F1936 -I/SP e3 0810017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN PIC16F1937 -I/P e3 0810017 Example 28-Lead QFN 16F1936 -I/ML e3 0810017 XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard PICmicro® device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 391 PIC16F193X/LF193X Package Marking Information (Continued) Example 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC16F1937 -I/ML e3 0810017 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN PIC16F1936 -I/SO e3 0810017 28-Lead SSOP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC16F1936 -I/SS e3 0810017 44-Lead TQFP Example XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN DS41364A-page 392 PIC16F1937 -I/PT e3 0810017 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 30.2 Package Details The following sections give the technical details of the packages. !" 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6&! '! 9'&! 7"') %! 7,8. 7 7 7: ; < & & & = = ##44!! - 1!& & = = "#& "#>#& . - -- ##4>#& . < : 9& - -? & & 9 - 9#4!! < ) ) < 1 = = 69#>#& 9 *9#>#& : *+ 1, - !" !"#$%&"' ()"&'"!&) &#*&&&# +%&,&!& - '! !#.# &"#' #%! &"! ! #%! &"! !! &$#/!# '! #& .0 1,2 1!'! &$& "! **& "&& ! * ,1 © 2008 Microchip Technology Inc. Preliminary DS41364A-page 393 PIC16F193X/LF193X #$ !" 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6&! '! 9'&! 7"') %! 7,8. 7 7 7: ; & & & = = ##44!! = 1!& & = = "#& "#>#& . = ? ##4>#& . < = < : 9& < = & & 9 = 9#4!! < = ) - = ) = - 1 = = 69#>#& 9 *9#>#& : *+ 1, !" !"#$%&"' ()"&'"!&) &#*&&&# +%&,&!& - '! !#.# &"#' #%! &"! ! #%! &"! !! &$#/!# '! #& .0 1,2 1!'! &$& "! **& "&& ! * ,?1 DS41364A-page 394 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X %&'!()$*$%&! +,-../(, !" 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 6&! '! 9'&! 7"') %! 99.. 7 7 7: ; < & : 8& < &# %% , &&4!! - : >#& . .$ !##>#& . : 9& .$ !##9& ?1, .3 ?1, -? - ?1, -? - , &&>#& ) - - - , &&9& 9 , &&& .$ !## @ = !" !"#$%&"' ()"&'"!&) &#*&&&# 4!!*!"&# - '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! = * ,1 © 2008 Microchip Technology Inc. Preliminary DS41364A-page 395 PIC16F193X/LF193X %&'!()$*$%&! +,-../(, !" 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 DS41364A-page 396 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X ##%&'!()*%&! !" 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 6&! '! 9'&! 7"') %! 99.. 7 7 7: ; & : 8& < &# %% , &&4!! - : >#& . .$ !##>#& . : 9& .$ !##9& ?1, .3 <1, ?- ? ?< <1, ?- ? , &&>#& ) - -< , &&9& 9 - , &&& .$ !## @ = !" !"#$%&"' ()"&'"!&) &#*&&&# 4!!*!"&# - '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! ?< = * ,-1 © 2008 Microchip Technology Inc. Preliminary DS41364A-page 397 PIC16F193X/LF193X ##%&'!()*%&! !" 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 DS41364A-page 398 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X 0 01'2-. 0/ !" 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 D N E E1 NOTE 1 1 2 3 b e h α h c φ A2 A L A1 L1 6&! '! 9'&! 7"') %! β 99.. 7 7 7: ; < & : 8& = 1, = ##44!! = = &# %%+ = - : >#& . ##4>#& . 1, : 9& 1, ? -1, ,'%A & B = 3 &9& 9 = 3 && 9 .3 3 & I C = <C 9#4!! < = -- 9#>#& ) - = #%& D C = C #%&1 && ' E C = C !" !"#$%&"' ()"&'"!&) &#*&&&# +%&,&!& - '! !#.# &"#' #%! &"! ! #%! &"! !! &$#''!# '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! * ,1 © 2008 Microchip Technology Inc. Preliminary DS41364A-page 399 PIC16F193X/LF193X ,3 0 .- 0 !" 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 6&! '! 9'&! 7"') %! 99.. 7 7 7: ; < & : 8& = ?1, = ##44!! ? < &# %% = = : >#& . < < ##4>#& . - ? : 9& 3 &9& 9 3 && 9 .3 9#4!! = 3 & C C <C 9#>#& ) = -< !" !"#$%&"' ()"&'"!&) &#*&&&# '! !#.# &"#' #%! &"! ! #%! &"! !! &$#''!# - '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! * ,-1 DS41364A-page 400 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X ##4,%&546*6*6'-4%& !" 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A c φ β L A1 6&! '! 9'&! 7"') %9#! A2 L1 99.. 7 7 7: ; 9#& : 8& = <1, = ##44!! &# %% = 3 &9& 9 ? 3 && 9 .3 3 & : >#& . C 1, -C : 9& 1, ##4>#& . 1, ##49& 1, C 9#4!! = 9#>#& ) - - #%& C C -C #%&1 && ' C C -C !" !"#$%&"' ()"&'"!&) &#*&&&# ,'%!& ! & D!E' - '! !#.# &"#' #%! &"! ! #%! &"! !! &$#''!# '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! * ,?1 © 2008 Microchip Technology Inc. Preliminary DS41364A-page 401 PIC16F193X/LF193X ##4,%&546*6*6'-4%& !" 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 DS41364A-page 402 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X APPENDIX A: DATA SHEET REVISION HISTORY Revision A Original release (12/2008) APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This discusses some of the issues in migrating from other PIC® devices to the PIC16F193X/LF193X family of devices. B.1 PIC16F917 to PIC16F193X/LF193X TABLE B-1: FEATURE COMPARISON Feature PIC16F917 PIC16F1937 Max. Operating Speed 20 MHz 32 MHz 8K 8K Max. Program Memory (Words) Max. SRAM (Bytes) 368 512 10-bit 10-bit Timers (8/16-bit) 2/1 4/1 Oscillator Modes 4 8 A/D Resolution Brown-out Reset Y Y Internal Pull-ups RB<7:0> RB<7:0> Interrupt-on-change RB<7:4> RB<7:0> 2 2 Comparator AUSART/EUSART 1/0 0/1 Extended WDT Y Y Software Control Option of WDT/BOR N Y INTOSC Frequencies 30 kHz 8 MHz 500 kHz 32 MHz Y Y Clock Switching Capacitive Sensing CCP/ECCP Enhanced PIC16 CPU MSSP/SSP LCD © 2008 Microchip Technology Inc. Preliminary N Y 2/0 2/3 N Y 0/1 1/0 Y Y DS41364A-page 403 PIC16F193X/LF193X NOTES: DS41364A-page 404 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X INDEX A A/D Specifications.................................................... 377, 378 Absolute Maximum Ratings .............................................. 355 AC Characteristics Industrial and Extended ............................................ 370 Load Conditions ........................................................ 369 ACKSTAT ......................................................................... 310 ACKSTAT Status Flag ...................................................... 310 ADC .................................................................................. 131 Acquisition Requirements ......................................... 140 Associated registers.................................................. 142 Block Diagram........................................................... 131 Calculating Acquisition Time..................................... 140 Channel Selection..................................................... 132 Configuration............................................................. 132 Configuring Interrupt ................................................. 136 Conversion Clock...................................................... 132 Conversion Procedure .............................................. 136 Internal Sampling Switch (RSS) Impedance.............. 140 Interrupts................................................................... 134 Operation .................................................................. 135 Operation During Sleep ............................................ 135 Port Configuration ..................................................... 132 Reference Voltage (VREF)......................................... 132 Source Impedance.................................................... 140 Special Event Trigger................................................ 135 Starting an A/D Conversion ...................................... 134 ADCON0 Register....................................................... 36, 137 ADCON1 Register....................................................... 36, 138 ADDFSR ........................................................................... 341 ADDWFC .......................................................................... 341 ADRESH Register............................................................... 36 ADRESH Register (ADFM = 0) ......................................... 138 ADRESH Register (ADFM = 1) ......................................... 139 ADRESL Register (ADFM = 0).......................................... 139 ADRESL Register (ADFM = 1).......................................... 139 Alternate Pin Function......................................................... 84 Analog-to-Digital Converter. See ADC ANSELA Register ............................................................... 86 ANSELB Register ............................................................... 91 ANSELD Register ............................................................... 97 ANSELE Register ............................................................. 101 APFCON Register............................................................... 84 Assembler MPASM Assembler................................................... 352 B BAUDCON Register.......................................................... 224 BF ............................................................................. 310, 312 BF Status Flag .......................................................... 310, 312 Block Diagram Capacitive Sensing ................................................... 177 Block Diagrams (CCP) Capture Mode Operation ............................... 187 ADC .......................................................................... 131 ADC Transfer Function ............................................. 141 Analog Input Model ........................................... 141, 147 CCP PWM................................................................. 191 Clock Source............................................................. 107 Comparator ............................................................... 144 Compare ................................................................... 189 Crystal Operation ...................................................... 110 © 2008 Microchip Technology Inc. Digital-to-Analog Converter (DAC) ........................... 152 EUSART Receive ..................................................... 214 EUSART Transmit .................................................... 213 External RC Mode .................................................... 111 Fail-Safe Clock Monitor (FSCM)............................... 119 Generic I/O Port.......................................................... 83 Interrupt Logic............................................................. 69 LCD Bias Voltage Generation .................................. 249 LCD Clock Generation.............................................. 248 MCLR Circuit .............................................................. 59 On-Chip Reset Circuit................................................. 57 Peripheral Interrupt Logic ........................................... 70 PIC16F193X/LF193X ................................................. 13 PWM (Enhanced) ..................................................... 195 Resonator Operation ................................................ 110 Timer0 ...................................................................... 157 Timer1 ...................................................................... 161 Timer1 Gate.............................................. 166, 167, 168 Timer2/4/6 ................................................................ 173 Voltage Reference.................................................... 155 Voltage Reference Output Buffer Example .............. 155 BORCON Register.............................................................. 63 BRA .................................................................................. 342 Break Character (12-bit) Transmit and Receive ............... 233 Brown-out Reset (BOR)...................................................... 62 Specifications ........................................................... 375 Timing and Characteristics ....................................... 374 C C Compilers MPLAB C18.............................................................. 352 MPLAB C30.............................................................. 352 CALL................................................................................. 343 CALLW ............................................................................. 343 Capacitive Sensing ........................................................... 177 Associated registers w/ Capacitive Sensing............. 181 Specifications ........................................................... 387 Capture Module. See Enhanced Capture/Compare/ PWM(ECCP) Capture/Compare/PWM ................................................... 183 Capture/Compare/PWM (CCP) ........................................ 185 Associated Registers w/ Capture ............................. 188 Associated Registers w/ Compare ........................... 190 Associated Registers w/ PWM ................................. 211 Capture Mode........................................................... 187 CCPx Pin Configuration............................................ 187 Clock Selection......................................................... 185 Compare Mode......................................................... 189 CCPx Pin Configuration.................................... 189 Software Interrupt Mode ........................... 187, 189 Special Event Trigger ....................................... 189 Timer1 Mode Selection............................. 187, 189 Prescaler .................................................................. 187 PWM Mode............................................................... 191 Duty Cycle ........................................................ 192 Effects of Reset ................................................ 194 Example PWM Frequencies and Resolutions, 20 MHZ ................................ 193 Example PWM Frequencies and Resolutions, 32 MHZ ................................ 193 Example PWM Frequencies and Resolutions, 8 MHz .................................. 193 Operation in Sleep Mode.................................. 194 Resolution ........................................................ 193 Preliminary DS41364A-page 405 PIC16F193X/LF193X Setup for Operation........................................... 194 System Clock Frequency Changes................... 194 PWM Period .............................................................. 192 Setup for PWM Operation ......................................... 194 CCP1CON Register ...................................................... 40, 41 CCPR1H Register ......................................................... 40, 41 CCPR1L Register.......................................................... 40, 41 CCPTMRS0 Register ........................................................ 185 CCPTMRS1 Register ........................................................ 186 CCPxAS Register.............................................................. 204 CCPxCON (ECCPx) Register ........................................... 184 Clock Accuracy with Asynchronous Operation ................. 222 Clock Sources External Modes ......................................................... 109 EC ..................................................................... 109 HS ..................................................................... 110 LP...................................................................... 110 OST................................................................... 109 RC..................................................................... 111 XT ..................................................................... 110 Internal Modes .......................................................... 111 Frequency Selection ......................................... 115 HFINTOSC........................................................ 112 Internal Oscillator Clock Switch Timing............. 115 INTOSC ............................................................ 111 INTOSCIO......................................................... 111 LFINTOSC ........................................................ 112 MFINTOSC ....................................................... 112 Clock Switching................................................................. 117 CMOUT Register............................................................... 149 CMxCON0 Register .......................................................... 148 CMxCON1 Register .......................................................... 149 Code Examples A/D Conversion ......................................................... 136 Changing Between Capture Prescalers .................... 187 Initializing PORTA ....................................................... 85 Initializing PORTB ....................................................... 89 Initializing PORTC....................................................... 93 Initializing PORTD....................................................... 96 Initializing PORTE ..................................................... 101 Write Verify ............................................................... 332 Writing to Flash Program Memory ............................ 330 Comparator Associated Registers ................................................ 150 Operation .................................................................. 143 Comparator Module .......................................................... 143 Cx Output State Versus Input Conditions ................. 145 Comparator Specifications ................................................ 380 Comparator Voltage Reference (CVREF) Associated Registers ................................................ 156 Comparators C2OUT as T1 Gate ................................................... 163 Compare Module. See Enhanced Capture/ Compare/PWM (ECCP) CONFIG1 Register............................................................ 126 CONFIG2 Register............................................................ 128 Core Registers .................................................................... 49 CPSCON0 Register .......................................................... 180 CPSCON1 Register .......................................................... 181 Customer Change Notification Service ............................. 413 Customer Notification Service........................................... 413 Customer Support ............................................................. 413 D DACCON0 (Digital-to-Analog Converter Control 0) Register.. 153 DS41364A-page 406 DACCON1 (Digital-to-Analog Converter Control 1) Register .................................................................... 153 Data EEPROM Memory.................................................... 321 Associated Registers ................................................ 332 Code Protection ........................................................ 332 Reading .................................................................... 325 Writing ...................................................................... 325 Data Memory ...................................................................... 24 DC and AC Characteristics............................................... 389 DC Characteristics Extended and Industrial ............................................ 365 Industrial and Extended ............................................ 358 Development Support ....................................................... 351 Device Configuration ........................................................ 125 Code Protection ........................................................ 129 Configuration Word................................................... 125 User ID ..................................................................... 129 Device Overview................................................................. 13 Digital-to-Analog Converter (DAC) ................................... 151 Associated Registers ................................................ 154 Effects of a Reset ..................................................... 151 Operation During Sleep ............................................ 151 Specifications ........................................................... 380 E ECCP/CCP. See Enhanced Capture/Compare/PWM EEADR Registers ............................................................. 321 EEADRH Registers........................................................... 321 EEADRL Register ............................................................. 322 EEADRL Registers ........................................................... 321 EECON1 Register..................................................... 321, 323 EECON2 Register..................................................... 321, 324 EEDATH Register............................................................. 322 EEDATL Register ............................................................. 322 EEPROM Data Memory Avoiding Spurious Write ........................................... 332 Write Verify ............................................................... 332 Effects of Reset PWM mode ............................................................... 194 Electrical Specifications .................................................... 355 Enhanced Capture/Compare/PWM Timer Resources ...................................................... 184 Enhanced Capture/Compare/PWM (ECCP)..................... 184 Enhanced PWM Mode.............................................. 195 Auto-Restart ..................................................... 205 Auto-shutdown.................................................. 203 Direction Change in Full-Bridge Output Mode.. 201 Full-Bridge Application...................................... 199 Full-Bridge Mode .............................................. 199 Half-Bridge Application ..................................... 198 Half-Bridge Application Examples .................... 206 Half-Bridge Mode.............................................. 198 Output Relationships (Active-High and Active-Low)............................................... 196 Output Relationships Diagram.......................... 197 Programmable Dead Band Delay..................... 206 Shoot-through Current ...................................... 206 Start-up Considerations .................................... 203 Specifications ........................................................... 377 Enhanced Mid-range CPU.................................................. 14 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .............................. 213 Errata .................................................................................. 11 EUSART ........................................................................... 213 Associated Registers Baud Rate Generator ....................................... 226 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X Asynchronous Mode ................................................. 215 12-bit Break Transmit and Receive .................. 233 Associated Registers Receive..................................................... 221 Transmit.................................................... 217 Auto-Wake-up on Break ................................... 231 Baud Rate Generator (BRG) ............................ 225 Clock Accuracy ................................................. 222 Receiver............................................................ 218 Setting up 9-bit Mode with Address Detect....... 220 Transmitter........................................................ 215 Baud Rate Generator (BRG) Auto Baud Rate Detect ..................................... 230 Baud Rate Error, Calculating ............................ 225 Baud Rates, Asynchronous Modes .................. 227 Formulas ........................................................... 226 High Baud Rate Select (BRGH Bit) .................. 225 Synchronous Master Mode ............................... 234, 238 Associated Registers Receive..................................................... 237 Transmit.................................................... 235 Reception.......................................................... 236 Transmission .................................................... 234 Synchronous Slave Mode Associated Registers Receive..................................................... 239 Transmit.................................................... 238 Reception.......................................................... 239 Transmission .................................................... 238 Extended Instruction Set ADDFSR ................................................................... 341 F Fail-Safe Clock Monitor..................................................... 119 Fail-Safe Condition Clearing ..................................... 119 Fail-Safe Detection ................................................... 119 Fail-Safe Operation................................................... 119 Reset or Wake-up from Sleep................................... 119 Firmware Instructions........................................................ 337 Fixed Voltage Reference (FVR) Specifications............................................................ 380 Flash Program Memory .................................................... 321 Erasing...................................................................... 328 Writing....................................................................... 328 FSR Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 48 FVRCON (Fixed Voltage Reference Control) Register ..... 156 I I2C Mode (MSSP) Acknowledge Sequence Timing................................ 314 Bus Collision During a Repeated Start Condition ................... 318 During a Stop Condition.................................... 319 Effects of a Reset...................................................... 315 I2C Clock Rate w/BRG.............................................. 320 Master Mode Operation .......................................................... 306 Reception.......................................................... 312 Start Condition Timing .............................. 308, 309 Transmission .................................................... 310 Multi-Master Communication, Bus Collision and Arbitration .................................................. 315 Multi-Master Mode .................................................... 315 Read/Write Bit Information (R/W Bit) ........................ 291 Slave Mode Transmission .................................................... 296 © 2008 Microchip Technology Inc. Sleep Operation........................................................ 315 Stop Condition Timing .............................................. 314 INDF Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 48 Indirect Addressing, INDF and FSR Registers ................... 53 Instruction Format............................................................. 338 Instruction Set................................................................... 337 ADDLW..................................................................... 341 ADDWF .................................................................... 341 ADDWFC.................................................................. 341 ANDLW..................................................................... 341 ANDWF .................................................................... 341 BRA .......................................................................... 342 CALL......................................................................... 343 CALLW ..................................................................... 343 LSLF ......................................................................... 345 LSRF ........................................................................ 345 MOVF ....................................................................... 345 MOVIW ..................................................................... 346 MOVLB ..................................................................... 346 MOVWI ..................................................................... 347 OPTION.................................................................... 347 RESET...................................................................... 347 SUBWFB .................................................................. 349 TRIS ......................................................................... 350 BCF .......................................................................... 342 BSF........................................................................... 342 BTFSC...................................................................... 342 BTFSS ...................................................................... 342 CALL......................................................................... 343 CLRF ........................................................................ 343 CLRW ....................................................................... 343 CLRWDT .................................................................. 343 COMF ....................................................................... 343 DECF........................................................................ 343 DECFSZ ................................................................... 344 GOTO ....................................................................... 344 INCF ......................................................................... 344 INCFSZ..................................................................... 344 IORLW ...................................................................... 344 IORWF...................................................................... 344 MOVLW .................................................................... 346 MOVWF.................................................................... 346 NOP.......................................................................... 347 RETFIE..................................................................... 348 RETLW ..................................................................... 348 RETURN................................................................... 348 RLF........................................................................... 348 RRF .......................................................................... 349 SLEEP ...................................................................... 349 SUBLW..................................................................... 349 SUBWF..................................................................... 349 SWAPF..................................................................... 350 XORLW .................................................................... 350 XORWF .................................................................... 350 INTCON Register................................................................ 73 Internal Oscillator Block INTOSC Specifications ................................................... 371 Internal Sampling Switch (RSS) Impedance ..................... 140 Internet Address ............................................................... 413 Interrupt-On-Change......................................................... 103 Associated Registers................................................ 105 Interrupts ............................................................................ 69 ADC .......................................................................... 136 Associated registers w/ Interrupts .............................. 80 Preliminary DS41364A-page 407 PIC16F193X/LF193X TMR1 ........................................................................ 165 INTOSC Specifications ..................................................... 371 IOCBF Register................................................................. 104 IOCBN Register ................................................................ 104 IOCBP Register................................................................. 104 L LATA Register............................................................... 85, 93 LATB Register..................................................................... 90 LATD Register..................................................................... 96 LATE Register..................................................................... 99 LCD Associated Registers ................................................ 272 Bias Voltage Generation ................................... 249, 250 Clock Source Selection ............................................. 248 Configuring the Module ............................................. 271 Disabling the Module ................................................ 271 Frame Frequency...................................................... 254 Interrupts ................................................................... 267 LCDCON Register .................................................... 241 LCDPS Register........................................................ 241 Multiplex Types ......................................................... 254 Operation During Sleep ............................................ 269 Pixel Control.............................................................. 254 Prescaler ................................................................... 248 Segment Enables...................................................... 254 Waveform Generation ............................................... 256 LCDCON Register..................................................... 241, 243 LCDCST Register ............................................................. 246 LCDDATAx Registers ............................................... 247, 252 LCDPS Register........................................................ 241, 244 LP Bits....................................................................... 248 LCDREF Register ............................................................. 245 LCDRL Register ................................................................ 252 LCDSEn Registers ............................................................ 247 Liquid Crystal Display (LCD) Driver .................................. 241 Load Conditions ................................................................ 369 LSLF.................................................................................. 345 LSRF ................................................................................. 345 M Master Synchronous Serial Port. See MSSP MCLR .................................................................................. 59 Internal ........................................................................ 59 Memory Organization.......................................................... 21 Data ............................................................................ 24 Program ...................................................................... 21 Microchip Internet Web Site .............................................. 413 Migrating from other PIC Microcontroller Devices............. 403 MOVIW.............................................................................. 346 MOVLB.............................................................................. 346 MOVWI.............................................................................. 347 MPLAB ASM30 Assembler, Linker, Librarian ................... 352 MPLAB ICD 2 In-Circuit Debugger.................................... 353 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................................... 353 MPLAB Integrated Development Environment Software .. 351 MPLAB PM3 Device Programmer..................................... 353 MPLAB REAL ICE In-Circuit Emulator System................. 353 MPLINK Object Linker/MPLIB Object Librarian ................ 352 MSSP ................................................................................ 273 SSPBUF Register ..................................................... 283 SSPSR Register ....................................................... 283 DS41364A-page 408 O OPCODE Field Descriptions............................................. 337 OPTION ............................................................................ 347 OPTION Register........................................................ 51, 159 OSCCON Register............................................................ 108 Oscillator Associated Registers ................................................ 120 Oscillator Module .............................................................. 107 EC............................................................................. 107 HFINTOSC ............................................................... 107 HS............................................................................. 107 INTOSC .................................................................... 107 LFINTOSC ................................................................ 107 LP ............................................................................. 107 MFINTOSC ............................................................... 107 RC ............................................................................ 107 XT ............................................................................. 107 Oscillator Parameters ....................................................... 371 Oscillator Specifications.................................................... 370 Oscillator Start-up Timer (OST) Specifications ........................................................... 375 Oscillator Switching Fail-Safe Clock Monitor ............................................ 119 Two-Speed Clock Start-up........................................ 117 OSCSTAT Register .......................................................... 113 OSCTUNE Register.......................................................... 114 P P1A/P1B/P1C/P1D.See Enhanced Capture/ Compare/PWM (ECCP)............................................ 195 Packaging ......................................................................... 391 Marking ............................................................. 391, 392 PDIP Details ............................................................. 393 PCL and PCLATH............................................................... 52 PCL Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 48 PCLATH Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 48 PCON Register ............................................................. 36, 65 PICSTART Plus Development Programmer..................... 354 PIE1 Register................................................................ 36, 74 PIE2 Register................................................................ 36, 75 PIE3 Register...................................................................... 76 Pin Diagram PIC16F1933/1936/1938, PICLF1933/1936/1938, 28-pin PDIP/SOIC/SSOP ..................................... 3 PIC16F1933/1936/1938, PICLF1933/1936/1938, 28-pin QFN ........................................................... 4 PICF1934/1937/1939, PICLF1934/1937/1939, 44-pin QFN ........................................................... 7 PICF1934/1937/1939, PICLF1934/1937/1939, 44-pin TQFP ......................................................... 8 PICF1934/1937/1939,PICLF1934/1937/1939, 40-pin PDIP .......................................................... 6 Pinout Descriptions PIC16F193X/PIC16LF193X........................................ 15 PIR1 Register ............................................................... 35, 77 PIR2 Register ............................................................... 35, 78 PIR3 Register ..................................................................... 79 PORTA ............................................................................... 85 ANSELA Register ....................................................... 86 Associated Registers .................................................. 88 PORTA Register ................................................... 35, 37 Specifications ........................................................... 373 PORTA Register ................................................................. 85 PORTB ............................................................................... 89 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X Additional Pin Functions Weak Pull-up ...................................................... 89 ANSELB Register ....................................................... 91 Associated Registers .................................................. 92 Interrupt-on-Change.................................................... 89 P1B/P1C/P1D.See Enhanced Capture/ Compare/PWM+ (ECCP+).................................. 89 Pin Descriptions and Diagrams................................... 92 PORTB Register ................................................... 35, 37 PORTB Register ................................................................. 90 PORTC ............................................................................... 93 Associated Registers .................................................. 95 P1A.See Enhanced Capture/Compare/ PWM+ (ECCP+) ................................................. 93 Pin Descriptions and Diagrams................................... 95 PORTC Register ................................................... 35, 37 Specifications............................................................ 373 PORTC Register ................................................................. 93 PORTD ............................................................................... 96 Additional Pin Functions ANSELD Register ............................................... 97 Associated Registers .................................................. 98 P1B/P1C/P1D.See Enhanced Capture/ Compare/PWM+ (ECCP+).................................. 96 Pin Descriptions and Diagrams................................... 98 PORTD Register ................................................... 35, 37 PORTD Register ................................................................. 96 PORTE................................................................................ 99 ANSELE Register ..................................................... 101 Associated Registers ................................................ 102 Pin Descriptions and Diagrams................................. 102 PORTE Register ................................................... 35, 37 PORTE Register ................................................................. 99 Power-Down Mode (Sleep) ............................................... 333 Associated Registers ................................................ 334 Power-on Reset .................................................................. 59 Power-up Time-out Sequence ............................................ 64 Power-up Timer (PWRT) .................................................... 59 Specifications............................................................ 375 PR2 Register................................................................. 35, 43 Precision Internal Oscillator Parameters........................... 371 Program Memory ................................................................ 21 Map and Stack (PIC16F1933/LF1933, PIC16F1934/LF1934) ......................................... 22 Map and Stack (PIC16F1936/LF1936, PIC16F1937/LF1937) ......................................... 22 Map and Stack (PIC16F1938/LF1938, PIC16F1939/LF1939) ......................................... 23 Programming, Device Instructions .................................... 337 PSTRxCON Register ........................................................ 208 Pulse Steering................................................................... 208 PWM (ECCP Module) Pulse Steering........................................................... 208 Steering Synchronization .......................................... 210 PWM Mode. See Enhanced Capture/Compare/PWM ...... 195 PWMxCON Register ......................................................... 207 R RCREG ............................................................................. 220 RCREG Register................................................................. 38 RCSTA Register ......................................................... 38, 223 Reader Response ............................................................. 414 Read-Modify-Write Operations ......................................... 337 Register RCREG Register....................................................... 230 Registers © 2008 Microchip Technology Inc. Preliminary ADCON0 (ADC Control 0) ........................................ 137 ADCON1 (ADC Control 1) ........................................ 138 ADRESH (ADC Result High) with ADFM = 0) .......... 138 ADRESH (ADC Result High) with ADFM = 1) .......... 139 ADRESL (ADC Result Low) with ADFM = 0)............ 139 ADRESL (ADC Result Low) with ADFM = 1)............ 139 ANSELA (PORTA Analog Select) .............................. 86 ANSELB (PORTB Analog Select) .............................. 91 ANSELD (PORTD Analog Select) .............................. 97 ANSELE (PORTE Analog Select) ............................ 101 APFCON (Alternate Pin Function Control) ................. 84 BAUDCON (Baud Rate Control)............................... 224 BORCON Brown-out Reset Control) .......................... 63 CCPTMRS0 (CCP Timers Control 0) ....................... 185 CCPTMRS1 (CCP Timers Control 1) ....................... 186 CCPxAS (CCPx Auto-Shutdown Control) ................ 204 CCPxCON (ECCPx Control) .................................... 184 CMOUT (Comparator Output) .................................. 149 CMxCON0 (Cx Control) ............................................ 148 CMxCON1 (Cx Control 1)......................................... 149 Configuration Word 1................................................ 126 Configuration Word 2................................................ 128 CPSCON0 (Capacitive Sensing Control Register 0) 180 CPSCON1 (Capacitive Sensing Control Register 1) 181 DACCON0 ................................................................ 153 DACCON1 ................................................................ 153 EEADRL (EEPROM Address) .................................. 322 EECON1 (EEPROM Control 1) ................................ 323 EECON2 (EEPROM Control 2) ................................ 324 EEDATH (EEPROM Data) ....................................... 322 EEDATL (EEPROM Data) ........................................ 322 FVRCON .................................................................. 156 INTCON (Interrupt Control) ........................................ 73 IOCBF (Interrupt-on-Change Flag)........................... 104 IOCBN (Interrupt-on-Change Negative Edge).......... 104 IOCBP (Interrupt-on-Change Positive Edge)............ 104 LATA (Data Latch PORTA) ........................................ 85 LATB (Data Latch PORTB) ........................................ 90 LATC (Data Latch PORTC) ........................................ 93 LATD (Data Latch PORTD) ........................................ 96 LATE (Data Latch PORTE) ........................................ 99 LCDCON (LCD Control) ........................................... 243 LCDCST (LCD Contrast Control) ............................. 246 LCDDATAx (LCD Data) .................................... 247, 252 LCDPS (LCD Phase)................................................ 244 LCDREF (LCD Reference Voltage Control) ............. 245 LCDRL (LCD Reference Voltage Control)................ 252 LCDSEn (LCD Segment Enable) ............................. 247 OPTION_REG (OPTION)................................... 51, 159 OSCCON (Oscillator Control)................................... 108 OSCSTAT (Oscillator Status) ................................... 113 OSCTUNE (Oscillator Tuning).................................. 114 PCON (Power Control Register)................................. 65 PCON (Power Control) ............................................... 65 PIE1 (Peripheral Interrupt Enable 1) .......................... 74 PIE2 (Peripheral Interrupt Enable 2) .......................... 75 PIE3 (Peripheral Interrupt Enable 3) .......................... 76 PIR1 (Peripheral Interrupt Register 1) ........................ 77 PIR2 (Peripheral Interrupt Request 2) ........................ 78 PIR3 (Peripheral Interrupt Request 3) ........................ 79 PORTA ....................................................................... 85 PORTB ....................................................................... 90 PORTC ....................................................................... 93 PORTD ....................................................................... 96 PORTE ....................................................................... 99 DS41364A-page 409 PIC16F193X/LF193X PSTRxCON (Pulse Steering Control) ....................... 208 PWMxCON (Enhanced PWM Control) ..................... 207 RCSTA (Receive Status and Control)....................... 223 Special Function, Summary ........................................ 35 SRCON0 (SR Latch Control 0) ................................. 122 SRCON1 (SR Latch Control 1) ................................. 123 SSPADD (MSSP Address and Baud Rate, I2C Mode).......................................................... 280 SSPCON1 (MSSP Control 1).................................... 277 SSPCON2 (SSP Control 2)....................................... 278 SSPCON3 (SSP Control 3)....................................... 279 SSPMSK (SSP Mask) ............................................... 280 SSPSTAT (SSP Status) ............................................ 276 STATUS ...................................................................... 50 T1CON (Timer1 Control)........................................... 169 T1GCON (Timer1 Gate Control) ............................... 170 TRISA (Tri-State PORTA) ........................................... 86 TRISB (Tri-State PORTB) ........................................... 91 TRISC (Tri-State PORTC) .......................................... 94 TRISD (Tri-State PORTD) .......................................... 97 TRISE (Tri-State PORTE) ......................................... 101 TxCON ...................................................................... 175 TXSTA (Transmit Status and Control) ...................... 222 WDTCON (Watchdog Timer Control).......................... 61 WPUB (Weak Pull-up PORTB) ................................... 90 RESET .............................................................................. 347 Reset................................................................................... 57 Reset Instruction ................................................................. 64 Resets ................................................................................. 57 Associated Registers .................................................. 68 Revision History ................................................................ 403 S SCK................................................................................... 281 SDI .................................................................................... 281 SDO .................................................................................. 281 Serial Clock, SCK.............................................................. 281 Serial Data In (SDI) ........................................................... 281 Serial Data Out (SDO) ...................................................... 281 Shoot-through Current ...................................................... 206 Slave Select (SS) .............................................................. 281 Software Simulator (MPLAB SIM)..................................... 352 SPBRG.............................................................................. 225 SPBRG Register ........................................................... 37, 38 SPBRGH ........................................................................... 225 Special Event Trigger........................................................ 135 Special Function Registers (SFRs) ..................................... 35 SPI Mode (MSSP) Associated Registers ................................................ 286 Serial Clock ............................................................... 281 Serial Data In ............................................................ 281 Serial Data Out ......................................................... 281 Slave Select .............................................................. 281 SPI Clock .................................................................. 283 Typical Connection ................................................... 282 SR Latch ........................................................................... 121 SRCON0 Register............................................................. 122 SRCON1 Register............................................................. 123 SS ..................................................................................... 281 SSPADD Register ....................................................... 39, 280 SSPBUF Register ............................................................... 39 SSPCON 1 Register.......................................................... 277 SSPCON Register............................................................... 39 SSPCON2 Register........................................................... 278 SSPCON3 Register........................................................... 279 SSPMSK Register............................................................. 280 DS41364A-page 410 SSPOV ............................................................................. 312 SSPOV Status Flag .......................................................... 312 SSPSTAT Register ..................................................... 39, 276 R/W Bit ..................................................................... 291 Stack................................................................................... 52 Accessing ................................................................... 53 Reset .......................................................................... 53 Stack Overflow/Underflow .................................................. 64 STATUS Register ............................................................... 50 SUBWFB .......................................................................... 349 T T1CON Register ......................................................... 35, 169 T1GCON Register ............................................................ 170 T2CON Register ........................................................... 35, 43 Thermal Considerations.................................................... 368 Timer0............................................................................... 157 Associated Registers ................................................ 159 Operation .................................................................. 157 Specifications ........................................................... 376 Timer1............................................................................... 161 Associated registers ................................................. 171 Asynchronous Counter Mode ................................... 163 Reading and Writing ......................................... 163 Clock Source Selection............................................. 162 Interrupt .................................................................... 165 Operation .................................................................. 162 Operation During Sleep ............................................ 165 Oscillator................................................................... 163 Prescaler .................................................................. 163 Specifications ........................................................... 376 Timer1 Gate Selecting Source .............................................. 163 TMR1H Register ....................................................... 161 TMR1L Register........................................................ 161 Timer2 Associated registers ................................................. 176 Timer2/4/6......................................................................... 173 Associated registers ................................................. 176 Timers Timer1 T1CON ............................................................. 169 T1GCON........................................................... 170 Timer2/4/6 TxCON.............................................................. 175 Timing Diagrams A/D Conversion......................................................... 378 A/D Conversion (Sleep Mode) .................................. 379 Acknowledge Sequence ........................................... 314 Asynchronous Reception.......................................... 220 Asynchronous Transmission..................................... 216 Asynchronous Transmission (Back to Back) ............ 216 Auto Wake-up Bit (WUE) During Normal Operation . 232 Auto Wake-up Bit (WUE) During Sleep .................... 232 Automatic Baud Rate Calibration.............................. 230 Baud Rate Generator with Clock Arbitration............. 307 BRG Reset Due to SDA Arbitration During Start Condition.................................................. 317 Brown-out Reset (BOR)............................................ 374 Brown-out Reset Situations ........................................ 62 Bus Collision During a Repeated Start Condition (Case 1)........................................................... 318 Bus Collision During a Repeated Start Condition (Case 2)........................................................... 318 Bus Collision During a Start Condition (SCL = 0) ..... 317 Bus Collision During a Stop Condition (Case 1) ....... 319 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X Bus Collision During a Stop Condition (Case 2) ....... 319 Bus Collision During Start Condition (SDA only) ...... 316 Bus Collision for Transmit and Acknowledge............ 315 CLKOUT and I/O....................................................... 372 Clock Synchronization .............................................. 304 Clock Timing ............................................................. 370 Comparator Output ................................................... 143 Enhanced Capture/Compare/PWM (ECCP) ............. 377 Fail-Safe Clock Monitor (FSCM) ............................... 120 First Start Bit Timing ................................................. 308 Full-Bridge PWM Output ........................................... 200 Half-Bridge PWM Output .................................. 198, 206 I2C Bus Data ............................................................. 385 I2C Bus Start/Stop Bits.............................................. 384 I2C Master Mode (7 or 10-Bit Transmission) ............ 311 I2C Master Mode (7-Bit Reception)........................... 313 I2C Stop Condition Receive or Transmit Mode ......... 314 INT Pin Interrupt.......................................................... 71 Internal Oscillator Switch Timing............................... 116 LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 268 LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 270 PWM Auto-shutdown ................................................ 205 Firmware Restart .............................................. 205 PWM Direction Change ............................................ 201 PWM Direction Change at Near 100% Duty Cycle ... 202 PWM Output (Active-High)........................................ 196 PWM Output (Active-Low) ........................................ 197 Repeat Start Condition.............................................. 309 Reset, WDT, OST and Power-up Timer ................... 373 Send Break Character Sequence ............................. 233 SPI Master Mode (CKE = 1, SMP = 1) ..................... 382 SPI Mode (Master Mode).......................................... 283 SPI Slave Mode (CKE = 0) ....................................... 383 SPI Slave Mode (CKE = 1) ....................................... 383 Synchronous Reception (Master Mode, SREN) ....... 237 Synchronous Transmission....................................... 235 Synchronous Transmission (Through TXEN) ........... 235 Time-out Sequence Case 1 ................................................................ 66 Case 2 ................................................................ 67 Case 3 ................................................................ 67 Timer0 and Timer1 External Clock ........................... 376 Timer1 Incrementing Edge........................................ 165 Two Speed Start-up .................................................. 118 Type-A in 1/2 Mux, 1/2 Bias Drive ............................ 257 Type-A in 1/2 Mux, 1/3 Bias Drive ............................ 259 Type-A in 1/3 Mux, 1/2 Bias Drive ............................ 261 Type-A in 1/3 Mux, 1/3 Bias Drive ............................ 263 Type-A in 1/4 Mux, 1/3 Bias Drive ............................ 265 Type-A/Type-B in Static Drive................................... 256 Type-B in 1/2 Mux, 1/2 Bias Drive ............................ 258 Type-B in 1/2 Mux, 1/3 Bias Drive ............................ 260 Type-B in 1/3 Mux, 1/2 Bias Drive ............................ 262 Type-B in 1/3 Mux, 1/3 Bias Drive ............................ 264 Type-B in 1/4 Mux, 1/3 Bias Drive ............................ 266 USART Synchronous Receive (Master/Slave) ......... 381 USART Synchronous Transmission (Master/Slave) . 381 Wake-up from Interrupt ............................................. 334 Timing Diagrams and Specifications PLL Clock.................................................................. 371 Timing Parameter Symbology........................................... 369 Timing Requirements I2C Bus Data ............................................................. 386 I2C Bus Start/Stop Bits ............................................. 385 SPI Mode .................................................................. 384 © 2008 Microchip Technology Inc. TMR0 Register.................................................................... 35 TMR1H Register ................................................................. 35 TMR1L Register.................................................................. 35 TMR2 Register.............................................................. 35, 43 TRIS ................................................................................. 350 TRISA Register............................................................. 36, 86 TRISB ................................................................................. 89 TRISB Register............................................................. 36, 91 TRISC ................................................................................. 93 TRISC Register............................................................. 36, 94 TRISD ................................................................................. 96 TRISD Register............................................................. 36, 97 TRISE ................................................................................. 99 TRISE Register........................................................... 36, 101 Two-Speed Clock Start-up Mode...................................... 117 TXCON (Timer2/4/6) Register .......................................... 175 TxCON Register ............................................................... 211 TXREG ............................................................................. 215 TXREG Register ................................................................. 38 TXSTA Register.......................................................... 38, 222 BRGH Bit .................................................................. 225 U USART Synchronous Master Mode Requirements, Synchronous Receive .............. 381 Requirements, Synchronous Transmission...... 381 Timing Diagram, Synchronous Receive ........... 381 Timing Diagram, Synchronous Transmission... 381 V VREF. SEE ADC Reference Voltage W Wake-up on Break ............................................................ 231 Wake-up Using Interrupts ................................................. 334 Watchdog Timer (WDT)...................................................... 59 Clock Source .............................................................. 59 Modes......................................................................... 60 Period ......................................................................... 59 Specifications ........................................................... 375 WCOL ....................................................... 307, 310, 312, 314 WCOL Status Flag.................................... 307, 310, 312, 314 WDTCON Register ............................................................. 61 WPUB Register................................................................... 90 WWW Address ................................................................. 413 WWW, On-Line Support ..................................................... 11 Preliminary DS41364A-page 411 PIC16F193X/LF193X NOTES: DS41364A-page 412 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2008 Microchip Technology Inc. Preliminary DS41364A-page 413 PIC16F193X/LF193X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16F193X/LF193X N Literature Number: DS41364A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41364A-page 414 Preliminary © 2008 Microchip Technology Inc. PIC16F193X/LF193X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device: PIC16F1933, PIC16LF1933, PIC16F1933T, PIC16LF1933T(1) PIC16F1934, PIC16LF1934, PIC16F1934T, PIC16LF1934T(1) PIC16F1936, PIC16LF1936, PIC16F1936T, PIC16LF1936T(1) PIC16F1937, PIC16LF1937, PIC16F1937T, PIC16LF1937T(1) PIC16F1938, PIC16LF1938, PIC16F1938T, PIC16LF1938T(1) PIC16F1939, PIC16LF1939, PIC16F1939T, PIC16LF1939T(1) Temperature Range: I E = = -40°C to +85°C -40°C to +125°C Package: ML P PT SO SP SS = = = = = = Micro Lead Frame (QFN) Plastic DIP TQFP (Thin Quad Flatpack) SOIC Skinny Plastic DIP SSOP Pattern: c) PIC16LF1937 - I/P = Industrial temp., Plastic DIP package, low-voltage VDD limits. PIC16F1934 - I/PT = Industrial temp., TQFP package, standard VDD limits. PIC16F1933 - E/ML = Extended temp., QFN package, standard VDD limits. Note 1: 2: F = Standard Voltage Range LF = Low Voltage Range T = In tape and reel for QFN, TQFP, SOIC and SSOP packages only. 3-Digit Pattern Code for QTP (blank otherwise) © 2008 Microchip Technology Inc. Preliminary DS41364A-page 415 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 01/02/08 DS41364A-page 416 Preliminary © 2008 Microchip Technology Inc.