JDSU EDR515BRSC-DM

COMMUNICATIONS COMPONENTS
Access PIN-TIA Receivers for 155 Mb/s and 622 Mb/s
EDR 51xx Series
Key Features
• Electro-optical
- InGaAs PIN photodiode with silicon transimpedance amplifier
- Operate on single supply
EDR 512x (5 V)
EDR 515x (3.3 V or 5 V)
- Three standard pin-out configurations
EDR 51xB - single-ended output
EDR 51xC - single-ended output with photodiode access
EDR 51xD - differential output
- Cost effective in receiver designs where sensitivity is
limited by the post-amplifier
- Shielded pre-amplifier makes it immune to crosstalk
with transmitter or to other EMI
- -40 to +85°C operating range
Applications
• Single mode 155 Mb/s (EDR 512x) and
622 Mb/s (EDR 515x) ATM receivers
• Campus network backbone
- Add/drop multiplexers
- Digital loop carriers
- Digital crossconnects
- Optical networking
• Enterprise network backbone
• Packaging
- Integrated 4-pin coaxial package
- Connector receptacle (panel or PCB mount) and fiber
pigtailed versions
- Case grounded versions
The EDR 51xx Series incorporates a 75 µm InGaAs PIN photodetector coupled
with a low cost BiCMOS transimpedance amplifier (TIA) designed to operate at
155 Mb/s (EDR 512x) or 622 Mb/s (EDR 515x). The PIN transduces optical
power into current with high efficiency. The TIA converts the current signal into
a voltage signal with a very low input noise current contribution. The EDR 512x
TIA also integrates an automatic gain control (AGC) circuit which decreases the
light to voltage conversion factor when the average incident optical power is
relatively high.
The EDR 51xx Series are assembled in rugged coaxial packages. They are available
with a connector receptacle or as a single mode fiber pigtail. Standard choices for
connector receptacles are LC, SC and FC. In addition, the EDR 51xx Series are
available in several standard pin-out configurations. The EDR 51xB is the simplest
configuration and provides a single ended output. The EDR 51xC provides access
to the photodiode current for those customers who need to design an alarm
circuit. The EDR 51xD provides a differential output for higher gain performance
without sacrifice to sensitivity and bandwidth.
NORTH AMERICA : 800 498-JDSU (5378)
WORLDWIDE : +800 5378-JDSU
WEBSITE : www.jdsu.com
ACCESS PIN-TIA RECEIVERS FOR 155 MB/S AND 622 MB/S
2
Typical Applications
The EDR 51xx Series are designed for many applications, including single mode
155 Mb/s (EDR 512x) and 622 Mb/s (EDR 515x) ATM receivers. The EDR 51xx
Series exceed Long Reach OC-3 (EDR 512x) and OC-12 (EDR 515x) SONET
receiver specifications and are ideal for transceiver designs or board level discrete
designs. Applications include receivers for digital cross connects, digital loop
carriers, add/drop multiplexers, optical network units and switches and routers
for LAN and WAN backbones.
External Circuitry
When designing the EDR 51xx Series into an optical receiver, standard high speed
printed circuit board design practices should be observed. For example, bypassing
of the power supply is recommended so as to reduce noise that appears at the
output of the PIN-TIA.
If signal traces are relatively long, use impedance matching techniques to maximize
power transfer from the PIN-TIA to its load: for microstrip design, assume 70 ohms
(EDR 512x) and 60 ohms (EDR 515x) as the output impedance for the PIN-TIA. Note
as well that the output of the PIN-TIA is DC-coupled. Since most applications require
AC-coupled stages, a high-Q RF chip capacitor should be placed on the output of the
module. To eliminate oscillations, the PIN-TIA should be mounted on a circuit board
with a large, low impedance ground plane. All the PIN-TIA leads should be made as
short as possible in order to reduce excess inductances. As a general rule, receiver
bandwidth requirements need only be greater than about 1/3 of the bit rate at which
they are intended to operate. A receiver for a 155 Mb/s system must have a bandwidth
greater than 110 MHz. A receiver for a 622 Mb/s system must have a bandwidth greater
than 415 MHz. On the other hand, any frequency component above 110 MHz for
155 Mb/s systems or above 415 MHz for 622 Mb/s systems contributes excess noise to
the output. The excess noise needlessly reduces the sensitivity of the receiver. The
receiver designer may therefore improve the PIN-TIA sensitivity by placing a low pass
noise filter on the output.
Performance Highlights
The EDR 51x Series offer a sensitivity of better than -36 dBm (EDR 512x) or -30 dBm
(EDR 515x) with appropriate filtering and a minimum overload of 0 dBm (EDR 512x)
or -7 dBm (EDR 515x). This large dynamic range makes these products ideal for both
long and short range applications. A time constant of 4 milliseconds makes the AGC
circuit of the EDR 512x models very stable, even during reception of the longest
streams of high or low logic levels. The EDR 51x Series operate over -40 to +85°C.
The EDR 51x Series provide significant benefits over hybrid designs and 14-pin
receivers. Integration of the TIA with the PIN detector onto the TO-46 header
reduces parasitic capacitances and lead inductances. The TO-52 cap hermetically
seals the hybrid and provides EMI shielding especially from the transmitter
circuit. These advantages improve sensitivity over designs that place the amplifier
outside the capsule and away from the detector. The EDR 51x Series, which have
four pins, are advantageous over 14-pin receivers because they require less board
space and fewer electrical connections. In addition, the EDR 51xx Series operate
from a single power supply, even in the pin-out configuration which provides
photodiode current monitoring. The smaller form factor and the need for a single
power supply make the EDR 51x Series a less expensive, high performance
alternative to other kinds of optical receivers.
ACCESS PIN-TIA RECEIVERS FOR 155 MB/S AND 622 MB/S
3
(Specifications in mm unless otherwise noted. )
Dimensions Diagram
EDR 51xx RSC-FM
EDR 51xx RSC-DM
TOP VIEW
22.0
18.0
TOP VIEW
22.0
18.0
(2) Thru Holes 2.30 diameter
(2) Thru Holes 2.30 diameter
9.20
9.20
12.75
12.75
6.80
12.3
19.45
12.3
19.8
15.2
15.2
4.20
4 Leads
(0.42 O.D. Typ.)
4 Leads
(0.42 O.D. Typ.)
2.2 diameter
13.5 Typ.
2.54 diameter
4
EDR 512B
EDR 515B
13.5 Typ.
EDR 512C
EDR 515C
EDR 512D
EDR 515D
1
2.54 diameter
1
2
EDR 512C
EDR 515C
EDR 512D
EDR 515D
2.54 diameter
EDR 512B
EDR 515B
1
4
2.54 diameter
1
2
7.0
7.0
7.0
7.0
2
BOTTOM VIEW
4
3
BOTTOM VIEW
3
2
BOTTOM VIEW
4
3
BOTTOM VIEW
3
Note: Critical dimensions meet NTT specifications.
Other dimensions subject to revision.
Note: Critical dimensions meet NTT specifications.
Other dimensions subject to revision.
EDR 51xx RFC2
EDR 51xx RLC
TOP VIEW
13.1
2.2 diameter holes with
4.0 diameter counterbore
1.5 deep
19.0
13.45
9.20
17.78
20.45
M8 x 0.75
6.0
7.8
2.0
2.67
7.0
13.7
5.4
4 Leads
(0.42 O.D. Typ.)
13.5 Typ
13.5 Typ.
4 Leads
(0.42 O.D. Typ.)
13.5
EDR 512B
EDR 515B
1
EDR 512C
EDR 515C
EDR 512D
EDR 515D
2.54 diameter
4
1
2.54 diameter
2
1
4
1
5.60 diameter
9.6
2
9.50 Radius
3
7.5
Pin circle
2.54 diameter
EDR 512B
EDR 515B
2
4
3
3
EDR 512C EDR 512D
EDR 515C EDR 515D
4
2
3
BOTTOM VIEW
BOTTOM VIEW
BOTTOM VIEW
EDR 51xx FJS with Bracket Option
Optimum point for
fiber coupling power
➤
BOTTOM VIEW
0.9 O.D. Fiber
4.7
➤
4
➤
2
➤
➤
o
➤
Leads
(0.45 O.D. Typ.)
1.00
4
3
1
4 Leads
(0.45 O.D. Typ.)
2
➤
➤
4.20
5.35
➤
➤
BOTTOM VIEW
1
10.0 ➤
18.0
➤
45
Bottom View
➤
2.54 Diameter
0.45 Diameter Typ.
7.7 17.0 12.7
➤
➤
1
➤
6.20
13.5 Typ.
4.0
MB-14
bracket
➤
13.5 Typ.
➤
➤
➤
3
4
➤
3.60
EDR 512 B
EDR 512 C
EDR 512 D
EDR 515 B
EDR 515 C
EDR 515 D
➤
1.9
Two 2.2 diameter
thru holes
➤
2 3
2.54 Diameter
➤
➤
➤
➤
➤
2.2
➤
EDR 51xx TL
ACCESS PIN-TIA RECEIVERS FOR 155 MB/S AND 622 MB/S
4
Electrical Schematics
EDR 512C, EDR 515C
EDR 512B, EDR 515B
2 Vcc
EDR 512D, EDR 515D
3 Vcc
3 Vcc
2 Vpd
Pin
Pin
TIA
TIA
1 Output
1 Output
1 Output
TIA
2 Output B
3,4 GND (Case)
4 GND (Case)
4 GND (Case)
Differential output is provided.
Access to photodiode current is provided.
Typical Low Pass Noise Filter Design
for 155 Mb/s and 622 Mb/s
EDR 512B, EDR 515B
NOISE FILTER
PIN - TIA
+Vcc
10 µF
0.1 µF
0.1 µF
L1
TIA
hv
V out
C2
C1
EDR 512C, EDR 515C
10 µF
NOISE FILTER
PIN - TIA
+Vcc
0.1 µF
TIA
0.1 µF
L1
hv
V out
C2
C1
100-1K Ω
VPD
+5V
EDR 512D, EDR 515D
10
µF
PIN - TIA
0.1
µF
NOISE FILTER
+Vcc
10 µF
L1
0.1 µF
hv
TIA
0.1 µF
C2
C1
L2
0.1 µF
V out
V out B
Model
L1
L2
C1
C2
EDR 512B
EDR 512C
EDR 512D
EDR 515B
EDR 515C
EDR 515D
150 nH
150 nH
120 nH
33 nH
33 nH
30 nH
120 nH
30 nH
27 pF
27 pF
18 pF
10 pF
10 pF
5.6 pF
27 pF
27 pF
18 pF
10 pF
10 pF
5.6 pF
ACCESS PIN-TIA RECEIVERS FOR 155 MB/S AND 622 MB/S
5
EDR 512x Specifications
(VCC = +5 V,TA = 25 °C, RL = 50 Ω (AC coupled),λ = 1300 nm.All specifications without connector.)
Parameter
Gain1
Bandwidth
Sensitivity2
Overload
Output resistance
Maximum output voltage
AGC time constant
AGC threshold
Minimum
Typical
Minimum
Typical
Typical
Maximum
Minimum
Typical
Typical
Typical
Typical
Typical
EDR 512B
EDR 512C
EDR 512D
15 V/mW
20 V/mW
110 MHz
200 MHz
-38.0 dBm
-36.0 dBm
0 dBm
2 dBm
70 Ω
400 mVpk-pk
4000 µs
2 µW
15 V/mW
20 V/mW
110 MHz
200 MHz
-38.0 dBm
-36.0 dBm
0 dBm
2 dBm
70 Ω
400 mVpk-pk
4000 µs
2 µW
25 V/mW
35 V/mW
110 MHz
200 MHz
-38.5 dBm
-36.5 dBm
0 dBm
2 dBm
70 Ω
800 mVpk-pk
4000 µs
2 µW
1. Measured at 100 MHz.
2. BER of 1E-10, 120 MHz noise filter.
EDR 515x Specifications
(VCC = +3.3 V,TA = 25 °C, RL = 50 Ω (AC coupled),λ = 1300 nm.All specifications without connector.)
Parameter
Gain1
Bandwidth
Sensitivity2
Overload
Output resistance
Maximum output voltage
1. Measured at 300 MHz.
2. BER of 1E-10, 415 MHz noise filter.
Minimum
Typical
Minimum
Typical
Typical
Maximum
Minimum
Maximum
Minimum
Typical
Maximum
Maximum
EDR 515B
EDR 515C
EDR 515D
1.7 V/mW
2.2 V/mW
415 MHz
500 MHz
-31.5 dBm
-30.0 dBm
-7.0 dBm
-4.0 dBm
45 Ω
60 Ω
75 Ω
500 mVpk-pk
1.7 V/mW
2.2 V/mW
415 MHz
500 MHz
-31.5 dBm
-30.0 dBm
-7.0 dBm
-4.0 dBm
45 Ω
60 Ω
75 Ω
500 mVpk-pk
3.0 V/mW
4.0 V/mW
415 MHz
500 MHz
-32.5 dBm
-31.0 dBm
-7.0 dBm
-4.0 dBm
45 Ω
60 Ω
75 Ω
950 mVpk-pk
ACCESS PIN-TIA RECEIVERS FOR 155 MB/S AND 622 MB/S
6
EDR 512x DC Electrical Characteristics and Maximum Ratings
Parameter
Minimum
Typical
Maximum
Supply voltage (VCC)
Output offset voltage
Diff. output offset voltage1
Supply current (ICC)
Dark current2
Optical input power
Operating temperature
Storage temperature
Photodiode voltage (Vpd)2
4.5 V
2.9 V
-40 °C
-40 °C
2V
5.0 V
3.2 V
80 mV
25 mA
-
5.5 V
3.5 V
50 mA
1 nA
5.0 mW
85 °C
85 °C
25 V
1. Applies to EDR 512D only.
2. Applies to EDR 512C only.
EDR 515x DC Electrical Characteristics and Maximum Ratings
Parameter
Minimum
Typical
Maximum
Supply voltage (VCC)
Output offset voltage
Diff. output offset voltage1
Supply current (ICC)
Dark current2
Optical input power
Operating temperature
Storage temperature
Photodiode voltage (Vpd)2
3.0 V
12 mA
-40 °C
-40 °C
2V
3.3/5.0 V
2.0/3.7 V
7.0 mV
25/35 mA
-
5.25 V
50 mA
1.0 nA
5.0 mW
85 °C
85 °C
25 V
1. Applies to EDR 515D only.
2. Applies to EDR 515C only.
ACCESS PIN-TIA RECEIVERS FOR 155 MB/S AND 622 MB/S
Ordering Information
For more information on this or other products and their availability, please contact your local JDSU account manager or
JDSU directly at 1-800-498-JDSU (5378) in North America and +800-5378-JDSU worldwide or via e-mail at
[email protected]
Sample: EDR 512C FJS LC
+
EDR 51
Code
2
5
Speed
155 Mb/s
622 Mb/s
Code
B
C
PIN-TIA
Single-ended output with case connected to ground
Access to photodiode current with case
connected to ground
With differential output voltage
D
Code
TL
FJS
RLC
RFC2
RSC-DM
RSC-FM
+
+
Package
Transistor ouline with lensed cap
Single mode (900 µm) fiber jacket
LC receptacle
FC receptacle with 2-hole flange
SC receptacle, dual-mount (panel & board)
SC receptacle, front-mount (panel only)
Code
LC
FC/SPC
SC/SPC
Connector (FJS only)
LC connector
FC/SPC connector
SC/SPC connector
Code
0
MB14
Bracket (FJS only)
No bracket
MB-14 bracket
Precautions for Use
ESD protection is imperative. Use of grounding straps, anti-static mats, and other standard ESD protective equipment is
required when handling or testing an InGaAs PIN or any other junction photodiode. Fiber pigtails should be handled with
less than 10 N pull and with bending radius greater than 1 inch. Soldering temperature of the leads should not exceed 260 °C
for more than 10 seconds.
All statements, technical information and recommendations related to the products herein are based upon information believed to be
reliable or accurate. However, the accuracy or completeness thereof is not guaranteed, and no responsibility is assumed for any
inaccuracies. The user assumes all risks and liability whatsoever in connection with the use of a product or its application. JDSU reserves
the right to change at any time without notice the design, specifications, function, fit or form of its products described herein, including
withdrawal at any time of a product offered for sale herein. JDSU makes no representations that the products
herein are free from any intellectual property claims of others. Please contact JDSU for more information. JDSU and the JDSU logo are
trademarks of JDS Uniphase Corporation. Other trademarks are the property of their respective holders. ©2006 JDS Uniphase
Corporation. All rights reserved. 30137554 Rev. 001 06/06 EDR51XX.DS.CC.AE
NORTH AMERICA : 800 498-JDSU (5378)
WORLDWIDE : +800 5378-JDSU
WEBSITE : www.jdsu.com