LTC1864L/LTC1865L µPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP U FEATURES DESCRIPTIO ■ The LTC®1864L/LTC1865L are 16-bit A/D converters that are offered in MSOP and SO-8 packages and operate on a single 3V supply. At 150ksps, the supply current is only 450µA. The supply current drops at lower speeds because the LTC1864L/LTC1865L automatically power down between conversions. These 16-bit switched capacitor successive approximation ADCs include sample-and-holds. The LTC1864L has a differential analog input with an external reference pin. The LTC1865L offers a softwareselectable 2-channel MUX and an external reference pin on the MSOP version. ■ ■ ■ ■ ■ ■ ■ ■ ■ 16-Bit 150ksps ADCs in MSOP Package Single 3V Supply Low Supply Current: 450µA (Typ) Auto Shutdown Reduces Supply Current to 10µA at 1ksps True Differential Inputs 1-Channel (LTC1864L) or 2-Channel (LTC1865L) Versions SPI/MICROWIRETM Compatible Serial I/O 16-Bit Upgrade to 12-Bit LTC1285/LTC1288 Pin Compatible with 12-Bit LTC1860L/LTC1861L No Minimum Data Transfer Rate U APPLICATIO S ■ ■ ■ ■ High Speed Data Acquisition Portable or Compact Instrumentation Low Power Battery-Operated Instrumentation Isolated and/or Remote Data Acquisition The 3-wire, serial I/O, small MSOP or SO-8 package and extremely high sample rate-to-power ratio make these ADCs ideal choices for compact, low power, high speed systems. These ADCs can be used in ratiometric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans down to 1V full scale allow direct connection to signal sources in many applications, eliminating the need for external gain stages. , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. U TYPICAL APPLICATIO Supply Current vs Sampling Frequency Single 3V Supply, 150ksps, 16-Bit Sampling ADC 1000 3V LTC1864L 1 ANALOG INPUT 0V TO 3V VREF VCC 2 IN + SCK 3 IN – SDO 4 GND CONV 8 7 6 5 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS SUPPLY CURRENT (µA) 1µF CONV LOW = 2µs TA = 25°C VCC = 2.7V 100 10 1 1864 TA01 0.1 0.01 0.1 100 1 10 SAMPLING FREQUENCY (kHz) 1000 1864L/65L TA02 sn18645L 18645Lfs 1 LTC1864L/LTC1865L W W W AXI U U ABSOLUTE RATI GS (Notes 1, 2) Supply Voltage (VCC) ................................................. 7V Ground Voltage Difference AGND, DGND LTC1865L MSOP Package ......... ±0.3V Analog Input ............... (GND – 0.3V) to (VCC + 0.3V) Digital Input ................................ (GND – 0.3V) to 7V Digital Output .............. (GND – 0.3V) to (VCC + 0.3V) Power Dissipation .............................................. 400mW Operating Temperature Range LTC1864LC/LTC1865LC/ LTC1864LAC/LTC1865LAC .................... 0°C to 70°C LTC1864LI/LTC1865LI/ LTC1864LAI/LTC1865LAI ................. – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C U U W PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW TOP VIEW VREF IN + IN¯ GND 8 7 6 5 1 2 3 4 ORDER PART NUMBER LTC1864LCMS8 LTC1864LIMS8 LTC1864LACMS8 LTC1864LAIMS8 VCC SCK SDO CONV MS8 PACKAGE 8-LEAD PLASTIC MSOP CONV CH0 CH1 AGND DGND LTC1865LCMS LTC1865LIMS LTC1865LACMS LTC1865LAIMS VREF VCC SCK SDO SDI MS PACKAGE 10-LEAD PLASTIC MSOP MS8 PART MARKING TJMAX = 150°C, θJA = 210°C/W 10 9 8 7 6 1 2 3 4 5 MS PART MARKING TJMAX = 150°C, θJA = 210°C/W LTC7 LTJ4 ORDER PART NUMBER TOP VIEW VREF 1 8 VCC IN + 2 7 SCK IN – 3 6 SDO GND 4 5 CONV LTC1864LCS8 LTC1864LIS8 LTC1864LACS8 LTC1864LAIS8 S8 PACKAGE 8-LEAD PLASTIC SO CONV 1 8 VCC CH0 2 7 SCK CH1 3 6 SDO GND 4 5 SDI 1864L 1864LI LTC1865LCS8 LTC1865LIS8 LTC1865LACS8 LTC1865LAIS8 S8 PACKAGE 8-LEAD PLASTIC SO S8 PART MARKING TJMAX = 150°C, θJA = 175°C/W ORDER PART NUMBER TOP VIEW S8 PART MARKING TJMAX = 150°C, θJA = 175°C/W 1864LA 864LAI 1865L 1865LI 1865LA 865LAI Consult LTC Marketing for parts specified with wider operating temperature ranges. W U U CO VERTER A D ULTIPLEXER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. ● PARAMETER CONDITIONS Resolution No Missing Codes Resolution INL (Note 3) ● 16 ● 14 15 Bits ±6 2 ±20 UNITS Bits ±8 2 ● LTC1864LA/LTC1865LA MIN TYP MAX 16 ● Transition Noise Gain Error LTC1864L/LTC1865L MIN TYP MAX LSB LSBRMS ±20 mV sn18645L 18645Lfs 2 LTC1864L/LTC1865L W U U CO VERTER A D ULTIPLEXER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. PARAMETER CONDITIONS LTC1864L/LTC1865L MIN TYP MAX LTC1864LA/LTC1865LA MIN TYP MAX ±2 ±2 ● Offset Error = IN + – IN – ● Input Differential Voltage Range VIN Absolute Input Range IN + Input IN – Input VREF Input Range LTC1864L SO-8 and MSOP, LTC1865L MSOP Analog Input Leakage Current (Note 4) CIN Input Capacitance In Sample Mode During Conversion ±5 UNITS mV ±5 0 VREF 0 VREF V – 0.05 – 0.05 VCC + 0.05 VCC /2 – 0.05 – 0.05 VCC + 0.05 VCC /2 V V 1 VCC 1 VCC V ±1 µA ● ±1 12 5 12 5 pF pF W U DY A IC ACCURACY TA = 25°C. VCC = 3V, VREF = 3V, fSAMPLE = 150kHz, unless otherwise noted. SYMBOL PARAMETER SNR Signal-to-Noise Ratio S/(N + D) Signal-to-Noise Plus Distortion Ratio THD LTC1864L/LTC1865L MIN TYP MAX CONDITIONS UNITS 82 dB 1kHz Input Signal 82 dB Total Hamonic Distortion Up to 5th Harmonic 1kHz Input Signal 92 dB Full Power Bandwidth 10 MHz 20 kHz Full Linear Bandwidth S/(N + D) ≥ 75dB U DIGITAL A D DC ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted. LTC1864L/LTC1865L MIN TYP MAX SYMBOL PARAMETER CONDITION VIH High Level Input Voltage VCC = 3.3V ● VIL Low Level Input Voltage VCC = 2.7V ● IIH High Level Input Current VIN = VCC ● 2.5 µA IIL Low Level Input Current VIN = 0V ● – 2.5 µA VOH High Level Output Voltage VCC = 2.7V, IO = 10µA VCC = 2.7V, IO = 360µA ● ● VOL Low Level Output Voltage VCC = 2.7V, IO = 400µA ● 0.3 V IOZ Hi-Z Output Leakage CONV = VCC ● ±3 µA ISOURCE Output Source Current VOUT = 0V ISINK Output Sink Current VOUT = VCC IREF Reference Current (LTC1864L SO-8 and MSOP, LTC1865L MSOP) CONV = VCC fSMPL = fSMPL(MAX) ● ● 0.001 0.01 3 0.1 µA mA ICC Supply Current CONV = VCC After Conversion fSMPL = fSMPL(MAX) ● ● 0.5 0.45 10 1.0 µA mA PD Power Dissipation fSMPL = fSMPL(MAX) 1.9 V 0.45 2.3 2.1 UNITS 2.6 2.45 V V – 6.5 mA 6.5 1.22 V mA mW sn18645L 18645Lfs 3 LTC1864L/LTC1865L U U U U WW RECO E DED OPERATI G CO DITIO S The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. SYMBOL PARAMETER LTC1864L/LTC1865L MIN TYP MAX CONDITIONS VCC Supply Voltage fSCK Clock Frequency tCYC Total Cycle Time tSMPL Analog Input Sampling Time (Note 5) tsuCONV Setup Time CONV↓ Before First SCK↑ (See Figure 1) thDI Hold Time SDI After SCK↑ LTC1865L 30 ns tsuDI Setup Time SDI Stable Before SCK↑ LTC1865L 30 ns tWHCLK SCK High Time fSCK = fSCK(MAX) 45% 1/fSCK tWLCLK SCK Low Time fSCK = fSCK(MAX) 45% 1/fSCK tWHCONV CONV High Time Between Data Transfer Cycles tCONV µs tWLCONV CONV Low Time During Data Transfer 16 SCK thCONV Hold Time CONV Low After Last SCK↑ 26 ns ● 2.7 3.6 DC 8 UNITS 16 • SCK + tCONV LTC1864L LTC1865L V MHz µs 16 14 SCK SCK 60 ns WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. LTC1864L/LTC1865L MIN TYP MAX SYMBOL PARAMETER CONDITIONS tCONV Conversion Time (See Figure 1) ● fSMPL(MAX) Maximum Sampling Frequency ● tdDO Delay Time, SCK↓ to SDO Data Valid CLOAD = 20pF tdis Delay Time, CONV↑ to SDO Hi-Z ten Delay Time, CONV↓ to SDO Enabled CLOAD = 20pF ● thDO Time Output Data Remains Valid After SCK↓ CLOAD = 20pF ● tr SDO Rise Time tf SDO Fall Time 3.7 4.66 150 45 55 60 ns ns 55 120 ns 35 120 ns 15 ns CLOAD = 20pF 25 ns CLOAD = 20pF 12 ns Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 5 µs kHz ● ● UNITS Note 4: Channel leakage current is measured while the part is in sample mode. Note 5: Assumes fSCK = fSCK(MAX) In the case of the LTC1864L SCK does not have to be clocked during this time if the SDO data word is not desired. In the case of the LTC1865L a minimum of 2 clocks are required on the SCK input after CONV falls to configure the MUX during this time. sn18645L 18645Lfs 4 LTC1864L/LTC1865L U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Sampling Frequency Sleep Current vs Temperature Supply Current vs Temperature 600 20 fS = 150kHz VCC = 2.7V VREF = 2.5V 500 100 10 1 SHUTDOWN CURRENT (µA) CONV LOW = 2µs TA = 25°C VCC = 2.7V SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 1000 400 300 200 fS = 150kHz VCC = 2.7V VREF = 2.5V 15 10 5 100 0.1 0.01 0.1 100 1 10 SAMPLING FREQUENCY (kHz) 0 –50 –25 1000 50 25 75 0 TEMPERATURE (°C) 0 –50 –25 125 Reference Current vs Sampling Rate 7 6 5 4 3 2 25 fS = 150kHz VCC = 2.7V VREF = 2.5V 20 REFERENCE CURRENT (µA) REFERENCE CURRENT (µA) 8 125 Reference Current vs Reference Voltage 25 CONV LOW = 2µs TA = 25°C VCC = 2.7V VREF = 2.5V 100 1864L/65L G03 Reference Current vs Temperature 10 9 50 25 75 0 TEMPERATURE (°C) 1864L/65L G02 1864L/65L G01 REFERENCE CURRENT (µA) 100 15 10 5 fS = 150kHz TA = 25°C VCC = 3.6V 20 15 10 5 1 0 –50 –25 0 0 25 75 100 125 50 SAMPLING FREQUENCY (kHz) 150 0 50 25 75 0 TEMPERATURE (°C) Typical INL Curve VCC = 2.7V VREF = 2.5V fS = 150kHz ANALOG INPUT LEAKAGE (nA) –2 0 –1 16384 32768 49152 65536 CODE –2 0 16384 32768 49152 65536 CODE 1865 G02 1.0 1.5 2.0 2.5 3.0 REFERENCE VOLTAGE (V) 4.0 3.5 Analog Input Leakage Current vs Temperature 1 DNL ERROR (LSBs) 2 0 0.5 1864L/65L G06 100 2 VCC = 2.7V VREF = 2.5V fS = 150kHz 0 0 Typical DNL Curve 4 INL ERROR (LSBs) 125 1864L/65L G05 1864L/65L G04 –4 100 1865 G03 CONV = 0V VCC = 2.7V VREF = 2.5V 75 50 25 0 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1864L/65L G09 sn18645L 18645Lfs 5 LTC1864L/LTC1865L U W TYPICAL PERFOR A CE CHARACTERISTICS Change in Offset vs Reference Voltage fS = 150kHz TA = 25°C VCC = 3.6V VCC = 2.7V VREF = 2.5V 10 5 0 –5 –10 3 2 1 0 –1 –2 –3 –15 –4 –20 –5 2 3 1 REFERENCE VOLTAGE (V) 0 4 50 25 75 0 TEMPERATURE (°C) –50 –25 VCC = 2.7V VREF = 2.5V 648 689 576 600 407 400 –2 291 –3 169 200 –4 152 52 50 25 75 0 TEMPERATURE (°C) 100 0 125 45 20 0 7 0 0 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 CODE SINAD vs Input Frequency 0 –20 70 –30 50 40 fS = 125kHz TA = 25°C VCC = 3V VIN = 0dB VREF = 3V 100 1864L/65L G16 5 10 15 20 25 30 35 40 45 50 55 60 65 INPUT FREQUENCY (kHz) 1864L/65L G15 SFDR vs Input Frequency 100 90 80 70 –40 SFDR (dB) SINAD THD (dB) SINAD (dB) 80 –50 –60 60 50 40 –70 30 –80 20 –90 10 –100 1 10 INPUT FREQUENCY (kHz) 4 fS = 125kHz TA = 25°C VCC = 3V VIN = 0.946045kHz VREF = 3V 0 fS = 125kHz TA = 25°C VCC = 3V VIN = 0dB VREF = 3V –10 SNR 10 INPUT FREQUENCY (kHz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 THD vs Input Frequency 100 90 2 3 1 REFERENCE VOLTAGE (V) 1864L/65L G14 1864L/65L G13 1 –3 1864L/65L G12 AMPLITUDE (dB) FREQUENCY CHANGE IN GAIN ERROR (LSB) 0 –1 10 –2 4096 Point FFT Nonaveraged 800 20 –1 0 1000 1 30 0 –5 125 1040 2 60 1 Histogram of 4096 Conversions of a DC Input Voltage 3 0 100 1200 –50 –25 2 1864L/65L G11 Change in Gain Error vs Temperature 4 3 –4 1864L/65L G10 5 fS = 150kHz TA = 25°C VCC = 3.6V 4 GHANGE IN GAIN ERROR (LSB) 4 CHANGE IN OFFSET (LSB) 15 CHANGE IN OFFSET (LSB) 5 5 20 –5 Change in Gain Error vs Reference Voltage Change in Offset vs Temperature 100 1864L/65L G17 0 fS = 125kHz TA = 25°C VCC = 3V VIN = 0dB VREF = 3V 1 10 INPUT FREQUENCY (kHz) 100 1864L/65L G18 sn18645L 18645Lfs 6 LTC1864L/LTC1865L U U U PI FU CTIO S LTC1864L VREF (Pin 1): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. IN +, IN– (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. CONV (Pin 5): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this pin. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. LTC1865L (MSOP Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to AGND. AGND (Pin 4): Analog Ground. AGND should be tied directly to an analog ground plane. DGND (Pin 5): Digital Ground. DGND should be tied directly to an analog ground plane. SDO (Pin 7): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 8): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 9): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF (Pin 10): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to AGND. SDI (Pin 6): Digital Data Input. The A/D configuration word is shifted into this input. LTC1865L (SO-8 Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. SDI (Pin 5): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF is tied internally to this pin. sn18645L 18645Lfs 7 LTC1864L/LTC1865L W FUNCTIONAL BLOCK DIAGRA U CONV (SDI) SCK U VCC PIN NAMES IN PARENTHESES REFER TO LTC1865L CONVERT CLK SDO SERIAL PORT BIAS AND SHUTDOWN DATA IN 16 BITS + IN (CH0) + IN – (CH1) – 16-BIT SAMPLING ADC DATA OUT 1864/65 BD GND VREF TEST CIRCUITS Load Circuit for t dDO, t r, t f, t dis and t en Voltage Waveforms for SDO Rise and Fall Times, t r, t f TEST POINT VOH SDO VOL VCC tdis WAVEFORM 2, ten 3k SDO tdis WAVEFORM 1 20pF tr tf 1864 TC04 1864 TC01 Voltage Waveforms for t en Voltage Waveforms for t dis CONV VIH CONV SDO 1864 TC03 SDO WAVEFORM 1 (SEE NOTE 1) ten 90% tdis Voltage Waveforms for SDO Delay Times, t dDO and t hDO SDO WAVEFORM 2 (SEE NOTE 2) 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL SCK VIL tdDO 1864 TC05 thDO VOH SDO VOL 1864 TC02 sn18645L 18645Lfs 8 LTC1864L/LTC1865L U W U U APPLICATIO S I FOR ATIO LTC1864L OPERATION Analog Inputs Operating Sequence The LTC1864L has a unipolar differential analog input. The converter will measure the voltage between the “IN + ” and “IN – ” inputs. A zero code will occur when IN+ minus IN – equals zero. Full scale occurs when IN+ minus IN – equals VREF minus 1LSB. See Figure 2. Both the “IN+ ” and “IN – ” inputs are sampled at the same time, so common mode noise on the inputs is rejected by the ADC. If “IN – ” is grounded and VREF is tied to VCC, a rail-to-rail input span will result on “IN+ ” as shown in Figure 3. The LTC1864L conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1864L goes into sleep mode drawing only leakage current. On the falling edge of CONV, the LTC1864L goes into sample mode and SDO is enabled. SCK synchronizes the data transfer with each bit being transmitted from SDO on the falling SCK edge. The receiving system should capture the data from SDO on the rising edge of SCK. After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 1. Reference Input The voltage on the reference input of the LTC1864L defines the full-scale range of the A/D converter. The LTC1864L can operate with reference voltages from VCC to 1V. CONV t SMPL SLEEP MODE tCONV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DON'T CARE SCK B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* SDO Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1854 F01 Figure 1. LTC1864L Operating Sequence 1µF VCC 1111111111111111 1111111111111110 LTC1864L • • • 1 VIN = 0V TO VCC 0000000000000001 0000000000000000 VIN* VREF VCC 2 IN + SCK 3 IN – SDO GND CONV 4 VREF VREF – 1LSB Figure 2. LTC1864L Transfer Curve VREF – 2LSB 1LSB 0V *VIN = IN + – IN – 8 7 6 5 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS 1864 F03 1864 F02 Figure 3. LTC1864L with Rail-to-Rail Input Span sn18645L 18645Lfs 9 LTC1864L/LTC1865L U W U U APPLICATIO S I FOR ATIO LTC1865L OPERATION Operating Sequence The LTC1865L conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1865L goes into sleep mode drawing only leakage current. The LTC1865L’s 2-bit data word is clocked into the SDI input on the rising edge of SCK after CONV goes low. Additional inputs on the SDI pin are then ignored until the next CONV cycle. The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 4. single-ended mode, all input channels are measured with respect to GND. A zero code will occur when the “+” input minus the “–” input equals zero. Full scale occurs when the “+” input minus the “–” input equals VREF minus 1LSB. See Figure 5. Both the “+” and “–” inputs are sampled at the same time so common mode noise is rejected. The input span in the SO-8 package is fixed at VREF = VCC. If the “–” input in differential mode is grounded, a rail-to-rail input span will result on the “+” input. Reference Input The reference input of the LTC1865L SO-8 package is internally tied to VCC. The span of the A/D converter is therefore equal to VCC. The voltage on the reference input of the LTC1865L MSOP package defines the span of the A/D converter. The LTC1865L MSOP package can operate with reference voltages from 1V to VCC. Analog Inputs Table 1. Multiplexer Channel Selection The two bits of the input word (SDI) assign the MUX configuration for the next requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the “+” and “–” signs in the selected row of Table 1. In MUX ADDRESS SGL/DIFF ODD/SIGN 0 1 1 1 0 0 1 0 SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE CHANNEL # 0 1 + + + – – + GND – – 1864 TBL1 CONV SDI t SMPL SLEEP MODE tCONV DON’T CARE S/D O/S 1 SCK SDO 2 DON’T CARE 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DON'T CARE B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1864 F04 Figure 4. LTC1865L Operating Sequence sn18645L 18645Lfs 10 LTC1864L/LTC1865L U W U U APPLICATIO S I FOR ATIO GENERAL ANALOG CONSIDERATIONS Grounding The LTC1864L/LTC1865L should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, use a printed circuit board. The ground pins (AGND and DGND for the LTC1865L MSOP package and GND for the LTC1864L and LTC1865L SO-8 package) should be tied directly to the analog ground plane with minimum lead length. Bypassing For good performance, the VCC and VREF pins must be free of noise and ripple. Any changes in the VCC/VREF voltage with respect to ground during the conversion cycle can induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with a minimum of 1µF tantalum. Keep the bypass capacitor leads as short as possible. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1864L/ LTC1865L have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem if source resistances are less than 200Ω or high speed op amps are used (e.g., the LT®1211, LT1469, LT1807, LT1810, LT1630, LT1226 or LT1215). But if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conversion begins. 1111111111111111 1111111111111110 • • • VIN* 0000000000000001 0000000000000000 VCC VCC – 1LSB VCC – 2LSB 1LSB 0V *VIN = (SELECTED “+” CHANNEL) – (SELECTED “–” CHANNEL) REFER TO TABLE 1 1864 F05 Figure 5. LTC1865L Transfer Curve sn18645L 18645Lfs 11 12 J1 J2 E9 E8 P3 P2 P1 P0 3.3VDIG 1 4 2 3 JP9 3 JP8 4 IN – IN + 1 2 5 6 3 2 IN – AGND 5 6 3 2 IN + 15V 15V 5 6 5 6 2 3 P3 P2 P1 P0 – + VIN U9A 74AC00 1 2 3 4 5 6 7 8 ON 1 1 6 RESET CLK P0 P1 P2 P3 ENP GND VCC RCO Q0 Q1 Q2 Q3 ENT LO U6 74HC163AD 2 JP1 +IN 3 R1 100Ω 1206 BUF 3 R3 2Ω 16 15 14 13 12 11 10 9 BUF OFF JP2 R2 100Ω –IN GND JP3 2 6 U9B 74AC00 IN– 3.3VDIG 3 C6 –15V 0.1µF 4 U2 OPT 7 IN+ 1 VOUT GND 4 C5 15V 0.1µF C20 0.1µF 2 U1 LT1460DCS8-2.5 C23 0.1µF 1 2 3 4 5 6 7 8 RESET CLK P0 P1 P2 P3 ENP GND VCC RCO Q0 Q1 Q2 Q3 ENT LO U7 74HC163AD C17 0.1µF U13B 74AC32 16 15 14 13 12 11 10 9 8 VCC 7 SCLK 6 DOUT 5 CONV U3 LTC1864LAIMS8 1 V 2 REF +IN 3 –IN 4 GND C4 0.1µF R8 1M R7 20k R10 10k CLK C24 0.1µF 1 2 3 4 RN1 330 U10 LTC1799 1 + V 2 GND 3 SET 3.3VDIG DIV OUT C18 0.1µF 3.3VAN 8 7 6 5 4 5 INT 3 2 JP6 CLK R4 2Ω EXT 1 U8C 74AC14 U13C 74AC32 CKIN 3 2 CKIN 1 U8D 74AC14 JP7 EXTCK U8B 74AC14 U8A 74AC14 C12 10µF 6.3V 1206 3.3VDIG C10 3.3VDIG 0.1µF C22 47pF R6 402Ω 1% C21 47pF R5 402Ω 1% 1 LT1121-3.3 3 VIN VOUT GND 2 U12B 74AC109 16 JP4 14 10 VCC CONV Q J 3 13 9 1 Q K 12 2 EXT INT CLK 15 CLR 11 8 PRE GND 3.3VDIG ANALOG GROUND PLANE C9 100pF 1206 3.3VDIG C16 0.1µF 3.3VDIG C3 10µF 6.3V 1206 C7 100pF 1206 U12A 74AC109 16 2 6 VCC Q J 3 7 Q K 4 CLK 1 CLR 5 8 GND PRE 3.3VDIG 3.3VDIG C8 470pF 1205 C1 0.1µF C2 1µF 10V 0805 3.3VAN 15V U8E 74AC14 U8F 74AC14 1 2 3 4 5 6 7 8 U9C 74AC00 U5 74HC595ADT QB VCC QC QA QD A QE OENB QF LCLK QG SCLK QH RESET GND SQH 1 GND 3 U13D 74AC32 R9 51Ω U9D 74AC00 EN EXT JP5 2 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 CONV CLKIN CLKOUT DOUT DGND 2 3 6 5 J3 E5 E4 E6 E3 ENABLE DATA E7 DGND E2 C15 3.3VDIG 0.1µF 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 J4 3201S40G1 1864/65 AI1 NOTES: UNLESS OTHERWISE SPECIFIED INSTALL SHUNTS ON JP1, JP3-JP7 PIN 1 AND PIN2; ON JP8 AND JP9 PIN 2 AND PIN 4, PIN 3 AND PIN 5. U13A 74AC32 C19 3.3VDIG 0.1µF 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 C14 0.1µF 3.3VDIG U4 3.3VDIG 74HC595ADT 16 QB V 15 CC QC QA 14 QD A 13 QE OENB 12 QF LCLK 11 QG SCLK 10 RESET QH 9 GND SQH C13 0.1µF 3.3VDIG U U W E1 APPLICATIO S I FOR ATIO U LTC1864L Evaluation Circuit Schematic LTC1864L/LTC1865L sn18645L 18645Lfs LTC1864L/LTC1865L U W U U APPLICATIO S I FOR ATIO Component Side Silk Screen for LTC1864L Evaluation Circuit Component Side Showing Traces (Note Wider Traces on Analog Side) Bottom Side Showing Traces (Note Almost No Analog Traces on Board Bottom) Ground Layer with Separate Analog and Digital Grounds Supply Layer with 5V Digital Supply and Analog Ground Repeated sn18645L 18645Lfs 13 LTC1864L/LTC1865L U PACKAGE DESCRIPTIO MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.2 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.65 (.0256) BSC 0.42 ± 0.04 (.0165 ± .0015) TYP 8 7 6 5 0.52 (.206) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 ± 0.102 (.118 ± .004) NOTE 4 4.90 ± 0.15 (1.93 ± .006) DETAIL “A” 0° – 6° TYP GAUGE PLANE 1 0.53 ± 0.015 (.021 ± .006) DETAIL “A” 2 3 4 1.10 (.043) MAX 0.86 (.034) REF 0.18 (.077) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) BSC 0.13 ± 0.076 (.005 ± .003) MSOP (MS8) 0802 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX sn18645L 18645Lfs 14 LTC1864L/LTC1865L U PACKAGE DESCRIPTIO S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 .050 BSC 8 .245 MIN 7 6 5 .160 ±.005 .150 – .157 (3.810 – 3.988) NOTE 3 .228 – .244 (5.791 – 6.197) .030 ±.005 TYP 1 RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) 3 2 4 .053 – .069 (1.346 – 1.752) .008 – .010 (0.203 – 0.254) .004 – .010 (0.101 – 0.254) 0°– 8° TYP .016 – .050 (0.406 – 1.270) .050 (1.270) BSC .014 – .019 (0.355 – 0.483) TYP NOTE: 1. DIMENSIONS IN INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) SO8 0303 MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.2 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 10 9 8 7 6 3.00 ± 0.102 (.118 ± .004) NOTE 4 4.90 ± 0.15 (1.93 ± .006) DETAIL “A” 0.497 ± 0.076 (.0196 ± .003) REF 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.01 (.021 ± .006) DETAIL “A” 0.86 (.034) REF 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.13 ± 0.076 (.005 ± .003) MSOP (MS) 0802 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX sn18645L 18645Lfs Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1864L/LTC1865L U TYPICAL APPLICATIO Tiny 2-Chip Data Acquisition System 1µF 3V 3V 0.1µF 8 + 3 VIN 4 LTC6910-1 – 2 7 6 VREF 1 499Ω 5 270pF IN+ SCK LTC1864L SDO IN – GND AGND 1µF VCC CONV ADC GAIN CONTROL CONTROL LTC6910-1 (IN TSOT-23 PACKAGE) COMPACTLY ADDS 40dB OF INPUT GAIN RANGE TO THE LTC1864L (IN MSOP 8-PIN PACKAGE). SINGLE 3V SUPPLY 1864L/65L TA03 RELATED PARTS PART NUMBER SAMPLE RATE POWER DISSIPATION DESCRIPTION 12-Bit Serial I/O ADCs LTC1860L/LTC1861L 150ksps 1.22mW Pin Compatible with LTC1864L/LTC1865L LTC1860/LTC1861 250ksps 4.25mW Pin Compatible with LTC1864/LTC1865 LTC1417 400ksps 20mW 16-Pin SSOP, Unipolar or Bipolar, Reference, 5V or ±5V LTC1418 200ksps 15mW Serial/Parallel I/O, Internal Reference, 5V or ±5V LTC1609 200ksps 65mW Configurable Bipolar or Unipolar Input Ranges, 5V LTC1864/LTC1865 250ksps 4.25mW 14-Bit Serial I/O ADCs 16-Bit Serial I/O ADCs MSOP, SO-8, 1- and 2-Channel, 5V Supply References LT1460 Micropower Precision Series Reference Bandgap, 130µA Supply Current, 10ppm/°C, Available in SOT-23 LT1790 Micropower Low Dropout Reference 60µA Supply Current, 10ppm/°C, SOT-23 LT1468/LT1469 Single/Dual 90MHz, 16-Bit Accurate Op Amps 22V/µs Slew Rate, 75µV/125µV Offset LT1806/LT1807 Single/Dual 325MHz Low Noise Op Amps 140V/µs Slew Rate, 3.5nV/√Hz Noise, – 80dBc Distortion LT1809/LT1810 Single/Dual 180MHz Low Distortion Op Amps 350V/µs Slew Rate, – 90dBc Distortion at 5MHz Op Amps sn18645L 18645Lfs 16 Linear Technology Corporation LT/TP 0403 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2001