MITSUBISHI M37702S1BFP

MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
M37702M2-XXXFP and
M37702S1FP are respectively
unified into M37702M2AXXXFP
and M37702S1AFP.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DESCRIPTION
M37702M2BXXXFP, M37702S1BFP
(The fastest instruction at 25 MHz frequency) .................. 160 ns
• Single power supply ..................................................... 5 V ± 10%
• Low power dissipation (at 16 MHz frequency)
......................................... 60 mW (Typ.)
• Interrupts ............................................................ 19 types 7 levels
• Multiple function 16-bit timer ................................................ 5 + 3
• UART (may also be synchronous) .............................................. 2
• 8-bit A-D converter ............................................. 8-channel inputs
• 12-bit watchdog timer.
• Programmable input/output
(ports P0, P1, P2, P3, P4, P5, P6, P7, P8) .............................. 68
The M37702M2AXXXFP is a single-chip microcomputers
designed with high-performance CMOS silicon gate technology.
This is housed in a 80-pin plastic molded QFP. This single-chip
microcomputer has a large 16 M bytes address space, three instruction queue buffers, and two data buffers for high-speed
instruction execution. The CPU is a 16-bit parallel processor that
can also be switched to perform 8-bit parallel processing. This
microcomputer is suitable for office, business, and industrial
equipment controller that require high-speed processing of large
data.
The differences between M37702M2AXXXFP, M37702M2BXXXFP,
M37702S1AFP and M37702S1BFP are the ROM size and the external clock input frequency as shown below. Therefore, the
following descriptions will be for the M37702M2AXXXFP unless
otherwise noted.
Type name
M37702M2AXXXFP
M37702M2BXXXFP
ROM size
16 K bytes
16 K bytes
External clock input frequency
16 MHz
25 MHz
M37702S1AFP
M37702S1BFP
External
External
16 MHz
25 MHz
APPLICATION
Control devices for office equipment such as copiers, printers,
typewriters, facsimiles, word processors, and personal computers
Control devices for industrial equipment such as ME, NC, communication and measuring instruments.
NOTE
Refer to “Chapter 5 PRECAUTIONS” when using this microcomputer.
FEATURES
The M37702M2AXXXFP and M37702S1AFP satisfy the timing
requirements and the switching characteristics of the former
M37702M2-XXXFP and M37702S1FP.
• Number of basic instructions ..................................................103
• Memory size
ROM ................................................ 16 K bytes
RAM ................................................. 512 bytes
• Instruction execution time
M37702M2AXXXFP, M37702S1AFP
(The fastest instruction at 16 MHz frequency) .................. 250 ns
41
42
44
43
45
47
46
49
48
50
51
52
53
56
54
55
59
57
58
61
60
63
62
64
P84/CTS1/RTS1
P85/CLK1
P86/RXD1
P87/TXD1
P00/A0
P01/A1
P02/A2
P03/A3
P04/A4
P05/A5
P06/A6
P07/A7
P10/A8/D8
P11/A9/D9
P12/A10/D10
P13/A11/D11
P14/A12/D12
P15/A13/D13
P16/A14/D14
P17/A15/D15
P20/A16/D0
P21/A17/D1
P22/A18/D2
P23/A19/D3
PIN CONFIGURATION (TOP VIEW)
P83/TXD0
P82/RXD0
P81/CLK0
65
40
66
39
67
38
P80/CTS0/RTS0
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/ADTRG
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
68
32
P24/A20/D4
P25/A21/D5
P26/A22/D6
P27/A23/D7
P30/R/W
P31/BHE
P32/ALE
P33/HLDA
Vss
31
E
30
29
XOUT
XIN
77
28
RESET
78
27
79
26
80
25
CNVSS
BYTE
P40/HOLD
37
34
24
23
20
22
21
19
33
18
17
16
15
7
6
5
4
3
1
36
35
P70/AN0
P67/TB2IN
P66/TB1IN
P65/TB0IN
P64/INT2
P63/INT1
P62/INT0
P61/TA4IN
P60/TA4OUT
P57/TA3IN
P56/TA3OUT
P55/TA2IN
P54/TA2OUT
P53/TA1IN
P52/TA1OUT
P51/TA0IN
P50/TA0OUT
P47/DBC✽
P46/VPA✽
P45/VDA✽
P44/QCL✽
P43/MX✽
P42/ φ1
P41/RDY
2
76
12
75
14
74
13
73
10
72
9
71
11
70
8
M37702M2AXXXFP
or
M37702M2BXXXFP
or
M37702S1AFP
or
M37702S1BFP
69
Outline 80P6N-A
✽ : Used in the evaluation chip mode only
2
Clock Generating Circuit
30
74 75 76 77 78 79 80 1
Input/Output
port P7
61 62 63 64 65 66 67 68
Input/Output
port P8
Arithmetic Logic
Unit(16)
P7(8)
Accumulator B(16)
P8(8)
Index Register X(16)
512 Bytes
69
(5V)
VCC
Timer TB0(16)
Input/Output
port P5
Input/Output
port P4
Program Bank Register PG(8)
Input/Output
port P6
Input/Output
port P3
Program Address Register PA(24)
Input/Output
port P2
37 38 39 40 41 42 43 44
P1(8)
Input/Output
port P1
45 46 47 48 49 50 51 52
Incrementer(24)
33 34 35 36
71
Reference
voltage input
VREF
Input/Output
port P0
26
Bus width
selection input
BYTE
53 54 55 56 57 58 59 60
P0(8)
Instruction Register(8)
Instruction Queue Buffer Q2(8)
18 19 20 21 22 23 24 25
P2(8)
70
(5V)
AVCC
Instruction Queue Buffer Q0(8)
10 11 12 13 14 15 16 17
Program Counter PC(16)
P3(4)
72
(0V)
AVSS
Data Buffer DBH(8)
2 3 4 5 6 7 8 9
Incrementer/Decrementer(24)
A-D Converter(8)
Data Address Register DA(24)
P4(8)
Timer TB1(16)
Timer TA0(16)
27
(0V)
CNVss
Address Bus
P5(8)
UART0(9)
Timer TB2(16)
Timer TA1(16)
32 73
(0V)
VSS
Data Buffer DBL(8)
P6(8)
UART1(9)
Watchdog Timer
Timer TA2(16)
Input Buffer Register IB(16)
Timer TA3(16)
Stack Pointer S(16)
16K Bytes
Index Register Y(16)
Timer TA4(16)
28
RESET
Reset input
Direct Page Register DPR(16)
RAM
31
E
Enable output
Processor Status Register PS(11)
ROM
29
Clock input Clock output
XIN
XOUT
M37702M2AXXXFP BLOCK DIAGRAM
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data Bus(Odd)
Data Bus(Even)
Instruction Queue Buffer Q1(8)
Data Bank Register DT(8)
Accumulator A(16)
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FUNCTIONS OF M37702M2AXXXFP
Parameter
Number of basic instructions
Instruction execution time
Memory size
Input/Output ports
Multi-function timers
M37702M2AXXXFP, M37702S1AFP
M37702M2BXXXFP, M37702S1BFP
ROM
RAM
P0 – P2, P4 – P8
250 ns (the fastest instruction at external clock 16 MHz frequency)
160 ns (the fastest instruction at external clock 25 MHz frequency)
16 K bytes
512 bytes
8-bit ✕ 8
P3
TA0, TA1, TA2, TA3, TA4
TB0, TB1, TB2
4-bit ✕ 1
16-bit ✕ 5
16-bit ✕ 3
(UART or clock synchronous serial I/O) ✕ 2
Serial I/O
A-D converter
8-bit ✕ 1 (8 channels)
12-bit ✕ 1
3 external types, 16 internal types
(Each interrupt can be set the priority levels to 0 – 7.)
Built-in (externally connected to a ceramic resonator or quartz
crystal resonator)
5 V ± 10%
60 mW (at external clock 16 MHz frequency)
Watchdog timer
Interrupts
Clock generating circuit
Supply voltage
Power dissipation
Input/Output characteristic
Memory expansion
Operating temperature range
Device structure
Package
Functions
103
Input/Output voltage
Output current
5V
5 mA
Maximum 16 M bytes
–20 – 85°C
CMOS high-performance silicon gate process
80-pin plastic molded QFP
3
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin
Name
Input/Output
Functions
VCC, VSS
Power supply
Supply 5 V ± 10% to VCC and 0V to VSS.
CNVSS
CNVSS input
Input
This pin controls the processor mode. Connect to VSS for single-chip mode, and
to VCC for external ROM types.
RESET
Reset input
Input
To enter the reset state, this pin must be kept at a “L” condition which should be
maintained for the required time.
XIN
Clock input
Input
XOUT
Clock output
Output
These are I/O pins of internal clock generating circuit. Connect a ceramic or quartz
crystal resonator between XIN and XOUT. When an external clock is used, the clock
source should be connected to the XIN pin and the XOUT pin should be left open.
E
Enable output
Output
Data or instruction read and data write are performed when output from this pin
is “L”.
BYTE
Bus width selection
input
Input
In memory expansion mode or microprocessor mode, this pin determines
whether the external data bus is 8-bit width or 16-bit width. The width is 16 bits
when “L” signal inputs and 8 bits when “H” signal inputs.
AVCC,
AVSS
Analog supply input
VREF
Reference voltage
input
P00 – P07
I/O port P0
I/O
In single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register
is available so that each pin can be programmed for input or output. These ports
are in input mode when reset.
Address (A7 – A0) is output in memory expansion mode or microprocessor mode.
P10 – P17
I/O port P1
I/O
In single-chip mode, these pins have the same functions as port P0. When the
BYTE pin is set to “L” in memory expansion mode or microprocessor mode and
external
_ data bus is 16-bit width, high-order data (D15 – D 8 ) is
_ input or output
when E output is “L” and an address (A15 – A8) is output when E output is “H”.
If the BYTE pin is “H” that is an external data bus is 8-bit width, only address
(A15 – A8) is output.
P20 – P27
I/O port P2
I/O
In single-chip mode, these pins have the same functions as port P0. In memory
expansion mode
or microprocessor mode low-order data (D7 – D0) is _input or
_
output when E output is “L” and an address (A23 – A16) is output when E output
is “H”.
P30 – P37
I/O port P3
I/O
In single-chip mode, these pins have the same__functions
as port P0.
In memory
____
_____
expansion mode or microprocessor mode, R/W, BHE, ALE and HLDA signals
are output.
P40 – P47
I/O port P4
I/O
In single-chip mode, these pins have the same functions as port_____
P0. In memory
____
expansion mode or microprocessor mode, P40 and P41 become HOLD and RDY
input pin respectively. Functions of other pins are the same as in single-chip
mode. In single-chip mode or memory expansion mode, port P4 2 can be programmed for φ 1 output pin divided the clock to XIN pin by 2. In microprocessor
mode. P42 always has the function as φ1 output pin.
P50 – P57
I/O port P5
I/O
In addition to having the same functions as port P0 in single-chip mode, these
pins also function as I/O pins for timer A0, timer A1, timer A2 and timer A3.
P60 – P67
I/O port P6
I/O
______
_
Power supply for the A-D converter. Connect AVCC to V CC and AV SS to V SS
externally.
Input
This is reference voltage input pin for the A-D converter.
In addition to having the same functions as port P0 in single-chip
mode,
these
____
____
pins also function as I/O pins for timer A4, external interrupt input INT0, INT1 and
INT2 pins, and input pins for timer B0, timer B1 and timer B2.
____
4
P70 – P77
I/O port P7
I/O
In addition to having the same functions as port P0 in single-chip mode, these
pins also function as analog input AN0 – AN7 input pins. P7 7 also has an A-D
conversion trigger input function.
P80 – P87
I/O port P8
I/O
In addition to having the same functions
as____
port P0 in single-chip mode, these
____
pins also function as RXD, TXD, CLK, CTS/RTS pins for UART 0 and UART 1.
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37702M2AXXXFP contains the following devices on a
single chip: ROM and RAM for storing instructions and data, CPU
for processing, bus interface unit (which controls instruction
prefetch and data read/write between CPU and memory), timers,
UART, A-D converter, and other peripheral devices such as I/O
ports. Each of these devices are described below.
MEMORY
The memory map is shown in Figure 1. The address space is 16
M bytes from addresses 016 to FFFFFF16. The address space is
divided into 64 K bytes units called banks. The banks are numbered from 016 to FF16.
Built-in ROM, RAM and control registers for built-in peripheral devices are assigned to bank 016.
00000016
The 16 K bytes area from addresses C00016 to FFFF 16 is the
built-in ROM. Addresses FFD616 to FFFF16 are the RESET and
interrupt vector addresses and contain the interrupt vectors. Refer
to the section on interrupts for details.
The 512 bytes area from addresses 8016 to 27F 16 contains the
built-in RAM. In addition to storing data, the RAM is used as stack
during a subroutine call, or interrupts.
Assigned to addresses 016 to 7F16 are peripheral devices such as
I/O ports, A-D converter, UART, timer, and interrupt control registers.
A 256 bytes direct page area can be allocated anywhere in bank
016 using the direct page register DPR. In direct page addressing
mode, the memory in the direct page area can be accessed with
two words thus reducing program steps.
00000016
00007F 16
00008016
00000016
Peripheral devices
control registers
Bank 0 16
see Fig. 2 for
further information
Internal RAM
512 bytes
00FFFF16
01000016
00007F 16
00027F 16
Bank 1 16
Interrupt vector table
00FFD6 16
A-D conversion
UART1 transmission
01FFFF16
UART1 receive
• • • • • • • • • •
UART0 transmission
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
FE000016
00C00016
Timer A1
Timer A0
Bank FE 16
INT2
Internal ROM
16K bytes
INT1
INT0
FEFFFF 16
FF000016
Watchdog timer
DBC
00FFD616
Bank FF 16
BRK instruction
Zero divide
FFFFFF 16
00FFFF 16
00FFFE16
RESET
Fig. 1 Memory map
5
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation)
000000
000001
000002 Port P0
000003 Port P1
000004 Port P0 data direction register
000005 Port P1 data direction register
000006 Port P2
000007 Port P3
000008 Port P2 data direction register
000009 Port P3 data direction register
00000A Port P4
00000B Port P5
00000C Port P4 data direction register
00000D Port P5 data direction register
00000E Port P6
00000F Port P7
000010 Port P6 data direction register
000011 Port P7 data direction register
000012 Port P8
000013
000014 Port P8 data direction register
000015
000016
000017
000018
000019
00001A
00001B
00001C
00001D
00001E A-D control register
00001F A-D sweep pin selection register
000020 A-D register 0
000021
000022 A-D register 1
000023
000024 A-D register 2
000025
000026 A-D register 3
000027
000028 A-D register 4
000029
00002A A-D register 5
00002B
00002C A-D register 6
00002D
00002E A-D register 7
00002F
000030 UART 0 transmit/receive mode register
000031 UART 0 bit rate generator
000032
UART 0 transmission buffer register
000033
000034 UART 0 transmit/receive control register 0
000035 UART 0 transmit/receive control register 1
000036
UART 0 receive buffer register
000037
000038 UART 1 transmit/receive mode register
000039 UART 1 bit rate generator
00003A
UART 1 transmission buffer register
00003B
00003C UART 1 transmit/receive control register 0
00003D UART 1 transmit/receive control register 1
00003E
UART 1 receive buffer register
00003F
Address (Hexadecimal notation)
Fig. 2 Location of peripheral devices and interrupt control registers
6
000040
000041
000042
000043
000044
000045
000046
000047
000048
000049
00004A
00004B
00004C
00004D
00004E
00004F
000050
000051
000052
000053
000054
000055
000056
000057
000058
000059
00005A
00005B
00005C
00005D
00005E
00005F
000060
000061
000062
000063
000064
000065
000066
000067
000068
000069
00006A
00006B
00006C
00006D
00006E
00006F
000070
000071
000072
000073
000074
000075
000076
000077
000078
000079
00007A
00007B
00007C
00007D
00007E
00007F
Count start flag
One-shot start flag
Up-down flag
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Processor mode register
Watchdog timer
Watchdog timer frequency selection flag
A-D conversion interrupt control register
UART 0 transmission interrupt control register
UART 0 receive interrupt control register
UART 1 transmission interrupt control register
UART 1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CENTRAL PROCESSING UNIT (CPU)
The CPU has ten registers and is shown in Figure 3. Each of
these registers is described below.
ACCUMULATOR A (A)
Accumulator A is the main register of the microcomputer. It consists of 16 bits and the lower 8 bits can be used separately. The
data length flag m determines whether the register is used as 16bit register or as 8-bit register. It is used as a 16-bit register when
flag m is “0” and as an 8-bit register when flag m is “1”. Flag m is
a part of the processor status register (PS) which is described
later.
Data operations such as calculations, data transfer, input/output,
etc., is executed mainly through the accumulator.
ACCUMULATOR B (B)
Accumulator B has the same functions as accumulator A, but the
use of accumulator B requires more instruction bytes and execution cycles than accumulator A.
INDEX REGISTER X (X)
Index register X consists of 16 bits and the lower 8 bits can be
used separately. The index register length flag x determines
whether the register is used as 16-bit register or as 8-bit register.
It is used as a 16-bit register when flag x is “0” and as an 8-bit reg-
ister when flag x is “1”. Flag x is a part of the processor status register (PS) which is described later.
In index addressing mode, register X is used as the index register
and the contents of this address is added to obtain the real address.
Also, when executing a block transfer instruction MVP or MVN, the
contents of index register X indicate the low-order 16 bits of the
source data address. The third byte of the MVP and MVN is the
high-order 8 bits of the source data address.
INDEX REGISTER Y (Y)
Index register Y consists of 16 bits and the lower 8 bits can be
used separately. The index register length flag x determines
whether the register is used as 16-bit register or as 8-bit register.
It is used as a 16-bit register when flag x is “0” and as an 8-bit register when flag x is “1”. Flag x is a part of the processor status
register (PS) which is described later.
In index addressing mode, register Y is used as the index register
and the contents of this address is added to obtain the real address.
Also, when executing a block transfer instruction MVP or MVN, the
contents of index register Y indicate the low-order 16 bits of the
destination address. The second byte of the MVP and MVN is the
high-order 8 bits of the destination data address.
15
7
AH
0
Accumulator A
AL
15
7
BH
0
Accumulator B
BL
15
7
XH
0
XL
15
7
YH
Index register X
0
YL
15
Index register Y
0
Stack pointer S
S
7
15
0
15
0
DT
Program counter PC
PC
Program bank register PG
PG
7
0
0
Direct page register DPR
DPR
Data bank register DT
15
0 0 0 0 0
7
IPL2 IPL1 IPL0
0
N V m x D I Z C
Processor status register PS
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Index register length flag
Data length flag
Overflow flag
Negative flag
Processor interrupt priority level IPL
Fig. 3 Register structure
7
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STACK POINTER (S)
PROCESSOR STATUS REGISTER (PS)
Stack pointer (S) is a 16-bit register. It is used during a subroutine
call or interrupts. It is also used during stack, stack pointer relative, or stack pointer relative indirect indexed Y addressing mode.
Processor status register (PS) is an 11-bit register. It consists of a
flag to indicate the result of operation and CPU interrupt levels.
Branch operations can be performed by testing the flags C, Z, V,
and N.
The details of each processor status register bit are described
below.
PROGRAM COUNTER (PC)
Program counter (PC) is a 16-bit counter that indicates the low-order 16-bits of the next program memory address to be executed.
There is a bus interface unit between the program memory and
the CPU, so that the program memory is accessed through bus interface unit. This is described later.
PROGRAM BANK REGISTER (PG)
Program bank register is an 8-bit register that indicates the highorder 8 bits of the next program memory address to be executed.
When a carry occurs by incrementing the contents of the program
counter, the contents of the program bank register (PG) is
incremented by 1. Also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the
program counter (PC) using branch instruction, the contents of the
program bank register (PG) is incremented or decremented by 1
so that programs can be written without worrying about bank
boundaries.
DATA BANK REGISTER (DT)
Data bank register (DT) is an 8-bit register. With some addressing
modes, a part of the data bank register (DT) is used to specify a
memory address. The contents of data bank register (DT) is used
as the high-order 8 bits of a 24-bit address. Addressing modes
that use the data bank register (DT) are direct indirect, direct indexed X indirect, direct indirect indexed Y, absolute, absolute bit,
absolute indexed X, absolute indexed Y, absolute bit relative, and
stack pointer relative indirect indexed Y.
DIRECT PAGE REGISTER (DPR)
Direct page register (DPR) is a 16-bit register. Its contents is used
as the base address of a 256-byte direct page area. The direct
page area is allocated in bank 0, but when the contents of DPR is
FF0116 or greater, the direct page area spans across bank 016 and
bank 116. All direct addressing modes use the contents of the direct page register (DPR) to generate the data address. If the
low-order 8 bits of the direct page register (DPR) is “0016”, the
number of cycles required to generate an address is minimized.
Normally the low-order 8 bits of the direct page register (DPR) is
set to “0016”.
8
1. Carry flag (C)
The carry flag contains the carry or borrow generated by the ALU
after an arithmetic operation. This flag is also affected by shift and
rotate instructions. This flag can be set and reset directly with the
SEC and CLC instructions or with the SEP and CLP instructions.
2. Zero flag (Z)
This zero flag is set if the result of an arithmetic operation or data
transfer is zero and reset if it is not. This flag can be set and reset directly with the SEP and CLP instructions.
3. Interrupt disable flag (I)
When the interrupt
disable flag is set to “1”, all interrupts except
____
watchdog timer, DBC, and software interrupt are disabled. This
flag is set to “1” automatically when there is an interrupt. It can be
set and reset directly with the SEI and CLI instructions or SEP and
CLP instructions.
4. Decimal mode flag (D)
The decimal mode flag determines whether addition and subtraction are performed as binary or decimal. Binary arithmetic is
performed when this flag is “0”. If it is “1”, decimal arithmetic is
performed with each word treated as two or four digit decimal.
Arithmetic operation is performed using four digits when the data
length flag m is “0” and with two digits when it is “1”. (Decimal operation is possible only with the ADC and SBC instructions.) This
flag can be set and reset with the SEP and CLP instructions.
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5. Index register length flag (x)
9. Processor interrupt priority level (IPL)
The index register length flag determines whether index register X
and index register Y are used as 16-bit registers or as 8-bit registers. The registers are used as 16-bit registers when flag x is “0”
and as 8-bit registers when it is “1”. This flag can be set and reset
with the SEP and CLP instructions.
The processor interrupt priority level (IPL) consists of 3 bits and
determines the priority of processor interrupts from level 0 to level
7. Interrupt is enabled when the interrupt priority of the device requesting interrupt (set using the interrupt control register) is higher
than the processor interrupt priority. When interrupt is enabled, the
current processor interrupt priority level is saved in a stack and the
processor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. Refer to the section
on interrupts for more details.
6. Data length flag (m)
The data length flag determines whether the data length is 16-bit
or 8-bit. The data length is 16-bit when flag m is “0” and 8-bit when
it is “1”. This flag can be set and reset with the SEM and CLM instructions or with the SEP and CLP instructions.
7. Overflow flag (V)
The overflow flag has meaning when addition or subtraction is
performed a word as signed binary number. When the data length
flag m is “0”, the overflow flag is set when the result of addition or
subtraction is outside the range between –32768 and +32767.
When the data length flag m is “1”, the overflow flag is set when
the result of addition or subtraction is outside the range between
–128 and +127. It is reset in all other cases. The overflow flag can
also be set and reset directly with the SEP, and CLV or CLP instructions.
8. Negative flag (N)
BUS INTERFACE UNIT
The CPU operates on an internal clock frequency which is obtained by dividing the external clock frequency f(XIN) by two. This
frequency is twice the bus cycle frequency. In order to speed-up
processing, a bus interface unit is used to pre-fetch instructions
when the data bus is idle. The bus interface unit synchronizes the
CPU and the bus and pre-fetches instructions. Figure 4 shows the
relationship between the CPU and the bus interface unit. The bus
interface unit has a program address register, a 3-byte instruction
queue buffer, a data address register, and a 2-byte data buffer.
The bus interface unit obtains an instruction code from memory
and stores it in the instruction queue buffer, obtains data from
memory and stores it in the data buffer, or writes the data from the
data buffer to the memory.
The negative flag is set when the result of arithmetic operation or
data transfer is negative (If data length flag m is “0”, when data bit
15 is “1”. If data length flag m is “1”, when data bit 7 is “1”.) It is reset in all other cases. It can also be set and reset with the SEP
and CLP instructions.
D'15 to D'8
D15 to D8
D'7 to D' 0
D7 to D0
A'23 to A' 0
A23 to A0
Bus interface
unit
CPU
BHE
R/W
E
Control signal
ALE
BYTE
HOLD
Fig. 4 Relationship between the CPU and the bus interface unit
9
MITSUBISHI MICROCOMPUTERS
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The bus interface unit operates using one of the waveforms (1) to
(6) shown in Figure 5. The standard waveforms are (1) and (2).
The ALE signal is used to latch only the address signal from the
multiplexed
signal containing data and address.
_
The E signal becomes “L” when the bus interface unit reads an instruction code or data from memory or when it writes data __
to
memory. Whether to perform read or write
is controlled by the R/W
__
signal. Read is performed when the R/W signal is “H” state and
write is performed when it is “L” state.
Waveform (1) in Figure 5 is used to access a single byte or two
bytes simultaneously. To read or write two bytes simultaneously,
the first address accessed must be even. Furthermore, when accessing an external memory area in memory expansion mode or
microprocessor mode, set the bus width selection input pin BYTE
to “L”. (external data bus width to 16 bits) The internal memory
area is always treated as 16-bit bus width regardless of BYTE.
When performing 16-bit data read or write, if the conditions for simultaneously accessing two bytes are not satisfied, waveform (2)
is used to access each byte one by one.
However, when prefetching the instruction code, if the address of
the instruction code is odd, waveform (1) is used, and only one
byte is read in the instruction
queue buffer.
____
The signals A0 and BHE in Figure 5 are used to control these
cases: 1-byte read from even address, 1-byte read from odd address, 2-byte simultaneous read from even and odd addresses,
1-byte write to even address, 1-byte write to odd address, or 2byte simultaneous write to even and odd addresses. The A0 signal
that is the address
bit 0 is “L” when an even number address is
____
accessed. The BHE signal becomes “L” when an odd number address is accessed.
The bit 2 of processor mode register (address
5E16) is the wait bit.
_
When this bit is set to “0”, the “L” width of E signal is 2 times as
long when accessing an external memory area in memory expan_
sion mode or microprocessor mode. However, the “L” width of E
signal is not extended when an internal memory
area is accessed.
_
When the wait bit is “1”, the “L” width of E signal is not extended
_
for any access. Waveform (3) is an expansion of the “L” width of E
signal in waveform (1).
Waveform (4), (5), and (6) are expansion
_
of each “L” width of E signal in waveform (2), first half of waveform
(2), and the last half of waveform (2) respectively.
Instruction code read, data read, and data write are described below.
Internal clock φ
Port P2
A
D
A
D
E
(1)
ALE
Port P2
A +1
D
E
(2)
ALE
Port P2
(3)
A
D
A
D
A +1
A
D
A +1
E
ALE
Port P2
(4)
D
E
ALE
Port P2
D
E
(5)
ALE
A
Port P2
(6)
D
A +1
D
E
ALE
A : Address
D : Data
These waveforms are at the memory expansion mode and
the microprocessor mode.
Access
method
Signal
A0
BHE
Access 2-byte Access even
Access odd
simultaneously address 1-byte address 1-byte
“L”
“L”
“L”
“H”
“H”
“L”
Fig. 5 Relationship
between access method and signals A 0
____
and BHE
10
MITSUBISHI MICROCOMPUTERS
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M37702S1AFP, M37702S1BFP
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Instruction code read will be described first.
The CPU obtains instruction codes from the instruction queue
buffer and executes them. The CPU notifies the bus interface unit
that it is requesting an instruction code during an instruction code
request cycle. If the requested instruction code is not yet stored in
the instruction queue buffer, the bus interface unit halts the CPU
until it can store more instructions than requested in the instruction
queue buffer.
Even if there is no instruction code request from the CPU, the bus
interface unit reads instruction codes from memory and stores
them in the instruction queue buffer when the instruction queue
buffer is empty or when only one instruction code is stored and the
bus is idle on the next cycle.
This is referred to as instruction pre-fetching.
Normally, when reading an instruction code from memory, if the
accessed address is even the next odd address is read together
with the instruction code and stored in the instruction queue buffer.
However, in memory expansion mode or microprocessor mode, if
the bus width switching pin BYTE is “H”, external data bus width is
8 bits and the address to be read is in external memory area is
odd, only one byte is read and stored in the instruction queue
buffer. Therefore, waveform (1) or (3) in Figure 5 is used for instruction code read.
Data read and write are described below.
The CPU notifies the bus interface unit when performing data read
or write. At this time, the bus interface unit halts the CPU if the bus
interface unit is already using the bus or if there is a request with
higher priority. When data read or write is enabled, the bus interface unit uses one of the waveforms from (1) to (6) in Figure 5 to
perform the operation.
During data read, the CPU waits until the entire data is stored in
the data buffer. The bus interface unit sends the address received
from_the CPU to the address bus. Then it reads the memory when
the E signal is “L” and stores the result in the data buffer.
During data write, the CPU writes the data in the data buffer and
the bus interface unit writes it to memory. Therefore, the CPU can
proceed to the next step without waiting for write to complete. The
bus interface unit sends the address
received from the CPU to the
_
address bus. Then when the E signal is “L”, the bus interface unit
sends the data in the data buffer to the data bus and writes it to
memory.
11
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INTERRUPTS
Table 1. Interrupt types and the interrupt vector addresses
Table 1 shows the interrupt types and the corresponding interrupt
vector addresses. Reset is also treated
as a type of interrupt and
____
is discussed in this section, too. DBC is an interrupt used during
debugging.
____
Interrupts other than reset, DBC, watchdog timer, zero divide, and
BRK instruction all have interrupt control registers. Table 2 shows
the addresses of the interrupt control registers and Figure 6 shows
the bit configuration of the interrupt control register.
Use the SEB and CLB instructions when setting each interrupt
control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt.
____
Also, interrupt request bits other than DBC and watchdog timer
can
be cleared
by software.
____
____
INT2 to INT0 are external interrupts and whether to cause an interrupt at the input level (level sense) or at the edge (edge sense)
can be selected with the level sense/edge sense selection bit. Furthermore, the polarity of the interrupt input can be selected with
polarity selection bit.
Timer and UART interrupts are described in the respective section. The priority of interrupts when multiple interrupts are caused
simultaneously is partially fixed by hardware, but, it can also be
adjusted by software as shown in Figure 7. The hardware priority
is fixed ____
the following:
reset > DBC > watchdog timer > other interrupts
Interrupts
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Vector addresses
00FFD616 00FFD716
00FFD816 00FFD916
00FFDA16 00FFDB16
00FFDC16 00FFDD16
00FFDE16
00FFE016
00FFDF16
00FFE116
00FFE216
00FFE416
00FFE316
00FFE516
00FFE616
00FFE816
00FFEA16
00FFE716
00FFE916
00FFEB16
00FFEC16
00FFEE16
00FFED16
00FFEF16
00FFF016
00FFF216
00FFF416
00FFF616
00FFF116
00FFF316
00FFF516
00FFF716
DBC (unusable)
Break instruction
00FFF816
00FFFA16
00FFF916
00FFFB16
Zero divide
Reset
00FFFC16
00FFFD16
00FFFE16
00FFFF16
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
____
INT2 external interrupt
____
INT1 external interrupt
____
INT0 external interrupt
Watchdog timer
____
7 6 5 4 3 2 1 0
Interrupt priority
Interrupt request bit
0 : No interrupt
1 : Interrupt
Interrupt control register configuration for A-D converter, UART0, UART1, timer A0 to timer A4, and
timer B0 to timer B2
7 6 5 4 3 2 1 0
Interrupt priority
Interrupt request bit
0 : No interrupt
1 : Interrupt
Polarity selection bit
0 : Set interrupt request bit at “H” level for level sense and when changing
from “H” to “L” level for edge sense.
1 : Set interrupt request bit at “L” level for level sense and when changing
from “L” to “H” level for edge sense.
Level sense/edge sense selection bit
0 : Edge sense
1 : Level sense
Interrupt control register configuration for INT2 to INT0.
Fig. 6 Interrupt control register configuration
12
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Table 2. Addresses of interrupt control registers
Interrupt control registers
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
Addresses
00007016
00007116
00007216
➃
4
00007516
00007616
00007716
3
➂
2
1
Watchdog
timer
DBC
Reset
00007816
00007916
A-D converter, UART, Timer, INT interrupts
00007A16
00007B16
Priority can be changed with software inside 4
INT0 interrupt control register
____
INT1 interrupt control register
INT2 interrupt control register
00007F16
____
Priority is determined by hardware
00007316
00007416
00007C16
00007D16
00007E16
____
Because priority resolution takes some time, no sampling pulse is
generated for a certain interval even if it is the next operation code
fetch cycle.
Fig. 7 Interrupt priority
Level 0
Interrupts caused by a BRK instruction and when dividing by zero
are software interrupts and are not included in this list.
Other interrupts previously mentioned are A-D converter, UART,
Timer, INT interrupts. The priority of these interrupts can be
changed by changing the priority level in the corresponding interrupt control register by software.
Figure 8 shows a diagram of the interrupt priority resolution circuit.
When an interrupt is caused, the each interrupt device compares
its own priority with the priority from above and if its own priority is
higher, then it sends the priority below and requests the interrupt.
If the priorities are the same, the one above has priority.
This comparison is repeated to select the interrupt with the highest
priority among the interrupts that are being requested. Finally the
selected interrupt is compared with the processor interrupt priority
level (IPL) contained in the processor status register (PS) and the
request is accepted if it is higher than IPL and the interrupt disable
flag I is “0”. The request is not accepted if flag I is “1”. The reset,
____
DBC, and watchdog timer interrupts are not affected by the interrupt disable flag I.
When an interrupt is accepted, the contents of the processor status register (PS) is saved to the stack and the interrupt disable
flag I is set to “1”.
Furthermore, the interrupt request bit of the accepted interrupt is
cleared to “0” and the processor interrupt priority level (IPL) in the
processor status register (PS) is replaced by the priority level of
the accepted interrupt.
Therefore, multi-level priority interrupts are possible by resetting
the interrupt
disable flag I to “0” and enable further interrupts.
____
For reset, DBC, watchdog timer, zero divide, and BRK instruction
interrupts, which do not have an interrupt control register, the processor interrupt level (IPL) is set as shown in Table 3.
Priority resolution is performed by latching the interrupt request bit
and interrupt priority level so that they do not change. They are
sampled at the first half and latched at the last half of the operation code fetch cycle.
A-D conversion
Interrupt request
UART1 transmit
UART1 receive
UART0 transmit
Reset
UART0 receive
Timer B2
Timer B1
DBC
Timer B0
Timer A4
Timer A3
Watchdog
timer
Timer A2
Timer A1
Interrupt disable flag I
Timer A0
INT2
IPL
INT1
INT0
Fig. 8 Interrupt priority resolution
13
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As shown in Figure 9, there are three different interrupt priority
resolution time from which one is selected by software. After the
selected time has elapsed, the highest priority is determined and
is processed after the currently executing instruction has been
completed.
The time is selected with bits 4 and 5 of the processor mode register (address 5E 16) shown in Figure 10. Table 4 shows the
relationship between these bits and the number of cycles. After a
reset, the processor mode register is initialized to “00 16” and
therefore, the longest time is selected.
However, the shortest time should be selected by software.
Table 3. Value set in processor interrupt level (IPL) during an
interrupt
Interrupt types
Reset
____
DBC
Watchdog timer
Zero divide
BRK instruction
Setting value
0
7
7
Not change value of IPL.
Not change value of IPL.
Table 4. Relationship between priority level resolution time
selection bit and number of cycles
Priority level resolution time selection bit
Bit 5
Bit 4
0
0
0
1
1
0
φ : internal clock
Internal clock φ
Operation code fetch cycle
Sampling pulse
Priority resolution time
0
Select from 0 to 2 with bits
4 and 5 of the processor
mode register
1
2
Fig. 9 Interrupt priority resolution time
7
6
5
4
3
0
2
1
0
Processor mode register (5E 16)
Processor mode bits
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Evaluation chip mode
Wait bit
0 : Wait
1 : No wait
Software reset bit
The processor is reset when this bit is set to “1” .
Priority resolution time selection bits
0 0 : Select 0 in Figure 9
0 1 : Select 1 in Figure 9
1 0 : Select 2 in Figure 9
Test mode bit
Must be “0”
Clock φ1 output selection bit
0 : No φ1 output
1 : φ1 output
Fig. 10 Processor mode register configuration
14
Number of cycles
7 cycles of φ
4 cycles of φ
2 cycles of φ
MITSUBISHI MICROCOMPUTERS
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TIMER
(1) Timer mode [00]
There are eight 16-bit timers. They are divided by type into timer A
(5) and timer B (3).
The timer I/O pins are shared with I/O pins for port P5 and P6. To
use these pins as timer input pins, the data direction register bit
corresponding to the pin must be cleared to “0” to specify input
mode.
Figure 12 shows the bit configuration of the timer Ai mode register
during timer mode. Bits 0, 1, and 5 of the timer Ai mode register
must always be “0” in timer mode.
Bit 3 is ignored if bit 4 is “0”.
Bits 6 and 7 are used to select the timer counter source.
The counting of the selected clock starts when the count start flag
is “1” and stops when it is “0”.
Figure 13 shows the bit configuration of the count start flag. The
counter is decremented, an interrupt is caused and the interrupt
request bit in the timer Ai interrupt control register is set when the
contents becomes 000016. At the same time, the contents of the
reload register is transferred to the counter and count is continued.
TIMER A
Figure 11 shows a block diagram of timer A.
Timer A has four modes; timer mode, event counter mode, oneshot pulse mode, and pulse width modulation mode. The mode is
selected with bits 0 and 1 of the timer Ai mode register (i = 0 to 4).
Each of these modes is described below.
f2
f(X IN )
1/2
f16
1/8
f32
1/2
f64
1/2
f512
1/8
Data bus (odd)
Data bus (even)
(Lower 8 bits)
Clock source selection
f2
f16
f64
f512
• Timer
• One-shot
• Pulse width modulation
(Higher 8 bits)
Reload register(16)
Timer (gate function)
Counter(16)
Up/Down
Polarity
selection
TAi IN
Event counter
Count start flag
(4016)
(i = 0 – 4)
External trigger
Down count
Always decremented
except in event count mode
Addresses
Timer A0 47 16 4616
Timer A1 49 16 4816
Timer A2 4B16 4A16
Timer A3 4D 16 4C16
Timer A4 4F16 4E16
Up-down flag
(44 16)
Pulse output
Toggle flip-flop
TAi OUT
(i = 0 – 4)
Fig. 11 Block diagram of timer A
15
MITSUBISHI MICROCOMPUTERS
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When bit 2 of the timer Ai mode register is “1”, the output is generated from TAiOUT pin. The output is toggled each time the contents
of the counter reaches to 000016. When the contents of the count
start flag is “0”, “L” is output from TAiOUT pin.
When bit 2 is “0”, TAiOUT can be used as a normal port pin. When
bit 4 is “0”, TAiIN can be used as a normal port pin. When bit 4 is
“1”, counting is performed only while the input signal from the
TAiIN pin is “H” or “L” as shown in Figure 14. Therefore, this can
be used to measure the pulse width of the TAi IN input signal.
Whether to count while the input signal is “H” or while it is “L” is
determined by bit 3. If bit 3 is “1”, counting is performed while the
TAiIN pin input signal is “H” and if bit 3 is “0”, counting is performed
while it is “L”.
Note that the duration of “H” or “L” on the TAiIN pin must be two or
more cycles of the timer count source.
When data is written to timer Ai register with timer Ai halted, the
same data is also written to the reload register and the counter.
When data is written to timer Ai which is busy, the data is written to
the reload register, but not to the counter. The counter is reloaded
with new data from the reload register at the next reload timer. The
contents of the counter can be read at any time.
When the value set in the timer Ai register is n, the timer frequency
dividing ratio is 1/(n + 1).
Addresses
7 6 5 4 3 2 1 0
0
0 0
Timer A0 mode register
56 16
Timer A1 mode register
57 16
Timer A2 mode register
58 16
Timer A3 mode register
59 16
Timer A4 mode register
5A 16
0 0 : Always “00” in timer mode
0 : No pulse output (TAi OUT is normal port pin)
1 : Pulse output
0 ✕ : No gate function (TAi IN is normal port pin)
1 0 : Count only while TAi IN input is “L”
1 1 : Count only while TAi IN input is “H”
0 : Always “0” in timer mode
Clock source selection bit
0 0 : Select f 2
0 1 : Select f 16
1 0 : Select f 64
1 1 : Select f 512
Fig. 12 Timer Ai mode register bit configuration during timer mode
16
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7 6 5 4 3 2 1 0
Count start flag
(Stop at “0”, Start at “1”)
Address
4016
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
Fig. 13 Count start flag bit configuration
Selected clock source f i
TAiN
Timer mode register
Bit 4
Bit 3
1
0
Timer mode register
Bit 4
Bit 3
1
1
Fig. 14 Count waveform when gate function is available
17
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(2) Event counter mode [01]
Figure 15 shows the bit configuration of the timer Ai mode register
during event counter mode. In event counter mode, the bit 0 of the
timer Ai mode register must be “1” and bit 1 and 5 must be “0”.
The input signal from the TAiIN pin is counted when the count start
flag shown in Figure 13 is “1“ and counting is stopped when it
is “0”.
Count is performed at the fall of the input signal when bit 3 is “0”
and at the rise of the signal when it is “1”.
In event counter mode, whether to increment or decrement the
count can be selected with the up-down flag or the input signal
from the TAiOUT pin.
When bit 4 of the timer Ai mode register is “0”, the up-down flag is
used to determine whether to increment or decrement the count
(decrement when the flag is “0” and increment when it is “1”). Figure 16 shows the bit configuration of the up-down flag.
When bit 4 of the timer Ai mode register is “1”, the input signal
from the TAiOUT pin is used to determine whether to increment or
decrement the count. However, note that bit 2 must be “0” if bit 4
is “1” because if bit 2 is “1”, TAiOUT pin becomes an output pin with
pulse output.
The count is decremented when the input signal from the TAiOUT
pin is “L” and incremented when it is “H”. Determine the level of
the input signal from the TAi OUT pin before valid edge is input to
the TAiIN pin.
An interrupt request signal is generated and the interrupt request
bit in the timer Ai interrupt control register is set when the counter
reaches 000016 (decrement count) or FFFF16 (increment count).
At the same time, the contents of the reload register is transferred
to the counter and the count is continued.
When bit 2 is “1” and the counter reaches 0000 16 (decrement
count) or FFFF16 (increment count), the waveform reversing polarity is output from TAiOUT pin.
If bit 2 is “0”, TAi OUT pin can be used as a normal port pin. However, if bit 4 is “1“ and the TAiOUT pin is used as an output pin, the
output from the pin changes the count direction. Therefore, bit 4
should be “0” unless the output from the TAiOUT pin is to be used
to select the count direction.
Addresses
7 6 5 4 3 2 1 0
✕ ✕ 0
0 1
Timer A0 mode register
56 16
Timer A1 mode register
57 16
Timer A2 mode register
58 16
Timer A3 mode register
59 16
Timer A4 mode register
5A 16
0 1 : Always “01” in event counter
mode
0 : No pulse output
1 : Pulse output
0 : Count at the falling edge of input
signal
1 : Count at the rising edge of input
signal
0 : Increment or decrement according
to up-down flag
1 : Increment or decrement according
to TAiOUT pin input signal level
0 : Always “0” in event counter mode
✕ ✕ : Not used in event counter mode
Fig. 15 Timer Ai mode register bit configuration during event
counter mode
Address
7 6 5 4 3 2 1 0
Up-down flag
4416
Timer A0 up-down flag
Timer A1 up-down flag
Timer A2 up-down flag
Timer A3 up-down flag
Timer A4 up-down flag
Timer A2 two-phase pulse signal processing
selection bit
0 : Two-phase pulse signal processing disabled
1 : Two-phase pulse signal processing mode
Timer A3 two-phase pulse signal processing
selection bit
0 : Two-phase pulse signal processing disabled
1 : Two-phase pulse signal processing mode
Timer A4 two-phase pulse signal processing
selection bit
0 : Two-phase pulse signal processing disabled
1 : Two-phase pulse signal processing mode
Fig. 16 Up-down flag bit configuration
18
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data write and data read are performed in the same way as for
timer mode. That is, when data is written to timer Ai halted, it is
also written to the reload register and the counter. When data is
written to timer Ai which is busy, the data is written to the reload
register, but not to the counter. The counter is reloaded with new
data from the reload register at the next reload time. The counter
can be read at any time.
In event counter mode, whether to increment or decrement the
counter can also be determined by supplying two-phase pulse input with phase shifted by 90° to timer A2, A3, or A4. There are two
types of two-phase pulse processing operations. One uses timers
A2 and A3, and the other uses timer A4. In either processing operation, two-phase pulse is input in the same way, that is, pulses
out of phase by 90° are input at the TAjOUT (j = 2 to 4) pin and
TAjIN pin.
When timers A2 and A3 are used, as shown in Figure 17, the
count is incremented when a rising edge is input to the TAk IN pin
after the level of TAkOUT (k = 2, 3) pin changes from “L” to “H”, and
when the falling edge is inserted, the count is decremented.
For timer A4, as shown in Figure 18, when a phase related pulse
with a rising edge input to the TA4IN pin is input after the level of
TA4 OUT pin changes from “L” to “H”, the count is incremented at
the respective rising edge and falling edge of the TA4OUT pin and
TA4IN pin.
When a phase related pulse with a falling edge input to the
TA4OUT pin is input after the level of TA4IN pin changes from “H” to
“L”, the count is decremented at the respective rising edge and
falling edge of the TA4IN pin and TA4 OUT pin. When performing
this two-phase pulse signal processing, timer Aj mode register bit
0 and bit 4 must be set to “1” and bits 1, 2, 3, and 5 must be “0”.
Bits 6 and 7 are ignored. Note that bits 5, 6, and 7 of the up-down
flag register (4416) are the two-phase pulse signal processing selection bit for timer A2, A3, and A4 respectively. Each timer
operates in normal event counter mode when the corresponding
bit is “0” and performs two-phase pulse signal processing when it
is “1”.
Count is started by setting the count start flag to “1”. Data write
and read are performed in the same way as for normal event
counter mode. Note that the direction register of the input port
must be set to input mode because two-phase pulse signal is input. Also, there can be no pulse output in this mode.
Addresses
Timer A2 mode register
58 16
7 6 5 4 3 2 1 0
Timer A3 mode register
59 16
✕ ✕ 0 1 0
Timer A4 mode register
5A 16
0 0 1
0 1 : Always “01” in event counter
mode
0 1 0 0 : Always “0100” when processing
two-phase pulse signal
✕ ✕ : Not used in event counter mode
Fig. 19 Timer Aj mode register bit configuration when performing two-phase pulse signal processing in event
counter mode
TAkOUT
TAkIN
(k = 2, 3)
Increment- Increment- Increment- Decrement- Decrement- Decrementcount
count
count
count
count
count
Fig. 17 Two-phase pulse processing operation of timer A2 and timer A3
TA4OUT
Increment-count at each edge
Decrement-count at each edge
TA4IN
Increment-count at each edge
Decrement-count at each edge
Fig. 18 Two-phase pulse processing operation of timer A4
19
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) One-shot pulse mode [10]
Figure 20 shows the bit configuration of the timer Ai mode register
during one-shot pulse mode. In one-shot pulse mode, bit 0 and bit
5 must be “0” and bit 1 and bit 2 must be “1”.
The trigger is enabled when the count start flag is “1”. The trigger
can be generated by software or it can be input from the TAiIN pin.
Software trigger is selected when bit 4 is “0” and the input signal
from the TAiIN pin is used as the trigger when it is “1”.
Bit 3 is used to determine whether to trigger at the fall of the trigger signal or at the rise. The trigger is at the fall of the trigger
signal when bit 3 is “0” and at the rise of the trigger signal when it
is “1”.
Software trigger is generated by setting the bit in the one-shot
start flag corresponding to each timer.
Figure 21 shows the bit configuration of the one-shot start flag.
As shown in Figure 22, when a trigger signal is received, the
counter counts the clock selected by bits 6 and 7.
If the contents of the counter is not 000016, the TAiOUT pin goes
“H” when a trigger signal is received. The count direction is decrement.
When the counter reaches 000116 , The TAiOUT pin goes “L” and
count is stopped. The contents of the reload register is transferred
to the counter. At the same time, and interrupt request signal is
generated and the interrupt request bit in the timer Ai interrupt
control register is set. This is repeated each time a trigger signal is
received. The output pulse width is
1
pulse frequency of the selected clock
✕ (counter’s value at the time of trigger).
If the count start flag is “0”, TAiOUT goes “L”. Therefore, the value
corresponding to the desired pulse width must be written to timer
Ai before setting the timer Ai count start flag.
As shown in Figure 23, a trigger signal can be received before the
operation for the previous trigger signal is completed. In this case,
the contents of the reload register is transferred to the counter by
the trigger and then that value is decremented.
Except when retriggering while operating, the contents of the reload register is not transferred to the counter by triggering.
When retriggering, there must be at least one timer count source
cycle before a new trigger can be issued.
Data write is performed to the same way as for timer mode. When
data is written in timer Ai halted, it is also written to the reload register and the counter.
When data is written to timer Ai which is busy, the data is written to
the reload register, but not to the counter. The counter is reloaded
with new data from the reload register at the next reload time.
Undefined data is read when timer Ai is read.
20
Addresses
7 6 5 4 3 2 1 0
0
1 1 0
Timer A0 mode register
56 16
Timer A1 mode register
57 16
Timer A2 mode register
58 16
Timer A3 mode register
59 16
Timer A4 mode register
5A 16
1 0 : Always “10” in one-shot
pulse mode
1 : Always “1” in one-shot pulse
mode
0 ✕ : Software trigger
1 0 : Trigger at the falling edge of
TAiIN input
1 1 : Trigger at the rising edge of
TAiIN input
0 : Always “0” in one-shot pulse
mode
Clock source selection
0 0 : Select f 2
0 1 : Select f 16
1 0 : Select f 64
1 1 : Select f 512
Fig. 20 Timer Ai mode register bit configuration during oneshot pulse mode
7 6 5 4 3 2 1 0
Address
One-shot start flag
4216
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
Fig. 21 One-shot start flag bit configuration
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selected
clock source f i
TAiIN
(in case of the
rising edge)
TAiOUT
Example when the contents of the reload register is 000316.
Fig. 22 Pulse output example when external rising edge is selected
Selected
clock source f i
TAiIN
(in case of the
rising edge)
TAiOUT
Example when the contents of the reload register is 000416.
Fig. 23 Example when trigger is re-issued during pulse output
21
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Pulse width modulation mode [11]
Figure 24 shows the bit configuration of the timer Ai mode register
during pulse width modulation mode. In pulse width modulation
mode, bits 0, 1, and 2 must be set to “1”. Bit 5 is used to determine whether to perform 16-bit length pulse width modulator or
8-bit length pulse width modulator. 16-bit length pulse width modulator is performed when bit 5 is “0” and 8-bit length pulse width
modulator is performed when it is “1”. The 16-bit length pulse
width modulator is described first.
The pulse width modulator can be started with a software trigger
or with an input signal from a TAiIN pin (external trigger).
The software trigger mode is selected when bit 4 is “0”. Pulse
width modulator is started and pulse is output from TAiOUT when
the timer Ai start flag is set to “1”.
The external trigger mode is selected when bit 4 is “1”. Pulse width
modulator starts when a trigger signal is input from the TAiIN pin
when the timer Ai start flag is “1”. Whether to trigger at the fall or
rise of the trigger signal is determined by bit 3. The trigger is at the
fall of the trigger signal when bit 3 is “0” and at the rise when it is
“1”.
When data is written to timer Ai with the pulse width modulator
halted, it is written to the reload register and the counter.
Then when the timer Ai start flag is set to “1” and a software trigger or an external trigger is issued to start modulation, the
waveform shown in Figure 25 is output continuously. Once modulation is started, triggers are not accepted. If the value in the
reload register is m, the duration “H” of pulse is
1
✕m
selected clock frequency
and the output pulse period is
1
✕ (216 – 1).
selected clock frequency
An interrupt request signal is generated and the interrupt request
bit in the timer Ai interrupt control register is set at each fall of the
output pulse.
The width of the output pulse is changed by updating timer data.
The update can be performed at any time. The output pulse width
is changed at the rise of the pulse after data is written to the timer.
The contents of the reload register are transferred to the counter
just before the rise of the next pulse so that the pulse width is
changed from the next output pulse.
Undefined data is read when timer Ai is read.
The 8-bit length pulse width modulator is described next.
The 8-bit length pulse width modulator is selected when the timer
Ai mode register bit 5 is “1”.
The reload register and the counter are both divided into 8-bit
halves.
The low order 8 bits function as a prescaler and the high order 8
bits function as the 8-bit length pulse width modulator. The
prescaler counts the clock selected by bits 6 and 7. A pulse is generated when the counter reaches 000016 as shown in Figure 26.
At the same time, the contents of the reload register is transferred
to the counter and count is continued.
22
Addresses
Timer A0 mode register
56 16
Timer A1 mode register
57 16
Timer A2 mode register
58 16
7 6 5 4 3 2 1 0
Timer A3 mode register
59 16
1 1 1
Timer A4 mode register
5A 16
1 1 : Always “11” in pulse width
modulation mode
1 : Always “1” in pulse width
modulation mode
0 ✕ : Software trigger
1 0 : Trigger at the falling of TAi IN input
1 1 : Trigger at the rising of TAi IN input
0 : 16 bit pulse width modulator
1 : 8 bit pulse width modulator
Clock source selection bit
0 0 : Select f 2
0 1 : Select f 16
1 0 : Select f 64
1 1 : Select f 512
Fig. 24 Timer Ai mode register bit configuration during pulse
width modulation mode
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Therefore, if the low order 8-bit of the reload register is n, the period of the generated pulse is
1
✕ (n + 1).
selected clock frequency
The high order 8-bit function as an 8-bit length pulse width modulator using this pulse as input. The operation is the same as for
16-bit length pulse width modulator except that the length is 8 bits.
If the high order 8-bit of the reload register is m, the duration “H” of
pulse is
1
✕ (n + 1) ✕ m.
selected clock frequency
And the output pulse period is
1
✕ (n + 1) ✕ (28 – 1).
selected clock frequency
1 / fi ✕ (216 – 1)
Selected clock
source f i
TAiIN
(in case of the
rising edge)
This trigger is not accepted
1 / fi ✕ (m)
TAiOUT
Example when the contents of the reload register is 0003 16.
Fig. 25 16-bit length pulse width modulator output pulse example
1 / f i ✕ (n + 1) ✕ (28 – 1)
Selected clock
source f i
TAiIN
(in case of the
falling edge)
1 / fi ✕ (n + 1)
Prescaler output
(when n = 2)
1 / fi ✕ (n + 1) ✕ (m)
8-bit length pulse
width modulator
output
(when m = 2)
Fig. 26 8-bit length pulse width modulator output pulse example
23
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMER B
Figure 27 shows a block diagram of timer B.
Timer B has three modes; timer mode, event counter mode, and
pulse period measurement/pulse width measurement mode. The
mode is selected with bits 0 and 1 of the timer Bi mode register
(i = 0 to 2). Each of these modes is described below.
(1) Timer mode [00]
Figure 28 shows the bit configuration of the timer Bi mode register
during timer mode. Bits 0, and 1 of the timer Bi mode register must
always be “0” in timer mode.
Bits 6 and 7 are used to select the clock source. The counting of
the selected clock starts when the count start flag is “1” and stops
when “0”.
As shown in Figure 13, the timer Bi count start flag is at the same
address as the timer Ai count start flag. The count is decremented,
an interrupt occurs, and the interrupt request bit in the timer Bi interrupt control register is set when the contents becomes 000016.
At the same time, the contents of the reload register is stored in
the counter and count is continued.
Timer Bi does not have a pulse output function or a gate function
like timer A.
When data is written to timer Bi halted, it is written to the reload
register and the counter. When data is written to timer Bi which is
busy, the data is written to the reload register, but not to the
counter. The counter is reloaded with new data from the reload
register at the next reload time. The contents of the counter can
be read at any time.
Data bus (odd)
Clock source selection
Data bus (even)
f2
f16
f64
f512
TBi IN
(i = 0 – 2)
(Lower 8 bits)
• Timer
• Pulse period measurement/pulse
width measurement
Polarity selection
and edge pulse
generator
Reload register (16)
Event counter
Counter (16)
Count start flag
(4016)
Counter reset
circuit
Fig. 27 Timer B block diagram
24
(Higher 8 bits)
Addresses
Timer B0 51 16 5016
Timer B1 53 16 5216
Timer B2 55 16 5416
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode [01]
Figure 29 shows the bit configuration of the timer Bi mode register
during event counter mode. In event counter mode, the bit 0 in the
timer Bi mode register must be “1” and bit 1 must be “0”.
The input signal from the TBiIN pin is counted when the count start
flag is “1” and counting is stopped when it is “0”. Count is performed at the fall of the input signal when bits 2, and 3 are “0” and
at the rise of the input signal when bit 3 is “0” and bit 2 is “1”.
When bit 3 is “1” and bit 2 is “0”, count is performed at the rise and
fall of the input signal.
Data write, data read and timer interrupt are performed in the
same way as for timer mode.
Addresses
7 6 5 4 3 2 1 0
✕
✕ ✕ 0 0
5B 16
Timer B1 mode register
5C 16
Timer B2 mode register
5D 16
0 0 : Always “00” in timer mode
✕ ✕ : Not used in timer mode and
may be any
✕ : Not used in timer mode
Clock source selection bit
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
(3) Pulse period measurement/pulse width
measurement mode [10]
Figure 30 shows the bit configuration of the timer Bi mode register
during pulse period measurement/pulse width measurement
mode.
In pulse period measurement/pulse width measurement mode, bit
0 must be “0” and bit 1 must be “1”. Bits 6 and 7 are used to select
the clock source. The selected clock is counted when the count
start flag is “1” and counting stops when it is “0”.
The pulse period measurement mode is selected when bit 3 is “0”.
In pulse period measurement mode, the selected clock is counted
during the interval starting at the fall of the input signal from the
TBiIN pin to the next fall or at the rise of the input signal to the next
rise and the result is stored in the reload register. In this case, the
reload register acts as a buffer register.
When bit 2 is “0”, the clock is counted from the fall of the input signal to the next fall. When bit 2 is “1”, the clock is counted from the
rise of the input signal to the next rise.
In the case of counting from the fall of the input signal to the next
fall, counting is performed as follows. As shown in Figure 31,
when the fall of the input signal from TBiIN pin is detected, the contents of the counter is transferred to the reload register. Next the
counter is cleared and count is started from the next clock. When
the fall of the next input signal is detected, the contents of the
counter is transferred to the reload register once more, the
counter is cleared, and the count is started. The period from the
fall of the input signal to the next fall is measured in this way.
Timer B0 mode register
Fig. 28 Timer Bi mode register bit configuration during timer
mode
Addresses
Timer B0 mode register
5B 16
7 6 5 4 3 2 1 0
Timer B1 mode register
5C 16
✕ ✕ ✕
Timer B2 mode register
5D 16
0 1
0 1 : Always “01” in event counter
mode
0 0 : Count at the falling edge of input
signal
0 1 : Count at the rising edge of input
signal
1 0 : Count at the both falling edge and
rising edge of input signal
✕ ✕ ✕ : Not used in event counter mode
Fig. 29 Timer Bi mode register bit configuration during event
counter mode
7
6
5
4
3
2
1
0
1
0
Addresses
Timer B0 mode register 5B 16
Timer B1 mode register 5C 16
Timer B2 mode register 5D 16
1 0 : Always “10” in pulse period
measurement/pulse width
measurement mode
0 0 : Count from the falling edge of
input signal to the next falling one
0 1 : Count from the rising edge of
input signal to the next rising one
1 0 : Count from the falling edge of input
signal to the next rising one
and from the rising edge to the
next falling one
Timer Bi overflow flag
Clock source selection bit
0 0 : Select f 2
0 1 : Select f 16
1 0 : Select f 64
1 1 : Select f 512
Fig. 30 Timer Bi mode register bit configuration during pulse
period measurement/pulse width measurement mode
25
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
After the contents of the counter is transferred to the reload register, an interrupt request signal is generated and the interrupt
request bit in the timer Bi interrupt control register is set. However,
no interrupt request signal is generated when the contents of the
counter is transferred first time to the reload register after the
count start flag is set to “1”.
When bit 3 is “1”, the pulse width measurement mode is selected.
Pulse width measurement mode is similar to pulse period measurement mode except that the clock is counted from the fall of the
TBiIN pin input signal to the next rise or from the rise of the input
signal to the next fall as shown in Figure 32.
When timer Bi is read, the contents of the reload register is read.
Note that in this mode, the interval between the fall of the TBiIN pin
input signal to the next rise or from the rise to the next fall must be
at least two cycles of the timer count source.
Timer Bi overflow flag which is bit 5 of time Bi mode register is set
to “1” when the timer Bi counter reaches 000016.
This flag is cleared by writing to corresponding timer Bi mode register. This bit is set to “1” at reset.
Selected clock
source fi
TBiIN
Reload register←Counter
Counter←0
Count start flag
Interrupt request signal
Fig. 31 Pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one)
Selected
clock source fi
TBiIN
Reload register←Counter
Counter←0
Count start
flag
Interrupt
request signal
Fig. 32 Pulse width measurement mode operation
26
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SERIAL I/O PORTS
Two independent serial I/O ports are provided. Figure 33 shows a
block diagram of the serial I/O ports.
Bits 0, 1, and 2 of the UARTi (i = 0, 1) Transmit/Receive mode register shown in Figure 34 are used to determine whether to use port
P8 as parallel port, clock synchronous serial I/O port, or asynchro-
nous (UART) serial I/O port using start and stop bits.
Figures 35 and 36 show the connections of receiver/transmitter
according to the mode.
Figure 37 shows the bit configuration of the UARTi transmit/receive control register.
Each communication method is described below.
Data bus (odd)
Data bus (even)
0
0
0
0
0
0
RxDi
Receive
0 D8 D7 D6 D5 D4 D3 D2 D1 D0 buffer register
UART0 (3716 , 3616)
UART1 (3F16, 3E16)
Receive register
UART receive
1/16 Divider
Clock source selection
f2
f 16
f 64
f 512
Bit rate
generator
UART0(3116 )
UART1(3916 )
Internal
1/(n + 1)
Divider
Clock synchronous
Receive clock
UART transmission
1/16 Divider
Clock synchronous
1/2 Divider
Receive control
circuit
Transmission
control circuit
Clock synchronous
(Internal clock)
External
Clock synchronous
(Internal clock)
Clock synchronous
(External clock)
Transmission clock
TxDi
Transmission register
Transmission
D8 D7 D6 D5 D4 D3 D2 D1 D0 buffer register
UART0 (33 16, 3216)
UART1 (3B 16, 3A16)
CLKi
CTSi/RTSi
Data bus (odd)
Data bus (even)
Fig. 33 Serial I/O port block diagram
7 6 5 4 3 2 1 0
Addresses
UART 0 transmit/receive mode register 30 16
UART 1 transmit/receive mode register 38 16
Serial communication method selection bits
0 0 0 : Parallel port
0 0 1 : Clock synchronous
1 0 0 : 7-bit UART
1 0 1 : 8-bit UART
1 1 0 : 9-bit UART
Internal clock/External clock selection bit
0 : Internal clock
1 : External clock
Stop bit length selection bit
0 : 1 stop bit
1 : 2 stop bits
Even/Odd parity selection bit
0 : Odd parity
1 : Even parity
Parity enable selection bit
0 : No parity
1 : With parity
Sleep selection bit
0 : No sleep
1 : Sleep
Fig. 34 UART i Transmit/ Receive mode register bit
configuration
27
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data bus (odd)
Data bus (even)
0
0
0
0
0
0
2 stop bit
RxDi
Stop
bit
0
Parity
bit
1 stop bit
D7
D6
D5
D4
D3
D2
D1
D0
Receive buffer
register
8 bit
9 bit
Synchronous
9 bit
7 bit
8 bit
9 bit
Parity
Stop
bit
D8
Receive
register
No
parity
7 bit
8 bit
7 bit
Synchronous
Synchronous
Fig. 35 Receiver block diagram
Data bus (odd)
Data bus (even)
D8
2 stop bit
“0”
Stop
bit
Stop
bit
Parity 7 bit
8 bit
9 bit
Parity
bit
D7
D6
D5
D4
D3
No
parity
8 bit
1 stop bit
“0”
D2
D1
D0
8 bit
7 bit
9 bit
9 bit
Synchro- Synchronous
nous
TxDi
Transmission register
7 bit
Synchronous
Fig. 36 Transmitter block diagram
7
6
5
4
3
2
Tx
R/C
EPTY
1
0
CS1
CS0
Addresses
UART 0 transmit/receive control register 0 34 16
UART 1 transmit/receive control register 0 3C 16
Clock source selection bits
0 0 : Select f 2
0 1 : Select f 16
1 0 : Select f 64
1 1 : Select f 512
CTS, RTS Selection bit
0 : Select CTS
1 : Select RTS
Transmission register empty bit
7
6
5
4
SUM PER FER OER
3
2
1
0
RI
RE
TI
TE
Addresses
UART 0 transmit/receive control register 1 35 16
UART 1 transmit/receive control register 1 3D 16
Transmit enable flag
Transmit buffer empty flag
Receive enable flag
Receive completion flag
Overrun error flag
Framing error flag
Parity error flag
Error sum flag
Fig. 37 UARTi Transmit/Receive control register bit configuration
28
Transmission
buffer register
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK SYNCHRONOUS SERIAL
COMMUNICATION
A case where communication is performed between two clock synchronous serial I/O ports as shown in Figure 38 will be described.
(The transmission side will be denoted by subscript j and the receiving side will be denoted by subscript k.)
Bit 0 of the UARTj transmit/receive mode register and UARTk
transmit/receive mode register must be set to “1” and bits 1 and 2
must be “0”. The length of the transmission data is fixed at 8 bits.
Bit 3 of the UARTj transmit/receive mode register of the clock
sending side is cleared to “0” to select the internal clock. Bit 3 of
the UARTk transmit/receive mode register of the clock receiving
side is set to “1” to select the external clock. Bits 4, 5 and 6 are ignored in-clock synchronous mode. Bit 7 must always be “0”.
The clock source is selected by bit 0 (CS0) and bit 1 (CS1) of the
clock sending side UARTj transmit/receive control register 0. As
shown in Figure 33, the selected clock is divided by (n +1), then
by 2, passed through a transmission control circuit, and output as
transmission clock CLKj. Therefore, when the selected clock is fi,
Bit Rate = fi/ {(n + 1) ✕ 2}
On the clock receiving side, the CS0 and CS1 bits of the UARTk
transmit/receive control register 0 are ignored because an external
clock is selected.
The bit 2 of the clock sending side
UARTj transmit/receive control
____
register 0 is clear to “0” to select CTSj
input. The bit____
2 of the clock
_____
____
receiving side is set to “1” to select RTSk output. CTS, and RTS
signals are described later.
Transmission
Transmission is started when the bit 0 (TEj flag) of UARTj transmit/receive
control register 1 is “1”, bit 1 (Tlj flag) of one is “0”, and
____
CTSj input is “L”. As shown in Figure 39, data is output from TxDj
pin when transmission clock CLKj changes from “H” to “L”. The
data is output from the least significant bit.
The Tlj flag indicates whether the transmission buffer register is
empty or not. It is cleared to “0” when data is written in the transmission buffer register and set to “1” when the contents of the
transmission buffer register is transferred to the transmission register.
When the transmission register becomes empty after the contents
has been transmitted, data is transferred automatically from the
transmission buffer register to the transmission register if the next
transmission start condition is satisfied.____
If the bit 2 of UARTj transmit/receive control register 0 is “1”, CTSj input is ignored and
transmission start is controlled only by the TEj flag and____
TIj flag.
Once transmission has started, the TEj flag, TIj flag, and CTSj signals are ignored until data transmission
completes. Therefore,
____
transmission is not interrupt when CTSj input is changed to “H”
during transmission.
The
transmission start condition indicated by TEj flag, TIj flag, and
____
CTSj is checked while the TENDj signal shown in Figure 39 is “H”.
Therefore, data can be transmitted continuously if the next transmission data is written in the transmission buffer register and TIj
flag is cleared to “0” before the TENDj signal goes “H”.
The bit 3 (TxEPTYj flag) of UARTj transmit/receive control register 0 changes to “1” at the next cycle after the TENDj signal goes
“H” and changes to “0” when transmission starts. Therefore, this
flag can be used to determine whether data transmission has
completed.
When the TIj flag changes from “0” to “1”, the interrupt request bit
in the UARTj transmission interrupt control register is set to “1”.
Receive
Receive starts when the bit 2 (REk flag) of UARTk transmit/receive
control
register 1 is set to “1”.
_____
The RTSk output is “H” when the REk flag is “0” and goes “L” when
the REk flag changed _____
to “1”. It goes back to “H” when receive
starts. Therefore, the RTS k output can be used to determine
whether the receive register is ready to receive. It is ready when
_____
RTSk output is “L”.
The data from the RxDk pin is retrieved and the contents of the receive register is shifted by 1 bit each time the transmission clock
CLKj changes from “L” to “H”. When an 8-bit data is received, the
contents of the receive register is transferred to the receive buffer
register and the bit 3 (RIk flag) of UARTk transmit/receive control
register 1 is set to “1”. In other words, the setting of the RIk flag indicates that the
receive buffer register contains the received data.
_____
At this point, RTSj output goes “L” to indicate that the next data
can be received. When the RIk flag changes from “0” to “1”, the interrupt request bit in the UARTk receive interrupt control register is
set to “1”. Bit 4 (OERk flag) of UARTk transmit/receive control register is set to “1” when the next data is transferred from the receive
register to the receive buffer register while RIk flag is “1”, and indicates that the next data was transferred to the receive register
before the contents of the receive buffer register was read.
RIk and OERk flags are cleared automatically to “0” when the loworder byte of the receive buffer register is read. The OERk flag is
also cleared when the REk flag is cleared. Bit 5 (FERk flag), bit 6
(PERk flag), and bit 7 (SUMk flag) are ignored in clock synchronous mode.
As shown in Figure 33, with clock synchronous serial communication, data cannot be received unless the transmitter is operating
because the receive clock is created from the transmission clock.
Therefore, the transmitter must be operating even when there is
no data to be sent from UARTk to UARTj.
29
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TxDk
TxDj
UARTj transmission register
UART k transmission register
UART j transmission buffer register
UART k transmission buffer register
UART j receive buffer register
UART k receive buffer register
RxDj
RxDk
UART j receive register
UART k receive register
UART j transmit/receive mode register
✕
0
✕
✕
0
0
0
UART k transmit/receive mode register
1
0
CLKj
0
TI
1
Tx
EPTY
CTSj
RE
✕
0
0
1
UART k transmit/receive control register 0
CS1 CS 0
1
✕
UART k transmit/receive control register 1
SUM PER FER OER RI
TE
RE
TI
Fig. 38 Clock synchronous serial communication
1 / fi ✕ ( n + 1 ) ✕ 2
Transmission
clock
TEj
TIj
Write in transmission buffer register
Transmission register
Transmission buffer register
CTSj
1 / fi ✕ ( n + 1 ) ✕ 2
Stopped because TEj = “0”
CLKj
TENDj
T X Dj
D0 D1 D2 D3 D4 D5 D 6 D7
TXEPTYj
Fig. 39 Clock synchronous serial I/O timing
30
✕
RTSk
UART j transmit/receive control register 1
SUM PER FER OER RI
✕
CLKk
UART j transmit/receive control register 0
Tx
EPTY
✕
D0 D1 D 2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
TE
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ASYNCHRONOUS SERIAL
COMMUNICATION
The selected internal or external clock is divided by (n +1), then by
16, and passed through a control circuit to create the UART transmission clock or UART receive clock.
Therefore, the transmission speed can be changed by changing
the contents n of the bit rate generator. If the selected clock is an
internal clock fi or an external clock fEXT,
Asynchronous serial communication can be performed using 7-,
8-, or 9-bit length data. The operation is the same for all data
lengths. The following is the description for 8-bit asynchronous
communication.
With 8-bit asynchronous communication, the bit 0 of UARTi transmit/receive mode register is “1“, the bit 1 is “0”, and the bit 2 is “1”.
Bit 3 is used to select an internal clock or an external clock. If bit 3
is “0”, an internal clock is selected and if bit 3 is “1”, then external
clock is selected. If an internal clock is selected, the bit 0 (CS0)
and bit 1 (CS1) of UARTi transmit/receive control register 0 are
used to select the clock source. When an internal clock is selected
for asynchronous serial communication, the CLKi pin can be used
as a normal I/O pin.
Bit Rate = (fi or fEXT) / {(n + 1) ✕ 16}
Bit 4 is the stop bit length selection bit to select 1 stop bit or 2 stop
bits.
The bit 5 is a selection bit of odd parity or even parity.
In the odd parity mode, the parity bit is adjusted so that the sum of
the 1’s in the data and parity bit is always odd.
In the even parity mode, the parity bit is adjusted so that the sum
of the 1’s in the data and parity bit is always even.
(1 / f1 , or 1 / fEXT) ✕ (n + 1) ✕ 16
Transmission clock
TEi
TIi
Transmission register ← Transmission
buffer register
Write in transmission buffer register
CTSi
TENDi
ST D0 D1 D2 D3 D4 D5
Stopped because TEi = “0”
Parity bit Stop bit
Start bit
TXDi
D 6 D7
ST D0 D1
P SP ST D0 D1 D2 D3 D4 D 5 D6 D7 P SP
TXEPTYi
Fig. 40 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit is selected
(1 / f1 or 1 / fEXT) ✕ (n + 1) ✕ 16
Transmission clock
TEi
TIi
TENDi
Write in transmission buffer register
Start bit
TXDi
ST D0 D1 D2 D3 D4 D5 D 6
Transmission register
Transmission
←
buffer register
Stop Bit Stop Bit
D7 D8 SP SP ST D0 D1 D 2 D3 D4 D5 D6 D7 D8 SP SP
Stopped because
TEi = “0”
ST D0 D1 D2
TXEPTYi
Fig. 41 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits is selected
31
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bit 6 is the parity bit selection bit which indicates whether to add
parity bit or not.
Bits 4 to 6 should be set or reset according to the data format of
the communicating devices.
Bit 7 is the sleep selection bit. The sleep mode is described later.
The UARTi transmit/receive
control register
0 bit 2 is used to de____
____
termine
whether to use CTSi input or____
RTSi output.
____
CTSi input is used if bit 2 is “0” and RTSi output is used if bit 2 is
“1”.
____
If CTSi input is selected, the user
can control
whether to stop or
____
____
start transmission by external CTSi input. RTSi will be described
later.
Transmission
Transmission is started when the bit 0 (TEi flag) of UARTi transmit/
____
receive control
register 1 is “1”, the bit 1 (TIi flag) is “0”, and CTSi
____
input is “L” if CTSi input is selected. As shown in Figure 40 and 41,
data is output from the TxDi pin with the stop bit and parity bit
specified by the bits 4 to 6 of UARTi transmit/receive mode register. The data is output from the least significant bit.
The TIi flag indicates whether the transmission buffer is empty or
not. It is cleared to “0” when data is written in the transmission
buffer and set to “1” when the contents of the transmission buffer
register is transferred to the transmission register.
When the transmission register becomes empty after the contents
has been transmitted, data is transferred automatically form the
transmission buffer register to the transmission register if the next
transmission start condition is satisfied.
____
Once transmission
has started, the TEi flag, TIi flag, and CTSi sig____
nal (if CTSi input is selected) are ignored until data transmission is
completed.
Therefore, transmission does not stop until it completes even if the
TEi flag is cleared during transmission.
The transmission start condition indicated by TEi flag, TIi flag, and
____
CTSi is checked while the TENDi signal shown in Figure 40 is “H”.
Therefore, data can be transmitted continuously if the next transmission data is written in the transmission buffer register and TIi
flag is cleared to 0 before the TENDi signal goes “H”.
The bit 3 (TxEPTYi flag) of UARTi transmit/receive control register
0 changes to “1” at the next cycle after the TENDi signal goes “H”
and changes to “0” when transmission starts. Therefore, this flag
can be used to determine whether data transmission is completed.
When the TIi flag changes from “0” to “1”, the interrupt request bit
in the UARTi transmission interrupt control register is set to “1”.
Receive
Receive is enabled when the bit 2 (REi flag) of UARTi transmit/receive control register 1 is set. As shown in Figure 42, the
frequency divider circuit at the receiving end begin to work when a
start bit is arrived and the data is received.
fi or fEXT
RE i
R xDi
Stop bit
Start bit
D0
Check to be “L” level
Receive
Clock
D1
D7
Get data
Starting at the falling
edge of start bit
RI i
RTS i
Fig. 42 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit is selected.
32
Start bit
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
____
If RTSi output is selected by setting
the bit 2 of UARTi transmit/re____
ceive control register 0 to “1”, the RTSi output is ____
“H” when the REi
flag is “0”. When the REi flag changes to “1”, the RTSi output goes
“L” to indicate receive ready
and returns to “H” once receive has
____
started. In other words, RTSi output can be used to determine externally whether the receive register is ready to receive.
The entire transmission data bits are received when the start bit
passes the final bit of the receive block shown in Figure 35. At this
point, the contents of the receive register is transferred to the receive buffer register and the bit 3 of UARTi transmit/receive control
register 1 is set. In other words, the RIi flag indicates
that the re____
ceive buffer
register
contains
data
when
it
is
set.
If
RTS
i output is
____
selected, RTSi output goes “L” to indicate that the register is ready
to receive the next data.
The interrupt request bit in the UARTi receive interrupt control register is set when the RIi flag changes from “0” to “1”.
The bit 4 (OERi flag) of UARTi transmission control register 1 is
set when the next data is transferred from the receive register to
the receive buffer register while the RI i flag is “1”. In other words
when an overrun error occurs. If the OERi flag is “1”, it indicates
that the next data has been transferred to the receive buffer register before the contents of the receive buffer register has been
read.
Bit 5 (FERi flag) is set when the number of stop bits is less than
required (framing error).
Bit 6 (PERi flag) is set when a parity error occurs.
Bit 7 (SUMi flag) is set when either the OERi flag, FERi flag, or the
PER i flag is set. Therefore, the SUM i flag can be used to determine whether there is an error.
The setting of the RIi flag, OERi flag, FERi flag, and the PERi flag
is performed while transferring the contents of the receive register
to the receive buffer register. The RIi OERi, FERi, PERi, and SUMi
flags are cleared when the low order byte of the receive buffer register is read or when the REi flag is cleared.
puters receive the same data. Each subordinate microcomputer
checks the received data, clears the sleep bit if bits 0 to 6 are its
own address and sets the sleep bit if not. Next the main microcomputer sends data with bit 7 cleared. Then the microcomputer
with the sleep bit cleared will receive the data, but the microcomputer with the sleep bit set will not. In this way, the main
microcomputer is able to communicate with only the designated
microcomputer.
Sleep mode
The sleep mode is used to communicate only between certain microcomputers when multiple microcomputers are connected
through serial I/O.
The sleep mode is entered when the bit 7 of UARTi transmit/receive mode register is set.
The operation of the sleep mode for an 8-bit asynchronous communication is described below.
When sleep mode is selected, the contents of the receive register
is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit
asynchronous communication and bit 8 if 9-bit asychronous communication) of the received data is “0”. Also the RIi, OERi, FERi,
PERi, and the SUMi flag are unchanged. Therefore, the interrupt
request bit of the UARTi receive interrupt control register is also
unchanged.
Normal receive operation takes place when bit 7 of the received
data is “1”.
The following is an example of how the sleep mode can be used.
The main microcomputer first sends data with bit 7 set to “1” and
bits 0 to 6 set to the address of the subordinate microcomputer
which wants to communicate with. Then all subordinate microcom-
33
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The A-D converter is an 8-bit successive approximation converter.
Figure 43 shows a block diagram of the A-D converter and Figure
44 shows the bit configuration of the A-D control register. The frequency of the A-D converter operating clock φAD is selected by the
bit 7 of the A-D control register. When bit 7 is “0”, φAD is the clock
frequency divided by 8. That is, φAD = f(XIN)/8. When bit 7 is “1”,
φAD is the clock frequency divided by 4 and φAD is = f(XIN)/4. The
φAD during A-D conversion must be 250 kHz minimum because
the comparator consists of a capacity coupling amplifier.
The operating mode is selected by the bits 3 and 4 of A-D control
register. The available operating modes are one-shot, repeat,
single sweep, and repeat sweep.
The bit of data direction register bit corresponding to the A-D converter pin must be “0” (input mode) because the analog input port
is shared with port P7.
The operation of each mode is described below.
7
6
5
4
3
2
1
0
Address
A-D control register 1
1E16
Analog input selection bits
0 0 0 : Select AN 0
0 0 1 : Select AN 1
0 1 0 : Select AN 2
0 1 1 : Select AN 3
1 0 0 : Select AN 4
1 0 1 : Select AN 5
1 1 0 : Select AN 6
1 1 1 : Select AN 7
A-D operation mode selection bits
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode
Trigger selection bit
0 : Software trigger
1 : ADTRG input trigger
A-D conversion start flag
0 : Stop A-D conversion
1 : Start A-D conversion
Frequency selection flag
0 : Select f(X IN)/8
1 : Select f(X IN)/4
Fig 44 A-D control register bit configuration
A-D conversion speed selection
f(XIN)
f2
1/2
1/2
VREF
Ladder network
AVSS
1/2
φ AD
Vref
Successive approximation register
Addresses
A-D control register
(1E16)
A-D register 0 (2016)
A-D register 1 (2216)
A-D register 2 (2416)
A-D register 3 (2616)
Decoder
A-D register 4 (2816)
Comparator
A-D register 5 (2A16)
A-D register 6 (2C16)
A-D register 7 (2E16)
Data bus (even)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADTRG
Fig 43 A-D converter block diagram
34
Selector
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) One-shot mode [00]
The A-D conversion pins are selected with the bit 0 to 2 of A-D
control register. A-D conversion can be started by a software trigger or by an external trigger.
A software trigger is selected when the bit 5 of A-D control register
is “0” and an external trigger is selected when it is “1”.
When a software trigger is selected, A-D conversion is started
when bit 6 (A-D conversion start flag) is set. A-D conversion ends
after 57 φAD cycles and an interrupt request bit is set in the A-D
conversion interrupt control register. At the same time, A-D control
register bit 6 (A-D conversion start flag) is cleared and A-D conversion stops. The result of A-D conversion is stored in the A-D
register corresponding to the selected pin.
If an external trigger is selected, A-D conversion
starts when the
______
A-D conversion start flag is “1” and the ADTRG input changes from
“H” to “L”. In this case, the pins that______
can be used for A-D conversion are AN0 to AN6 because the ADTRG pin is shared with the
analog voltage input pin AN7. The operation is the same as with
software trigger except that the A-D conversion start flag is not
cleared after A-D conversion and a retrigger can be available during A-D conversion.
The operation is the same as done by software trigger except that
the A-D conversion start flag is not cleared after A-D conversion
and a retrigger can be available during A-D conversion.
(4) Repeat sweep mode [11]
The difference with the single sweep mode is that A-D conversion
does not stop after converting from the AN0 pin to the selected
pins, but repeats again from the AN0 pin. The repeat is performed
among the selected pins. Also, no interrupt request is generated.
Furthermore, if software trigger is selected, the A-D conversion
start flag is not cleared. The A-D register can be read at any time.
7
6
5
4
3
2
1
0
A-D sweep pin
selection register
Address
1F16
0 0 : AN 0, AN1 (2 pins)
0 1 : AN 0 to AN 3 (4 pins)
1 0 : AN 0 to AN 5 (6 pins)
1 1 : AN 0 to AN 7 (8 pins)
(2) Repeat mode [01]
The operation of this mode is the same as the operation of oneshot mode except that when A-D conversion of the selected pin is
complete and the result is stored in the A-D register, conversion
does not stop, but is repeated. Also, no interrupt request is issued
in this mode. Furthermore, if software trigger is selected, the A-D
conversion start flag is not cleared. The contents of the A-D register can be read at any time.
Fig. 45 A-D sweep pin selection register configuration
(3) Single sweep mode [10]
In the sweep mode, the number of analog input pins to be swept
can be selected. Analog input pins are selected by bits 1 and 0 of
the A-D sweep pin selection register (1F 16 address) shown in Figure 45. Two pins, four pins, six pins, or eight pins can be selected
as analog input pins, depending on the contents of these bits.
A-D conversion is performed only for selected input pins. After
A-D conversion is performed for input of AN 0 pin, the conversion
result is stored in A-D register 0, and in the same way, A-D conversion is performed for selected pins one after another. After A-D
conversion is performed for all selected pins, the sweep is
stopped.
A-D conversion can be started with a software trigger or with an
external trigger input. A software trigger is selected when bit 5 is
“0” and an external trigger is selected when it is “1”.
When a software trigger is selected, A-D conversion is started
when A-D control register bit 6 (A-D conversion start flag) is set.
When A-D conversion of all selected pins end, an interrupt request
bit is set in the A-D conversion interrupt control register. At the
same time, A-D control register bit 6 (A-D conversion start flag) is
cleared and A-D conversion stops.
When an external trigger is selected, A-D conversion
starts when
______
the A-D conversion start flag is “1” and the ADTRG input changes
from “H” to “L”. In this case, the A-D conversion result of the
trig______
ger input itself is stored in the A-D register 7 because the ADTRG
pin is shared with AN7 pin.
35
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution sequence caused by software run-away.
Figure 46 shows a block diagram of the watchdog timer. The
watchdog timer consists of a 12-bit binary counter.
The watchdog timer counts the clock frequency divided by 32 (f32)
or by 512 (f512). Whether to count f32 or f512 is determined by the
watchdog timer frequency selection flag shown in Figure 47. f512
is selected when the flag is “0” and f32 is selected when it is “1”.
The flag is cleared after reset. FFF16
is set in the watchdog timer
______
when “L” or 2VCC is applied to the RESET pin, STP instruction is
executed, data is written to the watchdog timer, or the most significant bit of the watchdog timer become “0”.
After FFF16 is set in the watchdog timer, the contents of watchdog
timer is decremented by one at every cycle of selected frequency
f32 or f512, and after 2048 counts, the most significant bit of watchdog timer become “0”, and a watchdog timer interrupt request bit
is set, and FFF16 is preset in the watchdog timer.
Normally, a program is written so that data is written in the watchdog timer before the most significant bit of the watchdog timer
become “0”. If this routine is not executed due to unexpected program execution, the most significant bit of the watchdog timer
become eventually “0” and an interrupt is generated.
The processor can be reset by setting the bit 3 (software reset bit)
of processor mode register described in Figure 10 in the interrupt
section and generating a reset pulse.
______
The watchdog timer stops its function when the RESET pin voltage is raised to double the VCC voltage.
The watchdog timer can also be used to recover from when the
clock is stopped by the STP instruction. Refer to the section on
clock generation circuit for more details.
The watchdog timer hold the contents during a hold state and the
frequency is stopped to input.
36
Watchdog timer
frequency selection (connection forced to f 32 during
STP instruction execution)
f32
f512
Watchdog timer
(6016)
Hold
Write to watchdog
timer
RESET
2Vcc
detection
circuit
STP instruction
S
Set “FFF16 ”
Q
R
Fig. 46 Watchdog timer block diagram
7
6
5
4
3
2
1
0
Address
Watchdog timer
6116
frequency selection
0 : Select f 512
1 : Select f 32
Fig. 47 Watchdog timer frequency selection flag
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
______
Reset occurs when the RESET pin is returned to “H” level after
holding it at “L” level when the power voltage is at 5 V ± 10%. Program execution starts at the address formed by setting the
address pins A23 – A16 to 0016, A15 – A8 to the contents of address
FFFF16, and A7 – A0 to the contents of address FFFE16.
Figure 48 shows the status of the internal registers when a reset
occurs.
Figure 49 shows an example of a reset circuit. The reset input
voltage must be held 0.9 V or lower when the power voltage
reaches 4.5 V.
Power on
M37702M2AXXXFP
4.5V
RESET
VCC
28
0V
69
0V
0.9V
Fig. 49 Example of a reset circuit (perform careful evaluation
at the system design level before using)
Address
(1) Port P0 data direction register
(0416)•••
Address
0016
(29) Processor mode register
(5E16)•••
(2) Port P1 data direction register
(0516)•••
0016
(30) Watchdog timer
(3) Port P2 data direction register
(0816)•••
0016
(4) Port P3 data direction register
(0916)•••
(31) Watchdog timer frequency selection
(6116)•••
flag
(32) A-D conversion interrupt control register (7016)•••
(5) Port P4 data direction register
(0C16)•••
0016
(6) Port P5 data direction register
(0D16)•••
0016
(7) Port P6 data direction register
(1016)•••
0016
(8) Port P7 data direction register
(1116)•••
(9) Port P8 data direction register
(1416)•••
(10) A-D control register
(1E16)••• 0 0 0 0 0 ? ? ?
(11) A-D sweep pin selection register
(1F16)•••
1 1
(12) UART 0 transmit/receive mode
register
(13) UART 1 transmit/receive mode
register
(14) UART 0 transmit/receive
control register 0
(15) UART 1 transmit/receive
control register 0
(16) UART 0 transmit/receive
control register 1
(17) UART 1 transmit/receive
control register 1
(18) Count start flag
(3016)•••
(3816)•••
(19) One- shot start flag
0 0 0 0
(6016)•••
0016
FFF16
0
0 0 0 0
(33) UART 0 transmission interrupt control (7116)•••
register
(34) UART 0 receive interrupt control register (7216)•••
0 0 0 0
0 0 0 0
0016
(35) UART 1 transmission interrupt control (7316)•••
register
(36) UART 1 receive interrupt control register (7416)•••
0016
(37) Timer A0 interrupt control register
(7516)•••
0 0 0 0
(38) Timer A1 interrupt control register
(7616)•••
0 0 0 0
(39) Timer A2 interrupt control register
(7716)•••
0 0 0 0
0016
(40) Timer A3 interrupt control register
(7816)•••
0 0 0 0
0016
0 0 0 0
0 0 0 0
(41) Timer A4 interrupt control register
(7916)•••
0 0 0 0
(3416)•••
1 0 0 0
(42) Timer B0 interrupt control register
(7A16)•••
0 0 0 0
(3C16)•••
1 0 0 0
(43) Timer B1 interrupt control register
(7B16)•••
0 0 0 0
(3516)••• 0 0 0 0 0 0 1 0
(44) Timer B2 interrupt control register
(7C16)•••
0 0 0 0
(3D16)••• 0 0 0 0 0 0 1 0
(45) INT0 interrupt control register
(7D16)•••
0 0 0 0 0 0
(4016)•••
0016
(46) INT1 interrupt control register
(7E16)•••
0 0 0 0 0 0
(4216)•••
0 0 0 0 0
(47) INT2 interrupt control register
(7F16)•••
0 0 0 0 0 0
(20) Up-down flag
(4416)•••
0016
(48) Processor status register PS
(21) Timer A0 mode register
(5616)•••
0016
(49) Program bank register PG
(22) Timer A1 mode register
(5716)•••
0016
(50) Program counter PC H
Content of FFFF 16
(23) Timer A2 mode register
(5816)•••
0016
(51) Program counter PC L
Content of FFFE 16
(24) Timer A3 mode register
(5916)•••
0016
(52) Direct page register DPR
(25) Timer A4 mode register
(5A16)•••
0016
(53) Data bank register DT
(26) Timer B0 mode register
(5B16)••• 0 0 1
(27) Timer B1 mode register
(5C16)••• 0 0 1
0 0 0 0
(28) Timer B2 mode register
(5D16)••• 0 0 1
0 0 0 0
0 0 0 ? ? 0 0 0 1 ? ?
0016
000016
0016
0 0 0 0
Contents of other registers and RAM are not initialized and should be initialized by software.
Fig. 48 Microcomputer internal status during reset
37
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INPUT/OUTPUT PINS
Ports P8 to P0 all have a data direction register and each bit can
be programmed for input or output. A pin becomes an output pin
when the corresponding data direction register is set and an input
pin when it is cleared.
When pin programmed for output, the data is written to the port
latch and it is output to the output pin. When a pin is programmed
for output, the contents of the port latch is read instead of the
value of the pin. Therefore, a previously output value can be read
correctly even when the output “L” voltage is raised due to reasons such as directly driving an LED.
A pin programmed for input is floating and the value input to the
pin can be read. When a pin is programmed for input, the data is
written only in the port latch and the pin stays floating.
If an input/output pin is not used as an output port, clear the bit of
the corresponding data direction register so that the pin become
input mode.
Figure 50 shows
a block diagram of ports P8 to P0 in single-chip
_
mode and the E pin output.
In memory expansion mode, microprocessor mode, and evaluation chip mode, ports P4 to P0 are also used as address, data,
and control signal pins.
Refer to the section on processor modes for more details.
38
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Ports P00 – P07, P10 – P17, P20 – P27, P30 – P33, P42 – P46 (Inside dotted-line not included)
Ports P40, P41, P47, P57, P61 – P67, P82, P86 (Inside dotted-line included, but P82, P86 are without hysterisis)
Data direction register
Data bus
Port latch
• Ports P70 – P76 (Inside dotted-line not included)
• Ports P77 (Inside dotted-line included)
Data direction register
Data bus
Port latch
Analog input
• Ports P83, P87 (Inside dotted-line not included)
• Ports P50 – P56, P60 (Inside dotted-line included)
Data direction register
“1”
Output
Data bus
Port latch
• Ports P80, P81, P84, P85
Data direction register
“1”
“0”
Output
Data bus
Port latch
•E
_
Fig. 50 Block diagram for ports P8 to P0 in single-chip mode and the E pin output
39
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PROCESSOR MODE
• BYTE pin
The bits 0 and 1 of processor mode register as shown in Figure 51
are used to select any mode of single-chip mode, memory expansion mode, microprocessor mode, and evaluation chip mode.
Ports P3 to P0 and a part of port P4 are used as address, data,
and control signal I/O pins except in single-chip mode.
Figure 52 shows the functions of ports P4 to P0 in each mode.
The external memory area changes when the mode changes.
Figure 53 shows the memory map for each mode.
Refer to Figure 1 for the memory map of the single-chip mode.
The external memory area can be accessed except in single-chip
mode. The accessing of the external memory is affected by the
BYTE pin and the bit 2 (wait bit) of processor mode register.
These will be described next.
When accessing the external memory, the level of the BYTE pin is
used to determine whether to use the data bus as 8-bit width or
16-bit width.
The data bus width is 8 bits when the level of the BYTE pin is “H”
and port P2 becomes the data I/O pin.
The data bus width is 16 bits when the level of the BYTE pin is “L”
and ports P1 and P2 become the data I/O pins.
When accessing the internal memory, The data bus width is always 16 bits regardless of the BYTE pin level.
An exclusive mode in the evaluation chip mode allows the BYTE
pin level to be set to 2·VCC. In this case, the operation is slightly
different from the above. This is described in the evaluation chip
mode section.
7 6 5 4 3 2 1 0
0
Processor mode register
Address
5E16
Processor mode bit
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Evaluation chip mode
Wait bit
0 : Wait
1 : No Wait
Software reset bit
Reset occurs when this bit is set to 1
Interrupt priority resolusion time selection bit
0 0 : Select 1/f (X IN) ✕ 14
0 1 : Select 1/f (X IN) ✕ 8
1 0 : Select 1/f (X IN) ✕ 4
Test mode bit
This bit must be "0"
Clock φ1 output selection bit
0 : No φ1 output
1 : φ1 output
Fig. 51 Processor mode register bit configuration
40
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port
CM1
0
0
1
1
CM0
0
1
0
1
Single-chip Mode
Memory Expansion Mode
Microprocessor
Mode
Evaluation Chip Mode
Same as left
Same as left
Same as left
Same as left
Mode
Port P0
E
E
P07
to
P00
P07
to
P00
I/O Port
E
E
Port P1
BYTE =“L”
BYTE =“H”
P17
to
P10
P17
to
P10
I/O Port
or 2 • VCC
(Evaluation
chip mode
only.)
Port P2
A15 to A8
Address
E
E
P17
to
P10
P17
to
P10
P27
to
P20
P27
to
P20
Address A15 to A8
Same as left
A15 to A8
Address Data(odd)
Ports P4, P5 and their direction
registers are treated as 16-bit wide
bus. If BYTE = 2 • VCC, the internal
ROM area is also treated as 16-bit
wide bus.
A23 to A16
Data
(even)
Address
Same as left
Same as left
I/O Port
E
E
P27
to
P20
E
A23 to A16
Address
Data
(even, odd)
Same as left
P27
to
P20
A23 to A16
Address
Data
(even, odd)
Same as for Port P1
E
P33
Port P3
Data(odd)
E
E
BYTE =“L”
BYTE =“H”
or 2 • VCC
(Evaluation
chip mode
only.)
Address A7 to A0
P33
to
P30
I/O Port
E
HLDA
ALE
P32
P31
BHE
P30
R/W
E
P47
to
P40
I/O Port
✽ When processor mode
register bit 7 =“0”
Port P4
φ1
Same as above except P42
✽ When processor mode
register bit 7 =“1”
Same as left
E
I/O Port
P41
RDY
P40
HOLD
P42
DBC
P47
P47
to
P42
✽ When processor mode
register bit 7 =“0”
P42
Same as left
φ1
Same as above except P42
✽ When processor mode
register bit 7 =“1”
P46
VPA
P45
VDA
P44
QCL
P43
MX
P42
P41
Same as left in
spite of proces P40
-sor mode regi
-ster bit 7
φ1
RDY
HOLD
Fig. 52 Processor mode and ports P4 to P0 functions
41
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Wait bit
(1) Single-chip mode [00]
As shown in Figure 54, when the external memory area is accessed with the processor
mode register bit 2 (wait bit) cleared to
_
“0”, the “L” width of E signal becomes twice compared with no wait
(the wait bit is “1”). The wait bit is cleared to “0” at reset.
The accessing of internal memory area is performed in no wait
mode regardless of the wait bit.
The processor modes are described below.
Single-chip mode is entered by connecting the CNVSS pin to VSS
and starting from reset. Ports P4 to P0 all function as normal I/O
ports. Port P42 can be the φ1 output pin divided the clock to X IN
pin by 2 by setting bit 7 of processor mode register to “1”.
Memory expansion
mode
Microprocessor
mode
Evaluation
chip mode
216
916
A16
C16
216
916
8016
RAM
RAM
RAM
27F16
C00016
ROM
FFFF 16
FFFFFF 16
The shaded area is the external memory area.
Fig. 53 External memory area for each processor mode
Internal clock φ
Port P2
Wait bit
“1”
Data
Address
Data
Address
E
ALE
Address
Port P2
Wait bit
“0”
Address
Data
Data
E
ALE
Fig. 54 Relationship between wait bit and access time
42
(2) Memory expansion mode [01]
Memory expansion mode is entered by setting the processor
mode bits to “01” after connecting the CNVSS pin to VSS and starting from reset.
Port P0 becomes an address output pin and loses its I/O port
function.
Port P1 has two functions depending on the level of the BYTE pin.
When the BYTE_pin level is “L”, port P1 functions as an address
output
pin while E is “H” and as an odd address data I/O pin while
_
E is “L”. However,
if an internal memory is read, external data is
_
ignored while E is “L”. In this case the I/O port function is lost.
When the BYTE pin level “H”, port P1 functions as an address output pin and loses its I/O port function.
Port P2 has two functions depending on the level of the BYTE pin.
When the BYTE pin
level is “L”, port P2 functions as an address
_
output_pin while E is “H” and as an even address data I/O pin
while E is “L”. However,
if an internal memory is read, external
_
data is ignored while E is “L”.
When the BYTE_pin level is “H”, port P2 functions as an address
output pin_while E is “H” and as an even and odd address data I/O
pin while E is “L”. However,
if an internal memory is read, external
_
data is ignored while E is “L”. In this case the I/O port function is
lost.
__ ____
_____
Ports P30, P31, P32, and P33 become R/W, BHE, ALE, and HLDA
output
pin respectively and lose their I/O port functions.
__
R/W is a read/write signal which indicates a read when it is “H”
and a write when it is “L”.
____
BHE is a byte high enable signal which indicates that an odd address is accessed when it is “L”.
Therefore, two bytes at even and odd____
addresses are accessed simultaneously if address A0 is “L” and BHE is “L”.
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ALE is an address latch enable signal used to latch the address
signal from a multiplexed signal of address and data. The latch is
transparent while ALE is “H” to let the address signal pass through
and held while ALE is “L”.
_____
HLDA is a hold acknowledge signal and
is used to notify externally
_____
when the microcomputer receives HOLD input and enters into
hold state.
_____
____
Ports P40 and P41 become HOLD and RDY input pin respectively
and lose their output pin function, but the input pin function remains.
_____
HOLD is a hold request signal.
It is an input signal used to put the
_____
microcomputer in hold state. HOLD input is accepted when the internal clock φ falls from “H” level to “L” level while the bus is not
used. Ports P0, P1, P2, P30, and P31 are floating while the microcomputer stays in hold state. These ports
are floating after one
_____
cycle of the internal clock φ later than HLDA signal changes to “L”
level. At the removing of hold state, these ports
are removed from
_____
floating state after one cycle of φ later than HLDA signal changes
to “H” level.
____
RDY is a ready signal. If this signal goes “L”, the internal clock φ
stops at “L”. When φ1 output from port P42 is selected by ____
setting
bit 7 of processor mode register to “1”, φ1 output keeps on. RDY is
used when slow external memory is attached.
When a voltage twice the VCC voltage is applied to the BYTE pin,
the addresses corresponding to the internal ROM area are also
treated as 16-bit data bus.
The functions of ports P40 and P41 are the same as in memory
expansion mode.
Ports P42 to P46 become φ1, MX, QCL,
VDA, and VPA output pins
____
respectively. Port P47 becomes the DBC input pin.
φ1 from port P42 divided the clock to XIN pin by 2 is always output
in spite of bit 7 of processor mode register.
The MX signal normally contains the contents of flag m, but the
contents of flag x is output if the CPU is using flag x.
QCL is the queue buffer clear signal. It becomes “H” when the instruction queue buffer is cleared, for example, when a jump
instruction is executed.
VDA is the valid data address signal. It becomes “H” while the
CPU is reading data from data buffer or writing data to data buffer.
It also becomes “H” when the first byte of the instruction (operation code) is read from the instruction queue buffer.
VPA is the valid program address signal. It becomes “H” while the
CPU is reading an instruction code from the instruction queue
buffer.
____
DBC is the debug control signal and is used for debugging. Table
5 shows the relationship between the CNVSS pin input levels and
processor modes.
(3) Microprocessor mode [10]
Microprocessor mode is entered by connecting the CNVSS pin to
VCC and starting from reset. It can also be entered by programming the processor mode bits to “10” after connecting the CNVSS
pin to VSS and starting from reset. This mode is similar to memory
expansion mode except that internal ROM is disabled and an external memory is required, and φ1 from port P42 is always output
in spite of bit 7 of processor mode register.
Table 5. Relationship between the CNVSS pin input levels and
processor modes
CNVSS
VSS
(4) Evaluation chip mode [11]
Evaluation chip mode is entered by applying voltage twice the VCC
voltage to the CNVSS pin. This mode is normally used for evaluation tools.
The functions of ports P0 and P3 are the same as in memory expansion mode.
_
Port P1 functions as an address output_ pin while E is “H” and as
data I/O pin of odd addresses while E is “L” regardless of the
BYTE pin level. However,
if an internal memory is read, external
_
data is ignored while E is “L”.
_
Port P2 function as an address output
pin while E is “H” and as
_
data I/O pin of even addresses while E is “L” when the BYTE pin
level is “L”. However,
if an internal memory is read, external data
_
is ignored while E is “L”.
When the BYTE pin level _is “H” or 2·VCC, port P2 functions as an
address output pin while
E is “H” and as data I/O pin of even and
_
odd addresses while E is “L”. However,
if an internal memory is
_
read, external data is ignored while E is “L”.
Port P4 and its data direction register which are located at address 0A16 and 0C 16 are treated differently in evaluation chip
mode. When these addresses are accessed, the data bus width is
treated as 16 bits regardless of the BYTE pin level, and the access cycle is treated as internal memory regardless of the wait bit.
•
•
•
•
Mode
Single-chip
Memory expansion
Microprocessor
Evaluation chip
• Microprocessor
• Evaluation chip
VCC
2·VCC
• Evaluation chip
Description
Single-chip mode upon
starting after reset. Other
modes can be selected by
changing the processor
mode bit by software.
Microprocessor mode upon
starting after reset. Evaluation chip mode can be
selected by changing the
processor mode bit by software.
• Evaluation chip mode only.
43
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Figure 55 shows a block diagram of the clock generator.
When an STP instruction is executed, the internal clock φ stops
oscillating at “L” level. At the same time, FFF16 is written to watchdog timer and the watchdog timer input connection is forced to f32.
This connection is broken and connected to the input determined
by the watchdog timer frequency selection flag when the most significant bit of the watchdog timer is cleared or reset.
Oscillation resumes when an interrupt is received, but the internal
clock φ remains at “L” level until the most significant bit of the
watchdog timer is cleared. This is to avoid the unstable interval at
the start of oscillation when using a ceramic resonator.
When a WIT instruction is executed, the internal clock φ stops at
“L” level, but the oscillator does not stop. The clock is restarted
when an interrupt is received. Instructions can be executed immediately because the oscillator is not stopped.
The stop or wait state is released when an interrupt is received or
when reset is issued. Therefore, interrupts must be enabled before executing a STP or WIT instruction.
Figure 56 shows a circuit example using a ceramic (or quartz crystal) resonator. Use the manufacture’s recommended values for
constants such as capacitance which differ for each resonator.
Figure 57 shows an example of using an external clock signal.
M37702M2AXXXFP
XIN
XOUT
1MΩ
29
30
Rd
Fig. 56 Circuit using a ceramic resonator
M37702M2AXXXFP
X IN
XOUT
29
30
Open
External clock source
Vcc
Vss
Fig. 57 External clock input circuit
Interrupt request
S
STP instruction
R
Q
S
WIT instruction
Q
Q
R
Reset
S
R
STP instruction
Watchdog
timer
Internal clock φ
f2
1/2
XIN
XOUT
Fig. 55 Block diagram of a clock generator
44
f16
1/8
f32
1/2
f64
1/2
1/8
f512
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ADDRESSING MODES
The M37702M2AXXXFP has 28 powerful addressing modes.
Refer to the 7700 Family addressing mode description for the details of each addressing mode.
MACHINE INSTRUCTION LIST
The M37702M2AXXXFP has 103 machine instructions. Refer to
the 7700 Family machine instruction list for details.
DATA REQUIRED FOR MASK ORDERING
Please send the following data for mask orders.
(1) Mask ROM order confirmation form
(2) 80P6N mark specification form
(3) ROM data (EPROM 3 sets)
45
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M37702M2AXXXFP
ELECTRICAL CHARACTERISTICS (VCC = 5 V, VSS = 0 V, Ta = 25 °C, f(XIN) = 16 MHz, unless otherwise noted)
Symbol
VOH
Parameter
Limits
Test conditions
Min.
High-level output voltage P00–P07, P10–P17, P20–P27, IOH = –10 mA
P30, P31, P33, P40–P47,
P50–P57, P60–P67, P70–P77,
P80–P87
Typ.
Max.
Unit
3
V
VOH
High-level output voltage P00–P07, P10–P17, P20–P27, IOH = –400 µA
P30, P31, P33
4.7
VOH
High-level output voltage P32
IOH = –10 mA
3.1
IOH = –400 µA
4.8
IOH = –10 mA
3.4
IOH = –400 µA
4.8
V
V
_
VOH
High-level output voltage E
V
Low-level output voltage P00–P07, P10–P17, P20–P27, IOL = 10 mA
P30, P31, P33, P40–P47,
P50–P57, P60–P67, P70–P77,
P80–P87
VOL
VOL
Low-level output voltage P00–P07, P10–P17, P20–P27, IOL = 2 mA
P30, P31, P33
VOL
Low-level output voltage P32
2
V
0.45
IOL = 10 mA
1.9
IOL = 2 mA
0.43
IOL = 10 mA
1.6
IOL = 2 mA
0.4
V
V
_
VOL
Low-level output voltage E
V
_____ ____
VT+ – VT–
Hysteresis ____
HOLD,
RDY,_____
TA0IN_____
–TA4IN_____
, TB0IN–TB2IN,
____
INT0–INT2, ADTRG, CTS0, CTS1, CLK0, CLK1
0.4
1
V
______
VT+ – VT–
Hysteresis RESET
0.2
0.5
V
VT+ – VT–
Hysteresis XIN
0.1
0.3
V
IIH
High-level input current
IIL
Low-level input current
P00–P07, P10–P17, P20–P27, VI = 5 V
P30–P33, P40–P47, P50–P57,
P60–P6
7, P70–P77, P80–P87,
______
XIN, RESET, CNVSS, BYTE
5
P00–P07, P10–P17, P20–P27, VI = 0 V
P30–P33, P40–P47, P50–P57,
7, P70–P77, P80–P87,
P60–P6
______
XIN, RESET, CNVSS, BYTE
–5
µA
µA
VRAM
RAM hold voltage
When clock is stopped.
ICC
Power supply current
In single-chip
mode output only
pin is open and
other pins are
VSS during reset.
2
f(XIN) = 16 MHz,
square waveform
V
12
24
Ta = 25 °C when
clock is stopped.
1
Ta = 85 °C when
clock is stopped.
20
mA
µA
A-D CONVERTER CHARACTERISTICS (VCC = 5 V, VSS = 0 V, Ta = 25 °C, f(XIN) = 16 MHz, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min.
Typ.
Max.
Unit
—
Resolution
VREF = VCC
8
Bits
—
Absolute accuracy
VREF = VCC
±3
LSB
RLADDER
Ladder resistance
VREF = VCC
10
kΩ
tCONV
Conversion time
VREF
Reference voltage
2
VCC
V
VIA
Analog input voltage
0
VREF
V
46
2
µs
14.25
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
VCC
Supply voltage
–0.3 to 7
V
AVCC
Analog supply voltage
–0.3 to 7
V
–0.3 to 12
V
______
VI
Input voltage
RESET, CNVSS, BYTE
VI
Input voltage
P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, VREF, XIN
–0.3 to VCC+0.3
Output voltage P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P5
_ 7 , P60 –P67 , P70–P7 7,
P80–P87, XOUT, E
–0.3 to VCC+0.3
VO
V
V
Pd
Power dissipation
300
mW
Topr
Operating temperature
Ta = 25 °C
–20 to 85
°C
Tstg
Storage temperature
–40 to 150
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
(VCC = 5 V ± 10%, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Parameter
VCC
Supply voltage
AVCC
Analog supply voltage
VSS
Min.
4.5
Typ.
Max.
5.0
5.5
Unit
V
VCC
V
Supply voltage
0
V
AVSS
Analog supply voltage
0
VIH
High-level input voltage
7,
P00–P07, P30–P33, P40–P47, P50–P5
______
P60–P67, P70–P77, P80–P87, XIN, RESET,
CNVSS, BYTE
0.8VCC
V
VCC
V
VIH
High-level input voltage
P10–P17, P20–P27
(in single-chip mode)
0.8VCC
VCC
VIH
High-level input voltage
P10–P17, P20–P27
(in memory expansion mode and microprocessor mode)
0.5VCC
VCC
VIL
Low-level input voltage
V
7,
P00–P07, P30–P33, P40–P47, P50–P5
______
P60–P67, P70–P77, P80–P87, XIN, RESET,
CNVSS, BYTE
0
0.2VCC
V
VIL
Low-level input voltage
P10–P17, P20–P27
(in single-chip mode)
0
0.2VCC
VIL
Low-level input voltage
P10–P17, P20–P27
(in memory expansion mode and microprocessor mode)
0
0.16VCC
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
f(XIN)
–10
High-level average output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87
–5
Low-level peak output current
P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87
10
P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87
5
M37702M2AXXXFP, M37702S1AFP
16
M37702M2BXXXFP, M37702S1BFP
25
Low-level average output current
External clock frequency input
V
V
P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87
High-level peak output current
V
mA
mA
mA
mA
MHz
Note 1. Average output current is the average value of a 100 ms interval.
2. The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, and P8
must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 80 mA or less, and the sum of IOH(peak) for ports
P4, P5, P6, and P7 must be 80 mA or less.
47
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS (VCC = 5 V ± 10%, VSS = 0 V, Ta = 25 °C, unless otherwise noted)
External clock input
Limits
Symbol
Parameter
16 MHz
Min.
25 MHz
Max.
Min.
Unit
Max.
tc
External clock input cycle time
62
40
ns
tw(H)
External clock input high-level pulse width
25
15
ns
tw(L)
External clock input low-level pulse width
25
15
tr
External clock rise time
10
8
ns
tf
External clock fall time
10
8
ns
ns
Single-chip mode
Limits
Symbol
Parameter
16 MHz
Min.
25 MHz
Max.
Min.
Unit
Max.
tsu(P0D–E)
Port P0 input setup time
100
60
ns
tsu(P1D–E)
Port P1 input setup time
100
60
ns
tsu(P2D–E)
Port P2 input setup time
100
60
ns
tsu(P3D–E)
Port P3 input setup time
100
60
ns
tsu(P4D–E)
Port P4 input setup time
100
60
ns
tsu(P5D–E)
Port P5 input setup time
100
60
ns
tsu(P6D–E)
Port P6 input setup time
100
60
ns
tsu(P7D–E)
Port P7 input setup time
100
60
ns
tsu(P8D–E)
Port P8 input setup time
100
60
ns
th(E–P0D)
Port P0 input hold time
0
0
ns
th(E–P1D)
Port P1 input hold time
0
0
ns
th(E–P2D)
Port P2 input hold time
0
0
ns
th(E–P3D)
Port P3 input hold time
0
0
ns
th(E–P4D)
Port P4 input hold time
0
0
ns
th(E–P5D)
Port P5 input hold time
0
0
ns
th(E–P6D)
Port P6 input hold time
0
0
ns
th(E–P7D)
Port P7 input hold time
0
0
ns
th(E–P8D)
Port P8 input hold time
0
0
ns
Memory expansion mode and microprocessor mode
Limits
Symbol
Parameter
16 MHz
Min.
Max.
25 MHz
Min.
Unit
Max.
tsu(P1D–E)
Port P1 input setup time
45
30
ns
tsu(P2D–E)
Port P2 input setup time
45
30
ns
60
55
ns
____
tsu(RDY–φ1)
RDY input setup time
tsu(HOLD–φ1)
HOLD input setup time
60
55
ns
th(E–P1D)
Port P1 input hold time
0
0
ns
th(E–P2D)
Port P2 input hold time
0
0
ns
0
0
ns
0
0
ns
_____
____
th(φ1–RDY)
RDY input hold time
th(φ1–HOLD)
HOLD input hold time
_____
48
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M37702M2BXXXFP
ELECTRICAL CHARACTERISTICS (VCC = 5 V, VSS = 0 V, Ta = 25 °C, f(XIN) = 25 MHz, unless otherwise noted)
Symbol
VOH
Parameter
Limits
Test conditions
Min.
High-level output voltage P00–P07, P10–P17, P20–P27, IOH = –10 mA
P30, P31, P33, P40–P47,
P50–P57, P60–P67, P70–P77,
P80–P87
Typ.
Max.
Unit
3
V
VOH
High-level output voltage P00–P07, P10–P17, P20–P27, IOH = –400 µA
P30, P31, P33
4.7
VOH
High-level output voltage P32
IOH = –10 mA
3.1
IOH = –400 µA
4.8
IOH = –10 mA
3.4
IOH = –400 µA
4.8
V
V
_
VOH
High-level output voltage E
V
Low-level output voltage P00–P07, P10–P17, P20–P27, IOL = 10 mA
P30, P31, P33, P40–P47,
P50–P57, P60–P67, P70–P77,
P80–P87
VOL
VOL
Low-level output voltage P00–P07, P10–P17, P20–P27, IOL = 2 mA
P30, P31, P33
VOL
Low-level output voltage P32
2
V
0.45
IOL = 10 mA
1.9
IOL = 2 mA
0.43
IOL = 10 mA
1.6
IOL = 2 mA
0.4
V
V
_
VOL
Low-level output voltage E
V
_____ ____
VT+ – VT–
Hysteresis ____
HOLD,
RDY,_____
TA0IN–TA4
, TB0IN____
–TB2____
IN,
____
____IN____
INT0–INT2, ADTRG, CTS0, CTS1, CLK0, CLK1
0.4
1
V
______
VT+ – VT–
Hysteresis RESET
0.2
0.5
V
VT+ – VT–
Hysteresis XIN
0.1
0.3
V
IIH
High-level input current
IIL
Low-level input current
P00–P07, P10–P17, P20–P27, VI = 5 V
P30–P33, P40–P47, P50–P57,
P60–P6
7, P70–P77, P80–P87,
______
XIN, RESET, CNVSS, BYTE
5
P00–P07, P10–P17, P20–P27, VI = 0 V
P30–P33, P40–P47, P50–P57,
7, P70–P77, P80–P87,
P60–P6
______
XIN, RESET, CNVSS, BYTE
–5
µA
µA
VRAM
RAM hold voltage
When clock is stopped.
ICC
Power supply current
In single-chip
mode output only
pin is open and
other pins are
VSS during reset.
2
f(XIN) = 25 MHz,
square waveform
V
19
38
Ta = 25 °C when
clock is stopped.
1
Ta = 85 °C when
clock is stopped.
20
mA
µA
A-D CONVERTER CHARACTERISTICS (VCC = 5 V, VSS = 0 V, Ta = 25 °C, f(XIN) = 25 MHz, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min.
Typ.
Max.
Unit
—
Resolution
VREF = VCC
8
Bits
—
Absolute accuracy
VREF = VCC
±3
LSB
RLADDER
Ladder resistance
VREF = VCC
10
kΩ
tCONV
Conversion time
VREF
Reference voltage
2
VCC
V
VIA
Analog input voltage
0
VREF
V
2
µs
9.12
49
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A input (Count input in event counter mode)
Limits
Symbol
Parameter
16 MHz
Min.
tc(TA)
TAiIN input cycle time
tw(TAH)
tw(TAL)
25 MHz
Max.
Min.
Unit
Max.
125
80
ns
TAiIN input high-level pulse width
62
40
ns
TAiIN input low-level pulse width
62
40
ns
Timer A input (Gating input in timer mode)
Limits
Symbol
Parameter
16 MHz
Min.
25 MHz
Max.
Min.
Unit
Max.
tc(TA)
TAiIN input cycle time
500
320
ns
tw(TAH)
TAiIN input high-level pulse width
250
160
ns
tw(TAL)
TAiIN input low-level pulse width
250
160
ns
Timer A input (External trigger input in one-shot pulse mode)
Limits
Symbol
Parameter
16 MHz
Min.
25 MHz
Max.
Min.
Unit
Max.
tc(TA)
TAiIN input cycle time
250
160
ns
tw(TAH)
TAiIN input high-level pulse width
125
80
ns
tw(TAL)
TAiIN input low-level pulse width
125
80
ns
Timer A input (External trigger input in pulse width modulation mode)
Limits
Symbol
Parameter
16 MHz
Min.
25 MHz
Max.
Min.
Unit
Max.
tw(TAH)
TAiIN input high-level pulse width
125
80
ns
tw(TAL)
TAiIN input low-level pulse width
125
80
ns
Timer A input (Up-down input in event counter mode)
Limits
Symbol
Parameter
16 MHz
Min.
Max.
25 MHz
Min.
Unit
Max.
tc(UP)
TAiOUT input cycle time
2500
2000
ns
tw(UPH)
TAiOUT input high-level pulse width
1250
1000
ns
tw(UPL)
TAiOUT input low-level pulse width
1250
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
500
400
ns
th(TIN-UP)
TAiOUT input hold time
500
400
ns
50
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B input (Count input in event counter mode)
Limits
Symbol
Parameter
16 MHz
Min.
tc(TB)
TBiIN input cycle time (one edge count)
tw(TBH)
tw(TBL)
tc(TB)
25 MHz
Max.
Min.
Unit
Max.
125
80
ns
TBiIN input high-level pulse width (one edge count)
62
40
ns
TBiIN input low-level pulse width (one edge count)
62
40
ns
TBiIN input cycle time (both edges count)
250
160
ns
tw(TBH)
TBiIN input high-level pulse width (both edges count)
125
80
ns
tw(TBL)
TBiIN input low-level pulse width (both edges count)
125
80
ns
Timer B input (Pulse period measurement mode)
Limits
Symbol
Parameter
16 MHz
Min.
25 MHz
Max.
Min.
Unit
Max.
tc(TB)
TBiIN input cycle time
500
320
ns
tw(TBH)
TBiIN input high-level pulse width
250
160
ns
tw(TBL)
TBiIN input low-level pulse width
250
160
ns
Timer B input (Pulse width measurement mode)
Limits
Symbol
Parameter
16 MHz
Min.
25 MHz
Max.
Min.
Unit
Max.
tc(TB)
TBiIN input cycle time
500
320
ns
tw(TBH)
TBiIN input high-level pulse width
250
160
ns
tw(TBL)
TBiIN input low-level pulse width
250
160
ns
A-D trigger input
Limits
Symbol
Parameter
16 MHz
Min.
25 MHz
Max.
Min.
Unit
Max.
______
tc(AD)
ADTRG input cycle time (minimum allowable trigger)
tw(ADL)
ADTRG input low-level pulse width
1000
1000
ns
125
125
ns
_____
Serial I/O
Limits
Symbol
Parameter
16 MHz
Min.
25 MHz
Max.
Min.
Unit
Max.
tc(CK)
CLKi input cycle time
250
200
ns
tw(CKH)
CLKi input high-level pulse width
125
100
ns
tw(CKL)
CLKi input low-level pulse width
125
100
td(C–Q)
TxDi output delay time
th(C–Q)
TxDi hold time
tsu(D–C)
th(C–D)
90
ns
80
ns
0
0
ns
RxDi input setup time
30
20
ns
RxDi input hold time
90
90
ns
_____
External interrupt INTi input
Limits
Symbol
Parameter
16 MHz
Min.
Max.
25 MHz
Min.
Unit
Max.
____
tw(INH)
INTi input high-level pulse width
250
250
ns
250
250
ns
____
tw(INL)
INTi input low-level pulse width
51
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS (VCC = 5 V ± 10%, VSS = 0 V, Ta = 25 °C, unless otherwise noted)
Single-chip mode
Limits
Symbol
Parameter
Test conditions
16 MHz
Min.
25 MHz
Max.
Min.
Unit
Max.
td(E–P0Q)
Port P0 data output delay time
100
80
ns
td(E–P1Q)
Port P1 data output delay time
100
80
ns
td(E–P2Q)
Port P2 data output delay time
100
80
ns
td(E–P3Q)
Port P3 data output delay time
100
80
ns
td(E–P4Q)
Port P4 data output delay time
100
80
ns
td(E–P5Q)
Port P5 data output delay time
100
80
ns
td(E–P6Q)
Port P6 data output delay time
100
80
ns
td(E–P7Q)
Port P7 data output delay time
100
80
ns
td(E–P8Q)
Port P8 data output delay time
100
80
ns
Fig. 58
Memory expansion mode and microprocessor mode (when wait bit = “1”)
Limits
Symbol
Parameter
Test conditions
16 MHz
Min.
25 MHz
Max.
Min.
Unit
Max.
td(P0A–E)
Port P0 address output delay time
td(E–P1Q)
Port P1 data output delay time (BYTE = “L”)
70
45
ns
tPXZ(E–P1Z)
Port P1 floating start delay time (BYTE = “L”)
5
5
ns
td(P1A–E)
Port P1 address output delay time
30
12
td(P1A–ALE)
Port P1 address output delay time
24
5
td(E–P2Q)
Port P2 data output delay time
70
45
ns
tPXZ(E–P2Z)
Port P2 floating start delay time
5
5
ns
td(P2A–E)
Port P2 address output delay time
30
12
td(P2A–ALE)
Port P2 address output delay time
24
5
12
30
ns
ns
ns
ns
ns
_____
td(φ1–HLDA)
HLDA output delay time
td(ALE–E)
ALE output delay time
tw(ALE)
ALE pulse width
____
td(BHE–E)
BHE output delay time
td(R/W–E)
R/W output delay time
td(E–φ1)
φ1 output delay time
th(E–P0A)
Port P0 address hold time
th(ALE–P1A)
Port P1 address hold time (BYTE = “L”)
th(E–P1Q)
50
Fig. 58
50
ns
4
4
ns
35
22
ns
30
20
ns
30
20
__
0
20
0
ns
18
ns
25
18
ns
9
9
ns
Port P1 data hold time (BYTE = “L”)
25
18
ns
tPZX(E–P1Z)
Port P1 floating release delay time (BYTE = “L”)
25
18
ns
th(E–P1A)
Port P1 address hold time (BYTE = “H”)
25
18
ns
th(ALE–P2A)
Port P2 address hold time
9
9
ns
th(E–P2Q)
Port P2 data hold time
25
18
ns
tPZX(E–P2Z)
Port P2 floating release delay time
25
18
ns
18
18
ns
18
18
ns
95
50
ns
____
th(E–BHE)
BHE hold time
th(E–R/W)
R/W hold time
__
_
tw(EL)
52
E pulse width
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory expansion mode and microprocessor mode (when wait bit = “0”, and external memory area accessed)
Limits
Symbol
Test conditions
Parameter
16 MHz
Min.
25 MHz
Max.
Min.
Unit
Max.
td(P0A–E)
Port P0 address output delay time
td(E–P1Q)
Port P1 data output delay time (BYTE = “L”)
70
45
ns
tPXZ(E–P1Z)
Port P1 floating start delay time (BYTE = “L”)
5
5
ns
td(P1A–E)
Port P1 address output delay time
30
12
td(P1A–ALE)
Port P1 address output delay time
24
5
td(E–P2Q)
Port P2 data output delay time
70
45
ns
tPXZ(E–P2Z)
Port P2 floating start delay time
5
5
ns
td(P2A–E)
Port P2 address output delay time
30
12
td(P2A–ALE)
Port P2 address output delay time
24
5
12
30
ns
ns
ns
ns
ns
_____
td(φ1–HLDA)
HLDA output delay time
td(ALE–E)
ALE output delay time
tw(ALE)
ALE pulse width
50
Fig. 58
____
td(BHE–E)
BHE output delay time
td(R/W–E)
R/W output delay time
td(E–φ1)
φ1 output delay time
th(E–P0A)
Port P0 address hold time
th(ALE–P1A)
Port P1 address hold time (BYTE = “L”)
th(E–P1Q)
50
ns
4
4
ns
35
22
ns
30
20
ns
30
20
__
0
20
0
ns
18
ns
25
18
ns
9
9
ns
Port P1 data hold time (BYTE = “L”)
25
18
ns
tPZX(E–P1Z)
Port P1 floating release delay time (BYTE = “L”)
25
18
ns
th(E–P1A)
Port P1 address hold time (BYTE = “H”)
25
18
ns
th(ALE–P2A)
Port P2 address hold time
9
9
ns
th(E–P2Q)
Port P2 data hold time
25
18
ns
tPZX(E–P2Z)
Port P2 floating release delay time
25
18
ns
18
18
ns
18
18
ns
220
130
ns
____
th(E–BHE)
BHE hold time
th(E–R/W)
R/W hold time
tw(EL)
E pulse width
__
_
P0
P1
P2
P3
100 pF
P4
P5
P6
P7
P8
φ1
E
Fig. 58 Testing circuit for ports P0–P8, φ1
53
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
tr
tf
tc
tw(H)
Single-chip mode
f(XIN)
E
td(E–P0Q)
Port P0 output
tsu(P0D–E)
th(E–P0D)
Port P0 input
td(E–P1Q)
Port P1 output
tsu(P1D–E)
th(E–P1D)
Port P1 input
td(E–P2Q)
Port P2 output
tsu(P2D–E)
th(E–P2D)
Port P2 input
td(E–P3Q)
Port P3 output
tsu(P3D–E)
th(E–P3D)
Port P3 input
td(E–P4Q)
Port P4 output
tsu(P4D–E)
th(E–P4D)
Port P4 input
td(E–P5Q)
Port P5 output
tsu(P5D–E)
th(E–P5D)
Port P5 input
td(E–P6Q)
Port P6 output
tsu(P6D–E)
th(E–P6D)
Port P6 input
td(E–P7Q)
Port P7 output
tsu(P7D–E)
th(E–P7D)
Port P7 input
td(E–P8Q)
Port P8 output
tsu(P8D–E)
Port P8 input
54
th(E–P8D)
tw(L)
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
In Event counter mode TAiOUT input
(Up-down input)
TAiIN input
(when count by falling)
TAiIN input
(when count by rising)
th(TIN –UP)
tsu(UP–TIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
RxDi
th(C–D)
tw(INL)
INTi input
tw(INH)
55
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory expansion mode and microprocessor mode
(When wait bit = “1”)
φ1
E
RDY input
tsu(RDY–φ1) th(φ1–RDY)
( When wait bit = “0”)
φ1
E
RDY input
tsu(RDY–φ1) th(φ1–RDY)
(When wait bit = “1” or “0” in common)
φ1
tsu(HOLD–φ1)
th(φ1–HOLD)
HOLD input
td(φ1–HLDA)
HLDA output
Test conditions
• VCC = 5 V ± 10%
• Input timing voltage : V IL = 1.0 V, VIH = 4.0 V
• Output timing voltage : V OL = 0.8 V, VOH = 2.0 V
56
td(φ1–HLDA)
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory expansion mode and microprocessor mode (When wait bit = “1”)
tw(L)
tr
tf
tw(H)
tc
f(XIN)
φ1
td(E- φ1)
td(E- φ1)
tw(EL)
E
td(P0A-E)
th(E-P0A)
Port P0 output
(A0 to A7)
Address
th(ALE-P1A)
Port P1 output
(A8 to A15/D8 to D15)
(BYTE = “L”)
th(E-P1Q)
Address
td(P1A-ALE)
Address
tpxz(E-P1Z)
Data
Address
Address
td(E-P1Q)
td(P1A-E)
th(E-P1A)
Port P1 output
(A8 to A15)
(BYTE = “H”)
tpzx(E-P1Z)
Address
Address
tsu(P1D-E)
th(E-P1D)
Port P1 input
th(E-P2Q)
th(ALE-P2A)
Port P2 output
(A16 to A23/D0 to D7)
Address
td(P2A-ALE)
Data
tpxz(E-P2Z)
Address
td(E-P2Q)
td(P2A-E)
tpzx(E-P2Z)
Address
tsu(P2D-E)
th(E-P2D)
Port P2 input
tw(ALE)
td(ALE-E)
Port P32 output
(ALE)
td(BHE-E)
th(E-BHE)
td(R/W-E)
th(E-R/W)
Port P31 output
(BHE)
Port P30 output
(R/W)
Test conditions
• VCC = 5 V ± 10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Ports P1, P2 input
: VIL = 0.8 V, VIH = 2.5 V
57
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory expansion mode and microprocessor mode (When wait bit = “0”, and external memory area is accessed)
tc
f(XIN)
φ1
td(E- φ1)
td(E- φ1)
tw(EL)
E
th(E-P0A)
Port P0 output
(A0 to A7)
td(P0A-E)
Address
th(ALE-P1A)
Port P1 output
(A8 to A15/D8 to D15)
(BYTE = “L”)
Address
th(E-P1Q)
Address
Data
tpxz(E-P1Z)
tpzx(E-P1Z)
Address
Address
td(E-P1Q)
td(P1A-ALE)
th(E-P1A)
Port P1 output
(A8 to A15)
(BYTE = “H”)
td(P1A-E)
Address
Address
tsu(P1D-E)
th(E-P1D)
Port P1 input
th(ALE-P2A)
Port P2 output
(A16 to A23/D0 to D7)
Address
th(E-P2Q)
Data
tpxz(E-P2Z)
tpzx(E-P2Z)
Address
Address
tsu(P2D-E)
td(E-P2Q)
td(P2A-E)
td(P2A-ALE)
Port P2 input
tw(ALE)
td(ALE-E)
Port P32 output
(ALE)
td(BHE-E)
th(E-BHE)
Port P31 output
(BHE)
td(R/W-E)
Port P30 output
(R/W)
Test conditions
• VCC = 5 V ± 10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Ports P1, P2 input
58
: VIL = 0.8 V, VIH = 2.5 V
th(E-R/W)
th(E-P2D)
MITSUBISHI DATA BOOK
SINGLE-CHIP 16-BIT MICROCOMPUTERS Vol.1
Mar. First Edition 1996
Editioned by
Committee of editing of Mitsubishi Semiconductor Data Book
Published by
Mitsubishi Electric Corp., Semiconductor Division
This book, or parts thereof, may not be reproduced in any form without permission of
Mitsubishi Electric Corporation.
© 1996 MITSUBISHI ELECTRIC CORPORATION Printed in Japan