TI SN74LVC126ADR

SN74LVC126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCAS339Q – MARCH 1994 – REVISED JULY 2005
FEATURES
•
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4OE
4A
4Y
3OE
3A
3Y
RGY PACKAGE
(TOP VIEW)
1A
1Y
2OE
2A
2Y
DESCRIPTION/ORDERING INFORMATION
This quadruple bus buffer gate is designed for 1.65-V
to 3.6-V VCC operation.
VCC
•
1
1
14
2
13 4OE
3
12 4A
4
11 4Y
5
6
10 3OE
9 3A
The SN74LVC126A features independent line drivers
with 3-state outputs. Each output is disabled when
the associated output-enable (OE) input is low.
7
8
3Y
•
1OE
1A
1Y
2OE
2A
2Y
GND
1OE
•
•
•
D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
Operates From 1.65 V to 3.6 V
Specified From –40°C to 85°C and
From –40°C to 125°C
Inputs Accept Voltages to 5.5 V
Max tpd of 4.7 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
GND
•
•
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
QFN – RGY
Tube of 50
SN74LVC126AD
Reel of 2500
SN74LVC126ADR
Reel of 250
SN74LVC126ADT
SOP – NS
Reel of 2000
SN74LVC126ANSR
LVC126A
SSOP – DB
Reel of 2000
SN74LVC126ADBR
LC126A
Tube of 90
SN74LVC126APW
Reel of 2000
SN74LVC126APWR
Reel of 250
SN74LVC126APWT
Reel of 2000
SN74LVC126ADGVR
TSSOP – PW
TVSOP – DGV
(1)
TOP-SIDE MARKING
SN74LVC126ARGYR
SOIC – D
–40°C to 125°C
ORDERABLE PART NUMBER
Reel of 1000
LC126A
LVC126A
LC126A
LC126A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1994–2005, Texas Instruments Incorporated
SN74LVC126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCAS339Q – MARCH 1994 – REVISED JULY 2005
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1A
2OE
2A
1
3OE
2
3
1Y
3A
4
4OE
5
6
2Y
4A
10
9
8
3Y
13
12
11
4Y
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
range (2)
–0.5
6.5
V
–0.5
VCC + 0.5
VI
Input voltage
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
D package (4)
86
DB package (4)
θJA
Package thermal impedance
96
DGV package (4)
127
NS package (4)
76
PW package (4)
113
RGY package (5)
Tstg
Ptot
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2
Storage temperature range
Power dissipation
125°C (6) (7)
°C/W
47
–65
TA = –40°C to
V
150
°C
500
mW
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.
SN74LVC126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCAS339Q – MARCH 1994 – REVISED JULY 2005
Recommended Operating Conditions
(1)
TA = 25°C
VCC
Supply voltage
VIH
High-level
input voltage
Input voltage
VO
Output voltage
High-level
output current
IOH
MAX
MIN
MAX
MIN
MAX
1.65
3.6
1.65
3.6
1.65
3.6
1.5
1.5
1.5
0.65 × VCC
0.65 × VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
1.7
1.7
VCC = 2.7 V to 3.6 V
2
2
2
0.35 × VCC
0.35 × VCC
0.35 × VCC
0.7
0.7
0.7
VCC = 2.7 V to 3.6 V
0.8
0.8
0.8
0
5.5
0
5.5
V
0
VCC
0
VCC
0
VCC
V
–4
–4
VCC = 2.3 V
–8
–8
–8
VCC = 2.7 V
–12
–12
–12
VCC = 3 V
–24
–24
–24
4
4
4
VCC = 1.65 V
VCC = 2.3 V
8
8
8
VCC = 2.7 V
12
12
12
VCC = 3 V
24
24
24
10
10
10
∆t/∆v
Input transition rise or fall rate
(1)
V
5.5
–4
Low-level
output current
V
0
VCC = 1.65 V
IOL
UNIT
V
VCC = 2.3 V to 2.7 V
VCC = 1.65 V to 1.95 V
VI
–40 TO 125°C
MIN
Data retention only
VCC = 1.65 V to 1.95 V
Low-level
input voltage
VIL
Operating
–40 TO 85°C
mA
mA
ns/V
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VOH
1.65 V to 3.6 V
TA = 25°C
MIN
–40 TO 85°C
TYP MAX
MIN
–40 TO 125°C
MAX
MIN MAX
VCC – 0.2
VCC – 0.2
VCC – 0.3
IOH = –4 mA
1.65 V
1.29
1.2
1.05
IOH = –8 mA
2.3 V
1.9
1.7
1.55
2.7 V
2.2
2.2
2.05
2.25
IOH = –12 mA
VOL
VCC
UNIT
V
3V
2.4
2.4
IOH = –24 mA
3V
2.3
2.2
IOL = 100 µA
1.65 V to 3.6 V
0.1
0.2
IOL = 4 mA
1.65 V
0.24
0.45
0.6
IOL = 8 mA
2.3 V
0.3
0.7
0.75
IOL = 12 mA
2.7 V
0.4
0.4
0.6
IOL = 24 mA
3V
0.55
0.55
0.8
2
0.3
V
II
VI = 5.5 V or GND
3.6 V
±1
±5
±20
µA
IOZ
VO = VCC or GND
3.6 V
±1
±10
±20
µA
ICC
VI = VCC or GND,
3.6 V
1
10
40
µA
500
500
5000
µA
∆ICC
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.7 V to 3.6 V
Ci
VI = VCC or GND
3.3 V
4.5
pF
Co
VO = VCC or GND
3.3 V
7
pF
3
SN74LVC126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCAS339Q – MARCH 1994 – REVISED JULY 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
ten
tdis
FROM
(INPUT)
TO
(OUTPUT)
A
OE
OE
VCC
TA = 25°C
MIN
–40 TO 85°C
TYP MAX
–40 TO 125°C
MIN
MAX
MIN
MAX
1.8 V ± 0.15 V
1
4.2
9.3
1
9.8
1
11.3
2.5 V ± 0.2 V
1
2.7
6.7
1
7.2
1
9.3
2.7 V
1
2.9
5
1
5.2
1
6.5
3.3 V ± 0.3 V
1
2.5
4.5
1
4.7
1
6
1.8 V ± 0.15 V
1
4.8
9.5
1
10
1
11.5
2.5 V ± 0.2 V
1
2.8
7.8
1
8.3
1
10.4
2.7 V
1
3.1
6.1
1
6.3
1
8
Y
Y
3.3 V ± 0.3 V
1
2.5
5.5
1
5.7
1
7.5
1.8 V ± 0.15 V
1
4.4
12.1
1
12.6
1
14.1
2.5 V ± 0.2 V
1
2.7
8.2
1
8.7
1
10.8
2.7 V
1
2.7
6.5
1
6.7
1
8.5
1.3
2.3
5.8
1.3
6
1.3
7.5
Y
3.3 V ± 0.3 V
3.3 V ± 0.3 V
tsk(o)
1
1.5
UNIT
ns
ns
ns
ns
Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Outputs enabled
Cpd
Power dissipation capacitance per gate
f = 10 MHz
Outputs disabled
4
VCC
TYP
1.8 V
20
2.5 V
21
3.3 V
22
1.8 V
2
2.5 V
3
3.3 V
4
UNIT
pF
SN74LVC126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCAS339Q – MARCH 1994 – REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC126AD
ACTIVE
SOIC
D
14
SN74LVC126ADBLE
OBSOLETE
SSOP
DB
14
SN74LVC126ADBR
ACTIVE
SSOP
DB
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126ADBRE4
ACTIVE
SSOP
DB
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126ADE4
ACTIVE
SOIC
D
14
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126ADGVR
ACTIVE
TVSOP
DGV
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126ADGVRE4
ACTIVE
TVSOP
DGV
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126ADR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126ADRE4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126ADT
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126ADTE4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126ANSR
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126ANSRE4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126APW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126APWE4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126APWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126APWLE
OBSOLETE
TSSOP
PW
14
SN74LVC126APWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126APWRE4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126APWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126APWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126APWTE4
ACTIVE
TSSOP
PW
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC126ARGYR
ACTIVE
QFN
RGY
14
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74LVC126ARGYRG4
ACTIVE
QFN
RGY
14
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
50
Green (RoHS &
no Sb/Br)
TBD
50
TBD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
Lead/Ball Finish
CU NIPDAU
Call TI
Call TI
MSL Peak Temp (3)
Level-1-260C-UNLIM
Call TI
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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