SPANSION S75PL127NCGJFWGZ0

S75PL-N MirrorBit™ ORNAND™ MCPs
Stacked Multi-Chip Product (MCP)
S29PL-N: CMOS 3.0 Volt-only Simultaneous Read/Write,
Page-mode Flash Memory (NOR Interface)
S30ML-P: ORNAND Flash (NAND Interface)
3V pSRAM
S75PL-N MirrorBit™ ORNAND™ MCPs Cover Sheet
Data Sheet (Advance Information)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S75PL-N_00
Revision 01E
Issue Date April 21, 2006
Data
Sheet
( A dva nce
I nf or ma ti on)
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific
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LLC therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion LLC.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion LLC reserves the right to change or discontinue work on this
proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
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Some data sheets contain a combination of products with different designations (Advance Information,
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When a product has been in production for a period of time such that no changes or only nominal changes
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“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion LLC deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical
or specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
ii
S75PL-N MirrorBit™ ORNAND™ MCPs
April 21, 2006 S75PL-N_00-01E
S75PL-N MirrorBit™ ORNAND™ MCPs
Stacked Multi-Chip Product (MCP)
S29PL-N: CMOS 3.0 Volt-only Simultaneous Read/Write,
Page-mode Flash Memory (NOR Interface)
S30ML-P: ORNAND Flash (NAND interface)
3V pSRAM
Data Sheet (Advance Information)
Features
„ Speed
„ 107-Ball Fine-Pitch Ball Grid Array (FBGA)
– PL-N: 70 ns (initial access, 30 ns page access)
– ML-P: 30 ns (page access)
– pSRAM: 70 ns
– 9 x 12 x 1.4mm for ML512P based MCP's
– 11 x 13 x 1.4mm for ML01GP based MCPs
„ Operating Temperature Range
– Temperature Range of –25°C to +85°C
General Description
This document contains information for the S75PL-N MirrorBit MCP product. TheS75PL-N product consists of the following
devices:
„ S29PL-N
„ S30ML-P
„ 3 V pSRAM
Flash/RAM Combinations Table
pSRAM Density
S29PL127N +
32 Mb
S30ML512P
S75PL127NBF
64 Mb
S30ML01GP
Product Selector Guide
Device
pSRAM Density
pSRAM Type
S75PL127NBF
32 Mb
pSRAM Type 7
For detailed specifications, please refer to the individual data sheets:
Document
Publication Identification Number (PID)
S29PL-N
S29PL-N_M0
S30ML-P
S30ML-GP_00
32M pSRAM Type 7
pSRAM_29
Publication Number S75PL-N_00
Revision 01E
Issue Date April 21, 2006
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design
in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Data
1.
Sheet
( A dva nce
I nf or ma ti on)
Ordering Information
The ordering part number is formed by a valid combination of the following:
S75PL
127
N
B
F
JF
W
GZ
0
PACKING TYPE
0 = Tray
2 = 7” Tape and Reel
3 = 13” Tape and Reel
MODEL NUMBER
Refer to the Valid Combinations table below
TEMPERATURE RANGE
W = Wireless (–25°C to +85°C)
PACKAGE TYPE AND MATERIAL
JA = MCP BGA, 1.4 mm height, 0.8 mm pitch, Lead (Pb)-free Compliant package
JF = MCP BGA, 1.4 mm height, 0.8 mm pitch, Lead (Pb)-free package
ORNAND DATA DENSITY
F = S30ML512P
G = S30ML01GP
pSRAM DENSITY
B = 32 Mb pSRAM
C = 64 Mb pSRAM
D = 128 Mb pSRAM
PROCESS TECHNOLOGY
N = 110 nm MirrorBit™ Technology
FLASH DENSITY
256 = 256 Mb
127 = 128 Mb (Single CE#)
DEVICE FAMILY
S75PL = 3.0 Volt-only Simultaneous Read/Write, Page Mode Flash Memory with Data storage
ORNAND and pSRAM
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S75PL-N MirrorBit™ ORNAND™ MCPs
S75PL-N_00_01E April 21, 2006
D a ta
1.1
S h e e t
( A dv anc e
In fo rm at ion )
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
Valid Combinations
Base Ordering
Part Number (2)
Package &
Temperature
Model
Number
Packing
Type
pSRAM
Type
PL-N
Linear Mode
Access Time
ML-P Page
Mode Access
Time
pSRAM
Linear Mode
Access Time
S75PL127NBF
JAW, JFW
GZ
0, 2, 3
(1), (2)
Type 7
70 ns
30 ns
70 ns
Package Name
FMH107
9x12x1.4mm,
107 ball
Notes:
1. 7\SHLVVWDQGDUG6SHFLI\RWKHURSWLRQVDVUHTXLUHG
2. BGA package marking omits leading “S” and packing type designator from ordering part number.
3. Contact factory for availability for any of the OPNs listed since RAM type availability may vary over time.
2. Block Diagram (S29PL-N and pSRAM on Bus 1, S30ML-P on Bus 2)
A0-A20
A0-A20
A21-A22
A21-A22
RY/BY#
RY/BY#
F-CE#
OE#
F-RST#
F-ACC/WP#
CE#
OE#
RESET#
ACC/WP#
WE#
WE#
DQ0-DQ15
DQ0-DQ15
S29PL127N
VSS
VSS
VCC
VCCQ
F-VCC
A0-A20
DQ0-DQ15
R-CE#
CE#
OE#
R-LB#
R-UB#
LB#
UB#
WE#
R-CE2
R-CE2
I/O0-I/O7
I/O0-I/O7
N-RY/BY#
RY/BY#
N-CLE
N-CE#
N-ALE
CLE
CE#
ALE
32Mb
pSRAM
Memory
S30ML512P
x8 ORNAND
VSS
VCC
VCCQ
R-VCC
VCC
N-VCC
FP#
I/O0-I/O7
VSS
S75PL-N_00_01E April 21, 2006
N-RE#
N-WP#
N-WE#
RE#
WP#
WE#
N-PRE
PRE
S75PL-N MirrorBit™ ORNAND™ MCPs
I/O0-I/O7
N-VSS
3
Data
Sheet
( A dva nce
I nf or ma ti on)
3. Connection Diagrams
3.1
S75PL-N Pinout
Figure 3.1 107-ball Fine-Pitch Ball Grid Array (S75PL127NBF)
1
2
DNU
DNU
3
4
5
6
7
8
9
10
DNU
DNU
A
B
C
Index
No ball
RFU
VSS
RFU
RFU
RFU
RFU
RFU
RFU
RFU
N-RY/BY
RFU
A7
LB#
WP#/
ACC
WE#
A8
A11
RFU
RFU
N-RE#
A3
A6
UB#
RST#
R-CE2
A19
A12
A15
RFU
N-CE#
A2
A5
A18
RY/BY#
A20
A9
A13
A21
RFU
N-VCC
A1
A4
A17
RFU
RFU
A10
A14
A22
VCCn
N-VSS
A0
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
VSSn
N-CLE
F-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
I/O7
ORNAND Flash Only
N-ALE R-CE1#
DQ0
DQ10
F-VCC R-VCC
DQ12
DQ7
VSS
I/O6
pSRAM Only
N-WE# N-WP#
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
I/O4
I/O5
RFU
VSS
RFU
I/O0
I/O1
I/O2
I/O3
N-PRE
DNU
DNU
D
E
Legend
F
Reserved for Future Use
G
DNU
H
NOR Flash Only
J
K
L
M
DNU
RFU
DNU
DNU
N
P
Note:
Top view—balls facing down. The addresses that are shared vary by MCP combination as shown in the table below:
S75PL127NBF
PL-N Addresses
PL-N/pSRAM Addresses
A22-A21
A20:A0
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
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S75PL-N MirrorBit™ ORNAND™ MCPs
S75PL-N_00_01E April 21, 2006
D a ta
3.2
S h e e t
( A dv anc e
In fo rm at ion )
FMH107—107-Ball Fine Pitch Ball Grid Array (FBGA) 9 x 12 mm package
Figure 3.2 FMH107
D1
A
D
eD
0.15 C
(2X)
10
9
SE
8
7
7
6
E
E1
5
4
eE
3
2
1
M L K J
INDEX MARK
PIN A1
CORNER
B
9
TOP VIEW
H G F
E D C
B A
PIN A1
CORNER
7
SD
0.15 C
(2X)
BOTTOM VIEW
0.20 C
A A2
A1
C
6
b
107X
0.08 C
SIDE VIEW
0.15 M C A B
0.08 M C
NOTES:
PACKAGE
FMH 107
JEDEC
N/A
DxE
12.00 mm x 9.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.40
A1
0.17
---
---
A2
0.94
---
1.11
PROFILE
BALL HEIGHT
BODY SIZE
E
9.00 BSC.
BODY SIZE
D1
8.80 BSC.
MATRIX FOOTPRINT
E1
7.20 BSC.
MD
12
MATRIX SIZE D DIRECTION
ME
10
MATRIX SIZE E DIRECTION
MATRIX FOOTPRINT
107
0.35
0.40
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E"
DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL
POSITIONS FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO
DATUMS A AND B AND DEFINE THE POSITION OF THE
CENTER SOLDER BALL IN THE OUTER ROW.
BALL COUNT
0.45
0.80 BSC.
BALL PITCH
eD
0.80 BSC.
BALL PITCH
0.40 BSC.
SOLDER BALL PLACEMENT
A3,A4,A5,A6,A7,A8,
B1,M3,M4,M5,M6,M7,M8
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS
IN THE OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
eE
SD / SE
2.
BODY THICKNESS
12.00 BSC.
n
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
NOTE
D
Øb
1.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS
IN THE OUTER ROW, SD OR SE = e/2
8.
"+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
9.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER
OR INK MARK, METALLIZED MARK INDENTATION OR
OTHER MEANS.
DEPOPULATED SOLDER BALLS
3512 \ 16-038.19 \ 8.9.05
S75PL-N_00_01E April 21, 2006
S75PL-N MirrorBit™ ORNAND™ MCPs
5
Data
4.
Sheet
( A dva nce
I nf or ma ti on)
Revision History
4.1
Revision A (April 21, 2006)
Initial release.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
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Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2006 Spansion LLC. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, and combinations thereof are
trademarks of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners.
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S75PL-N MirrorBit™ ORNAND™ MCPs
S75PL-N_00_01E April 21, 2006