21130F.book Page 1 Wednesday, December 5, 2012 2:47 PM Not recommended for new designs – Please use 93AA76C or 93AA86C. 93AA76/86 8K/16K 1.8V Microwire Serial EEPROM Features: PDIP Package 1 2 3 4 8 VCC 7 6 5 PE ORG 93AA76/86 CS CLK DI DO 93AA76/86 • Single supply operation down to 1.8V • Low-power CMOS technology: - 1 mA active current typical - 5 A standby current (typical) at 3.0V • ORG pin selectable memory configuration: - 1024 x 8 or 512 x 16-bit organization (93AA76) - 2048 x 8 or 1024 x 16-bit organization (93AA86) • Self-timed erase and write cycles • Automatic ERAL before WRAL • Power on/off data protection circuitry • Industry standard 3-wire serial I/O • Device status signal during erase/write cycles • Sequential read function • 1,000,000 erase/write cycles ensured • Data retention > 200 years • 8-pin PDIP/SOIC package • Temperature ranges available: - Commercial (C): 0C to +70C Package Types 8 VSS SOIC Package CS CLK DI DO 1 2 3 4 7 6 5 VCC PE ORG VSS Block Diagram VCC VSS Description: The Microchip Technology Inc. 93AA76/86 are 8K and 16K low voltage serial Electrically Erasable PROMs. The device memory is configured as x8 or x16 bits depending on the ORG pin setup. Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. These devices also have a Program Enable (PE) pin to allow the user to write-protect the entire contents of the memory array. The 93AA76/86 is available in standard 8-pin PDIP and 8-pin surface mount SOIC packages. Memory Array Address Decoder Address Counter Data Register Output Buffer DO DI PE CS CLK 1996-2012 Microchip Technology Inc. Mode Decode Logic Clock Generator DS21130F-page 1 21130F.book Page 2 Wednesday, December 5, 2012 2:47 PM 93AA76/86 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to Vcc + 1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C Soldering temperature of leads (10 seconds) .......................................................................................................+300°C ESD protection on all pins ..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 1.1 AC Test Conditions AC Waveform: VLO = 2.0V VHI = Vcc - 0.2V (Note 1) VHI = 4.0V for (Note 2) Timing Measurement Reference Level: Input 0.5 VCC Output Note 1: 2: 0.5 VCC For VCC 4.0V For VCC 4.0V DS21130F-page 2 1996-2012 Microchip Technology Inc. 21130F.book Page 3 Wednesday, December 5, 2012 2:47 PM 93AA76/86 TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Parameter Applicable over recommended operating ranges shown below unless otherwise noted: VCC = +1.8V to +6.0V Commercial (C): TA = 0°C to +70°C Symbol Min. Max. Units Conditions VCC 2.7V VIH1 2.0 VCC + 1 V VIH2 0.7 VCC VCC + 1 V VCC < 2.7V Low-level input voltage VIL1 -0.3 0.8 V VCC 2.7V VIL2 -0.3 0.2 VCC V VCC < 2.7V Low-level output voltage VOL1 — 0.4 V IOL = 2.1 mA; VCC = 4.5V VOL2 — 0.2 V IOL =100 A; VCC = VCC Min. High-level output voltage VOH1 2.4 — V IOH = -400 A; VCC = 4.5V VOH2 VCC-0.2 — V IOH = -100 A; VCC = VCC Min. Input leakage current ILI -10 10 A VIN = 0.1V to VCC Output leakage current ILO -10 10 A VOUT = 0.1V to VCC Pin capacitance (all inputs/outputs) CINT — 7 pF (Note 1) TA = +25°C, FCLK = 1 MHz Operating current ICC write — 3 mA VCC = 5.5V ICC read — 1 500 mA A FCLK = 3 MHz; VCC = 5.5V FCLK = 1 MHz; VCC = 3.0V ICCS — 100 30 A A CLK = CS = 0V; VCC = 5.5V CLK = CS = 0V; VCC = 3.0V DI = PE = VSS ORG = VSS or VCC High-level input voltage Standby current Note 1: This parameter is periodically sampled and not 100% tested. 1996-2012 Microchip Technology Inc. DS21130F-page 3 21130F.book Page 4 Wednesday, December 5, 2012 2:47 PM 93AA76/86 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Parameter Applicable over recommended operating ranges shown below unless otherwise noted: VCC = +1.8V to +6.0V Commercial (C): TA = 0°C to +70°C Symbol Min. Max. Units Clock frequency FCLK — 3 2 1 MHz MHz Mhz 4.5V VCC 6.0V 2.5V VCC 4.5V 1.8V VCC 2.5V Clock high time TCKH 200 300 500 — ns ns ns 4.5V VCC 6.0V 2.5V VCC 4.5V 1.8V VCC 2.5V Clock low time TCKL 100 200 500 — ns ns ns 4.5V VCC 6.0V 2.5V VCC 4.5V 1.8V VCC < 2.5V Chip select setup time TCSS 50 100 250 — ns ns ns 4.5V VCC 6.0V, Relative to CLK 2.5V VCC 4.5V, Relative to CLK 1.8V VCC 2.5V, Relative to CLK Chip select hold time TCSH 0 — ns 1.8V VCC 6.0V Chip select low time TCSL 250 — ns 1.8V VCC 6.0V, Relative to CLK Data input setup time TDIS 50 100 250 — ns ns ns 4.5V VCC 6.0V, Relative to CLK 2.5V VCC <4.5V, Relative to CLK 1.8V VCC < 2.5V, Relative to CLK Data input hold time TDIH 50 100 250 — ns ns ns 4.5V VCC 6.0V, Relative to CLK 2.5V VCC 4.5V, Relative to CLK 1.8V VCC < 2.5V, Relative to CLK Data output delay time TPD — 100 250 500 ns ns ns 4.5V VCC 6.0V, CL = 100 pF 2.5V VCC < 4.5V, CL = 100 pF 1.8V VCC < 2.5V, CL = 100 pF Data output disable time TCZ — 100 500 ns ns 4.5V VCC 5.5V (Note 1) 1.8V VCC < 4.5V (Note 1) Status valid time Tsv — 200 300 500 ns ns ns 4.5V VCC 6.0V, CL = 100 pF 2.5V VCC < 4.5V, CL = 100 pF 1.8V VCC < 2.5V, CL = 100 pF Program cycle time TWC — 5 ms Erase/Write mode TEC — 15 ms ERAL mode TWL — 30 ms WRAL mode — 1M — cycles Endurance Note 1: 2: Conditions 25°C, VCC = 5.0V, Block mode (Note 2) This parameter is periodically sampled and not 100% tested. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at: www.microchip.com DS21130F-page 4 1996-2012 Microchip Technology Inc. 21130F.book Page 5 Wednesday, December 5, 2012 2:47 PM 93AA76/86 TABLE 1-3: Instruction INSTRUCTION SET FOR 93AA76: ORG = 1 (X16 ORGANIZATION) SB Opcode READ 1 10 X A8 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 EWEN 1 00 1 1 X X X X X X X X — High-Z 13 ERASE 1 11 X A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 13 ERAL 1 00 1 0 X X X X X X X X — (RDY/BSY) 13 WRITE 1 01 X A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 29 WRAL 1 00 0 1 X X X X X X X X D15 - D0 (RDY/BSY) 29 EWDS 1 00 0 0 X X X X X X X X — High-Z 13 TABLE 1-4: Instruction Address Data In Data Out Req. CLK Cycles 29 INSTRUCTION SET FOR 93AA76: ORG = 0 (X8 ORGANIZATION) Opcode READ 1 10 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 EWEN 1 00 1 1 X X X X X X X X — High-Z 14 ERASE 1 11 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 14 ERAL 1 00 1 0 X X X X X X X X — (RDY/BSY) 14 WRITE 1 01 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 22 WRAL 1 00 0 1 X X X X X X X X D7 - D0 (RDY/BSY) 22 EWDS 1 00 0 0 X X X X X X X X — High-Z 14 TABLE 1-5: Instruction Address Data In Data Out Req. CLK Cycles SB 22 INSTRUCTION SET FOR 93AA86: ORG = 1 (X16 ORGANIZATION) SB Opcode READ 1 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 EWEN 1 00 1 1 X X X X X X X X — High-Z 13 ERASE 1 11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 13 ERAL 1 00 1 0 X X X X X X X X — (RDY/BSY) 13 WRITE 1 01 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 29 WRAL 1 00 0 1 X X X X X X X X D15 - D0 (RDY/BSY) 29 EWDS 1 00 0 0 X X X X X X X X TABLE 1-6: Instruction Address Data In — Data Out High-Z Req. CLK Cycles 29 13 INSTRUCTION SET FOR 93AA86: ORG = 0 (X8 ORGANIZATION) SB Opcode Address Data In READ 1 10 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 22 EWEN 1 00 1 — High-Z 14 ERASE 1 11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 14 ERAL 1 00 1 — (RDY/BSY) 14 WRITE 1 01 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 22 WRAL 1 00 0 1 X X X X X X X X D7 - D0 (RDY/BSY) 22 EWDS 1 00 0 0 X X X X X X X — High-Z 14 1996-2012 Microchip Technology Inc. 1 0 X X X X X X X X X X X X X X X X X Data Out Req. CLK Cycles DS21130F-page 5 21130F.book Page 6 Wednesday, December 5, 2012 2:47 PM 93AA76/86 2.0 PRINCIPLES OF OPERATION When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a high-Z state except when reading data from the device, or when checking the Ready/Busy status during a programming operation. The Ready/Busy status can be verified during an erase/write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the high-impedance state on the falling edge of the CS. 2.1 Start Condition The Start bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a Start condition is detected, CS, CLK and DI may change in any combination (except to that of a Start condition), without resulting in any device operation (Read, Write, Erase, EWEN, EWDS, ERAL and WRAL). As soon as CS is high, the device is no longer in the Standby mode. An instruction following a Start condition will only be executed if the required amount of opcode, address and data bits for any particular instruction are clocked in. 2.3 Erase/Write Enable and Disable (EWEN, EWDS) The 93AA76/86 powers up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To protect against accidental data disturb, the EWDS instruction can be used to disable all erase/write functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. 2.4 Data Protection During power-up, all programming modes of operation are inhibited until VCC has reached a level greater than 1.4V. During power-down, the source data protection circuitry acts to inhibit all programming modes when VCC has fallen below 1.4V. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become “don't care” bits until a new Start condition is detected. 2.2 DI/DO It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the read operation, if A0 is a logic high level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin. DS21130F-page 6 1996-2012 Microchip Technology Inc. 21130F.book Page 7 Wednesday, December 5, 2012 2:47 PM 93AA76/86 3.0 3.1 DEVICE OPERATION READ The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 16-bit (x16 organization) or 8-bit (x8 organization) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high and clock transitions continue. The memory address pointer will automatically increment and output data sequentially. 3.2 ERASE The ERASE instruction forces all data bits of the specified address to the logical “1” state. The self-timed programming cycle is initiated on the rising edge of CLK as the last address bit (A0) is clocked in. At this point, the CLK, CS and DI inputs become “don’t cares”. The DO pin indicates the Ready/Busy status of the device if the CS is high. The Ready/Busy status will be displayed on the DO pin until the next Start bit is received as long as CS is high. Bringing the CS low will place the device in Standby mode and cause the DO pin to enter the high-impedance state. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been erased and the device is ready for another instruction. The erase cycle takes 3 ms per word (typical). 3.3 WRITE The WRITE instruction is followed by 16 bits (or by 8 bits) of data to be written into the specified address. The self-timed programming cycle is initiated on the rising edge of CLK as the last data bit (D0) is clocked in. At this point, the CLK, CS and DI inputs become “don’t cares”. The DO pin indicates the Ready/Busy status of the device if the CS is high. The Ready/Busy status will be displayed on the DO pin until the next Start bit is received as long as CS is high. Bringing the CS low will place the device in Standby mode and cause the DO pin to enter the high-impedance state. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been written and the device is ready for another instruction. 3.4 Erase All (ERAL) The ERAL instruction will erase the entire memory array to the logical “1” state. The ERAL cycle is identical to the erase cycle except for the different opcode. The ERAL cycle is completely self-timed and commences on the rising edge of the last address bit (A0). Note that the Least Significant 8 or 9 address bits are “don’t care” bits, depending on selection of x16 or x8 mode. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The ERAL instruction is ensured at Vcc = +4.5V to +6.0V. The DO pin indicates the Ready/Busy status of the device if the CS is high. The Ready/Busy status will be displayed on the DO pin until the next Start bit is received as long as CS is high. Bringing the CS low will place the device in Standby mode and cause the DO pin to enter the high-impedance state. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the entire device has been erased and is ready for another instruction. The ERAL cycle takes 15 ms maximum (8 ms typical). 3.5 Write All (WRAL) The WRAL instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and commences on the rising edge of the last address bit (A0). Note that the Least Significant 8 or 9 address bits are “don’t cares”, depending on selection of x16 or x8 mode. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The WRAL instruction is ensured at Vcc = +4.5V to +6.0V. The DO pin indicates the Ready/Busy status of the device if the CS is high. The Ready/Busy status will be displayed on the DO pin until the next Start bit is received as long as CS is high. Bringing the CS low will place the device in Standby mode and cause the DO pin to enter the high-impedance state. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the entire device has been written and is ready for another instruction. The WRAL cycle takes 30 ms maximum (16 ms typical). The write cycle takes 3 ms per word (typical). 1996-2012 Microchip Technology Inc. DS21130F-page 7 21130F.book Page 8 Wednesday, December 5, 2012 2:47 PM 93AA76/86 FIGURE 3-1: SYNCHRONOUS DATA TIMING VIH CS TCSS VIL TCKH TCKL TCSH VIH CLK VIL TDIH TDIS VIH DI VIL DO (Read) TPD VOH VOL TCZ TPD TCZ TSV VOH DO (Program) VOL Status Valid The memory automatically cycles to the next register. FIGURE 3-2: READ TCSL CS CLK DI 1 0 AN ... A0 High-impedance DO FIGURE 3-3: 1 0 DN ... D0 DN ... D0 EWEN TCSL CS CLK DI 1 0 0 1 1 X ... X ORG = VCC, 8 X’s ORG = VSS, 9 X’s DS21130F-page 8 1996-2012 Microchip Technology Inc. 21130F.book Page 9 Wednesday, December 5, 2012 2:47 PM 93AA76/86 FIGURE 3-4: EWDS TCSL CS CLK DI 1 0 0 0 0 ... X X ORG = VCC, 8 X’s ORG = VSS, 9 X’S FIGURE 3-5: WRITE CS Standby CLK DI 1 0 AN 1 ... A0 DN ... D0 TCZ High-impedance DO Busy Ready TWC FIGURE 3-6: WRAL Standby CS CLK DI 1 0 0 0 1 X ... X DN ... D0 TCZ DO High-impedance ORG = VCC, 8 X’s ORG = VSS, 9 X’s 1996-2012 Microchip Technology Inc. Ensured at Vcc = +4.5V to +6.0V. Busy Ready TWL DS21130F-page 9 21130F.book Page 10 Wednesday, December 5, 2012 2:47 PM 93AA76/86 FIGURE 3-7: ERASE CS Standby CLK DI 1 1 1 ... AN ... A0 TCZ High-impedance DO Busy Ready TWC FIGURE 3-8: ERAL CS Standby CLK DI 1 0 0 1 0 X ... High-impedance DO X TCZ Busy Ready TEC ORG = VCC, 8 X’s ORG = VSS, 9 X’s DS21130F-page 10 Ensured at VCC = +4.5V to +6.0V. 1996-2012 Microchip Technology Inc. 21130F.book Page 11 Wednesday, December 5, 2012 2:47 PM 93AA76/86 4.0 PIN DESCRIPTIONS TABLE 4-1: PIN FUNCTION TABLE Name Chip Select CLK Serial Data Clock DI Serial Data Input DO Serial Data Output VSS Ground ORG 4.1 Function CS Note: Memory Configuration PE Program Enable VCC Power Supply Chip Select (CS) A high level selects the device. A low level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated will be completed, regardless of the CS input signal. If CS is brought low during a program cycle, the device will go into Standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a Reset status. 4.2 After detection of a Start condition the specified number of clock cycles (respectively low-to-high transitions of CLK) must be provided. These clock cycles are required to clock in all opcode, address and data bits before an instruction is executed (see Table 1-2 through Table 1-6 for more details). CLK and DI then become “don’t care” inputs waiting for a new Start condition to be detected. 4.3 CS must go low between consecutive instructions, except when performing a sequential read (Refer to Section 3.1 “READ” for more detail on sequential reads). Data In (DI) Data In is used to clock in a Start bit, opcode, address and data synchronously with the CLK input. 4.4 Data Out (DO) Data Out is used in the Read mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides Ready/Busy status information during erase and write cycles. Ready/Busy status information is available when CS is high. It will be displayed until the next Start bit occurs as long as CS stays high. Serial Clock (CLK) The Serial Clock is used to synchronize the communication between a master device and the 93AA76/86. Opcode, address and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address and data. CLK is a “don't care” if CS is low (device deselected). If CS is high, but Start condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for Start condition). 4.5 Organization (ORG) When ORG is connected to VCC, the x16 memory organization is selected. When ORG is tied to VSS, the x8 memory organization is selected. There is an internal pull-up resistor on the ORG pin that will select x16 organization when left unconnected. 4.6 Program Enable (PE) This pin allows the user to enable or disable the ability to write data to the memory array. If the PE pin is floated or tied to VCC, the device can be programmed. If the PE pin is tied to VSS, programming will be inhibited. There is an internal pull-up on this device that enables programming if this pin is left floating. CLK cycles are not required during the self-timed write (i.e., auto erase/write) cycle. 1996-2012 Microchip Technology Inc. DS21130F-page 11 21130F.book Page 12 Wednesday, December 5, 2012 2:47 PM 93AA76/86 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 8-Lead PDIP Example XXXXXXXX XXXXXNNN YYWW 93AA76 017 0410 8-Lead SOIC (.150”) XXXXXXXX XXXXYYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: DS21130F-page 12 Example 93AA86 /SN0410 017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 1996-2012 Microchip Technology Inc. 21130F.book Page 13 Wednesday, December 5, 2012 2:47 PM 93AA76/86 8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c A1 B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c § B1 B eB MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10 MAX .170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 1996-2012 Microchip Technology Inc. DS21130F-page 13 21130F.book Page 14 Wednesday, December 5, 2012 2:47 PM 93AA76/86 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1 h 45 c A2 A L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21130F-page 14 1996-2012 Microchip Technology Inc. 21130F.book Page 15 Wednesday, December 5, 2012 2:47 PM 93AA76/86 APPENDIX A: REVISION HISTORY Revision E Added note to page 1 header (Not recommended for new designs). Added Section 5.0: Package Marking Information. Added On-line Support page. Updated document format. Revision F Added a note to each package outline drawing. 1996-2012 Microchip Technology Inc. DS21130F-page 15 21130F.book Page 16 Wednesday, December 5, 2012 2:47 PM 93AA76/86 NOTES: DS21130F-page 16 1996-2012 Microchip Technology Inc. 21130F.book Page 17 Wednesday, December 5, 2012 2:47 PM 93AA76/86 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. 1996-2012 Microchip Technology Inc. DS21130F-page 17 21130F.book Page 18 Wednesday, December 5, 2012 2:47 PM 93AA76/86 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 93AA76/86 Literature Number: DS21130F Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21130F-page 18 1996-2012 Microchip Technology Inc. 21130F.book Page 19 Wednesday, December 5, 2012 2:47 PM 93AA76/86 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Device 93AA76/86: Microwire Serial EEPROM 93AA76/86T: Microwire Serial EEPROM (Tape and Reel) Temperature Range Blank = 0C to Package P SN = = PDIP Plastic SOIC (150) mil Body), 8-lead +70C Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. Your local Microchip sales office The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 1996-2012 Microchip Technology Inc. DS21130F-page 19 21130F.book Page 20 Wednesday, December 5, 2012 2:47 PM 93AA76/86 NOTES: DS21130F-page 20 1996-2012 Microchip Technology Inc. 21130F.book Page 21 Wednesday, December 5, 2012 2:47 PM Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1996-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620767405 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 1996-2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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