MICROCHIP 27LV64-25IP

27LV64
64K (8K x 8) Low-Voltage CMOS EPROM
PACKAGE TYPES
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
PGM
NC
A8
A9
A11
OE
A10
CE
O7
O6
O5
O4
O3
30
31
1
32
2
5
29
6
28
7
8
9
10
27
26
25
24
A8
A9
A11
NC
OE
A10
CE
O7
O6
20
19
21
18
22
13
17
23
12
16
11
15
A6
A5
A4
A3
A2
A1
A0
NC
O0
3
4
A7
A12
VPP
NU
Vcc
PGM
NC
PLCC
14
The Microchip Technology Inc. 27LV64 is a low-voltage
(3.0 volt) CMOS EPROM designed for battery powered
applications. The device is organized as 8K x 8 (8KByte) non-volatile memory product. The 27LV64 consumes only 8mA maximum of active current during a
3.0 volt read operation therefore improving battery performance. This device is designed for very low voltage
applications where conventional 5.0 volt only EPROMs
can not be used. Accessing individual bytes from an
address transition or from power-up (chip enable pin
going low) is accomplished in less than 200 ns at
3.0V.This device allows system designers the ability to
use low voltage non-volatile memory with today’s low
voltage microprocessors and peripherals in battery
powered applications.
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
VSS
27LV64
DESCRIPTION
DIP/SOIC
27LV64
• Wide voltage range 3.0V to 5.5V
• High speed performance
- 200 ns access time available at 3.0V
• CMOS Technology for low power consumption
- 8 mA active current at 3.0V
- 20 mA active current at 5.5V
- 100 µA standby current
• Factory programming available
• Auto-insertion-compatible plastic packages
• Auto ID aids automated programming
• Separate chip enable and output enable controls
• High speed “express” programming algorithm
• Organized 8K x 8: JEDEC standard pinouts
- 28-pin Dual-in-line package
- 32-pin PLCC Package
- 28-pin SOIC package
- Tape and reel
• Available for the following temperature ranges:
- Commercial:
0˚C to +70˚C
- Industrial:
-40˚C to +85˚C
O1
O2
VSS
NU
O3
O4
O5
FEATURES
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount applications, PLCC or SOIC packaging is available. Tape
and reel packaging is also available for PLCC or SOIC
packages.
 1996 Microchip Technology Inc.
DS11024E-page 1
This document was created with FrameMaker 4 0 4
27LV64
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
TABLE 1-1:
PIN FUNCTION TABLE
Name
Function
VCC and input voltages w.r.t. VSS ....... -0.6V to + 7.25V
A0-A12
VPP voltage w.r.t. VSS during
programming .......................................... -0.6V to +14V
CE
Chip Enable
OE
Output Enable
Voltage on A9 w.r.t. VSS ...................... -0.6V to +13.5V
Address Inputs
Output voltage w.r.t. VSS ............... -0.6V to VCC +1.0V
PGM
Program Enable
Storage temperature .......................... -65˚C to +150˚C
VPP
Programming Voltage
Ambient temp. with power applied ..... -65˚C to +125˚C
O0 - O7
*Notice: Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any
other conditions above those indicated in the operation listings of
this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
VCC
+5V Or +3V Power Supply
VSS
Ground
NC
No Connection; No Internal Connections
NU
Not Used; No External Connection Is
Allowed
TABLE 1-2:
Data Output
READ OPERATION DC CHARACTERISTICS
VCC = 3.0V to 5.5V unless otherwise specified
Commercial:
Tamb = 0˚C to +70˚C
Industrial:
Tamb = -40˚C to +85˚C
Parameter
Part*
Status
Symbol
Min.
Max.
Units
Conditions
Input Voltages
all
Logic "1"
Logic "0"
VIH
VIL
2.0
-0.5
VCC+1
0.8
V
V
Input Leakage
all
—
ILI
-10
10
µA
VIN = 0 to VCC
Output Voltages
all
Logic "1"
Logic "0"
VOH
VOL
2.4
0.45
V
V
IOH = -400 µA
IOL = 2.1 mA
Output Leakage
all
—
ILO
-10
10
µA
VOUT = 0V to VCC
Input Capacitance
all
—
CIN
—
6
pF
VIN = 0V; Tamb = 25°C;
f = 1 MHz
Output Capacitance
all
—
COUT
—
12
pF
VOUT = 0V; Tamb = 25°C;
f = 1 MHz
Power Supply Current,
Active
C
TTL input
ICC1
—
I
TTL input
ICC2
—
20 @ 5.0V
8 @ 3.0V
25 @ 5.0V
10 @ 3.0V
mA
mA
mA
mA
VCC = 5.5V; VPP = VCC
f = 1 MHz;
OE = CE = VIL;
IOUT = 0 mA;
VIL = -0.1 to 0.8V;
VIH = 2.0 to VCC;
Note 1
C
I
all
TTL input
TTL input
CMOS input
ICC(S)
—
1 @ 3.0V
[email protected] 3.0V
100 @ 3.0V
mA
mA
µA
Power Supply Current,
Standby
CE = VCC ± 0.2V
* Parts: C=Commercial Temperature Range; I=Industrial Temperature Range
Note 1: Typical active current increases .5 mA per MHz up to operating frequency for all temperature ranges.
DS11024E-page 2
 1996 Microchip Technology Inc.
27LV64
TABLE 1-3:
READ OPERATION AC CHARACTERISTICS
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
27LV64-20
Parameter
VIH = 2.4V and VIL = 0.45V; VOH = 2.0V VOL = 0.8V
1 TTL Load + 100 pF
10 ns
Commercial:
Tamb = 0˚C to +70˚C
Industrial:
Tamb = -40˚C to +85˚C
27LV64-25
27LV64-30
Sym
Units
Min.
Max.
Min.
Max.
Min.
Max.
Conditions
Address to Output Delay
tACC
—
200
—
250
—
300
ns
CE = OE = VIL
CE to Output Delay
tCE
—
200
—
250
—
300
ns
OE = VIL
OE to Output Delay
tOE
—
100
—
125
—
125
ns
CE = VIL
CE or OE to O/P High
Impedance
tOFF
0
50
0
50
0
50
ns
Output Hold from Address CE or
OE, whichever goes first
tOH
0
—
0
—
0
—
ns
FIGURE 1-1:
READ WAVEFORMS
VIH
Address Valid
Address
VIL
VIH
CE
VIL
t CE(2)
VIH
OE
VIL
Outputs
O0 - O7
VOH
t OFF(1,3)
t OH
t OE(2)
High Z
Valid Output
High Z
VOL
t ACC
Notes: (1) tOFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to t CE - t OE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested.
 1996 Microchip Technology Inc.
DS11024E-page 3
27LV64
TABLE 1-4:
PROGRAMMING DC CHARACTERISTICS
Ambient Temperature: Tamb = 25°C ± 5°C
VCC = 6.5V ± 0.25V, VPP = VH = 13.0V ± 0.25V
Parameter
Status
Symbol
Min.
Max.
Units
Input Voltages
Logic”1”
Logic”0”
VIH
VIL
2.0
-0.1
VCC+1
0.8
V
V
Input Leakage
—
ILI
-10
10
µA
VIN = 0V to VCC
Logic”1”
Logic”0”
VOH
VOL
2.4
0.45
V
V
IOH = -400 µA
IOL = 2.1 mA
VCC Current, program & verify
—
ICC2
—
20
mA
Note 1
VPP Current, program
—
IPP2
—
25
mA
Note 1
A9 Product Identification
—
VH
11.5
12.5
V
Output Voltages
Conditions
Note 1: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
TABLE 1-5:
PROGRAMMING AC CHARACTERISTICS
for Program, Program Verify
and Program Inhibit Modes
Parameter
AC Testing Waveform: VIH=2.4V and VIL=0.45V; VOH=2.0V; VOL=0.8V
Ambient Temperature: Tamb=25°C ± 5°C
VCC= 6.5V ± 0.25V, VPP = VH = 13.0V ± 0.25V
Symbol
Min.
Max.
Units
Address Set-Up Time
tAS
2
—
µs
Data Set-Up Time
tDS
2
—
µs
Data Hold Time
tDH
2
—
µs
Address Hold Time
tAH
0
—
µs
Float Delay (2)
tDF
0
130
ns
VCC Set-Up Time
tVCS
2
—
µs
Program Pulse Width (1)
tPW
95
105
µs
CE Set-Up Time
tCES
2
—
µs
OE Set-Up Time
tOES
2
—
µs
VPP Set-Up Time
tVPS
2
—
µs
Data Valid from OE
tOE
100
ns
Remarks
100 µs typical
Note 1: For express algorithm, initial programming width tolerance is 100 µs ±5%.
Note 2: This parameter is only sampled and not 100% tested. Output float is defined as the point where data is no
longer driven (see timing diagram).
DS11024E-page 4
 1996 Microchip Technology Inc.
27LV64
FIGURE 1-2:
PROGRAMMING WAVEFORMS (1)
Program
Verify
VIH
Address Stable
Address
VIL
tAS
t AH
VIH
High Z
Data
Data In Stable
VIL
Data Out Valid
t DF
(2)
t DH
t DS
13.0 V (3)
V PP
tVPS
5.0 V
6.5 V (3)
V CC
tVCS
5.0 V
VIH
CE
VIL
tCES
VIH
PGM
VIL
t OES
tPW
t OE
(2)
VIH
OE
tOPW
VIL
Notes: (1) The input timing reference is 0.8V for V IL and 2.0V for VIH .
(2) t DF and tOE are characteristics of the device but must be accommodated by the programmer.
(3) Vcc = 6.5V ±0.25V, V PP = VH = 13.0V ±0.25V for Express algorithm.
TABLE 1-6:
MODES
Operation Mode
CE
OE
PGM
VPP
A9
O0 - O7
Read
VIL
VIL
VIH
VCC
X
DOUT
Program
VIL
VIH
VIL
VH
X
DIN
Program Verify
VIL
VIL
VIH
VH
X
DOUT
Program Inhibit
VIH
X
X
VH
X
High Z
Standby
VIH
X
X
VCC
X
High Z
Output Disable
VIL
VIH
VIH
VCC
X
High Z
Identity
VIL
VIL
VIH
VCC
VH
Identity Code
X = Don’t Care
1.2
Read Mode
(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when
a)
b)
For Read operations, if the addresses are stable, the
address access time (tACC) is equal to the delay from
CE to output (tCE). Data is transferred to the output
after a delay from the falling edge of OE (tOE).
the CE pin is low to power up (enable) the chip
the OE pin is low to gate the data to the output
pins
 1996 Microchip Technology Inc.
DS11024E-page 5
27LV64
1.3
Standby Mode
The standby mode is defined when the CE pin is high
(VIH) and a program mode is not defined.
When these conditions are met, the supply current will
drop from 20 mA to 100 µA.
1.4
Output Enable
This feature eliminates bus contention in microprocessor-based systems in which multiple devices may drive
the bus. The outputs go into a high impedance state
when the following condition is true:
• The OE and PGM pins are both high.
1.5
Erase Mode (U.V. Windowed Versions)
Windowed products offer the capability to erase the
memory array. The memory matrix is erased to the all
1’s state when exposed to ultraviolet light. To ensure
complete erasure, a dose of 15 watt-second/cm2 is
required. This means that the device window must be
placed within one inch and directly underneath an ultraviolet lamp with a wavelength of 2537 Angstroms,
intensity of 12,000µW/cm2 for approximately 20 minutes.
1.6
Programming Mode
The Express Algorithm has been developed to improve
the programming throughput times in a production
environment. Up to ten 100-microsecond pulses are
applied until the byte is verified. No overprogramming
is required. A flowchart of the express algorithm is
shown in Figure 1-3.
Programming takes place when:
a)
b)
c)
d)
e)
VCC is brought to the proper voltage,
VPP is brought to the proper VH level,
the CE pin is low,
the OE pin is high, and
the PGM pin is low.
Since the erased state is “1” in the array, programming
of “0” is required. The address to be programmed is set
via pins A0-A12 and the data to be programmed is presented to pins O0-O7. When data and address are stable, OE is high, CE is low and a low-going pulse on the
PGM line programs that location.
DS11024E-page 6
1.7
Verify
After the array has been programmed it must be verified to ensure all the bits have been correctly programmed. This mode is entered when all the following
conditions are met:
a)
b)
c)
d)
e)
VCC is at the proper level,
VPP is at the proper VH level,
the CE line is low,
the PGM line is high, and
the OE line is low.
1.8
Inhibit
When programming multiple devices in parallel with different data, only CE or PGM need be under separate
control to each device. By pulsing the CE or PGM line
low on a particular device in conjunction with the PGM
or CE line low, that device will be programmed; all other
devices with CE or PGM held high will not be programmed with the data, although address and data will
be available on their input pins (i.e., when a high level
is present on CE or PGM); and the device is inhibited
from programming.
1.9
Identity Mode
In this mode specific data is output which identifies the
manufacturer as Microchip Technology Inc. and device
type. This mode is entered when Pin A9 is taken to VH
(11.5V to 12.5V). The CE and OE lines must be at VIL.
A0 is used to access any of the two non-erasable bytes
whose data appears on O0 through O7.
Pin
Identity
Manufacturer
Device Type*
Input
Output
H
e
x
A0
0 O O O O O O O
7 6 5 4 3 2 1 0
VIL
VIH
0 0 1 0 1 0 0 1 29
0 0 0 0 0 0 1 0 02
* Code subject to change
 1996 Microchip Technology Inc.
27LV64
FIGURE 1-3:
PROGRAMMING EXPRESS ALGORITHM
Conditions:
Tamb = 25˚C ±5˚C
VCC = 6.5 ±0.25V
VPP = 13.0 ±0.25V
Start
ADDR = First Location
VCC = 6.5V
VPP = 13.0V
X=0
Program one 100 µs pulse
Increment X
Verify
Byte
Pass
Fail
No
X = 10 ?
Last
Address?
Yes
Device
Failed
Yes
No
Increment Address
VCC = VPP = 4.5V, 5.5V
Device
Passed
 1996 Microchip Technology Inc.
Yes
All
bytes
= original
data?
No
Device
Failed
DS11024E-page 7
27LV64
NOTES:
DS11024E-page 8
 1996 Microchip Technology Inc.
27LV64
NOTES:
 1996 Microchip Technology Inc.
DS11024E-page 9
27LV64
NOTES:
DS11024E-page 10
 1996 Microchip Technology Inc.
27LV64
27LV64 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
27LV64
–
25
I
/P
Package:
Temperature
Range:
Access
Time:
Device:
 1996 Microchip Technology Inc.
L =
P =
SO =
Blank =
I =
20 =
25 =
30 =
27LV64
Plastic Leaded Chip Carrier
Plastic DIP (600 Mil)
Plastic SOIC (300 Mil)
0˚C to +70˚C
–40˚C to +85˚C
200 ns
250 ns
300 ns
64K (8K x 8) Low-Voltage CMOS EPROM
DS11024E-page 11
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Tel: 81 45 471 6166 Fax: 81 45 471 6122
9/3/96
All rights reserved.  1996, Microchip Technology Incorporated, USA. 9/96
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS11024E-page 12
 1996 Microchip Technology Inc.