TI CD74HCT299E

[ /Title
(CD74
HC299
,
CD74
HCT29
9)
/Subject
(High
Speed
CMOS
Logic
8-Bit
Universal
Shift
CD54HC299, CD74HC299,
CD54HCT299, CD74HCT299
Data sheet acquired from Harris Semiconductor
SCHS178C
January 1998 - Revised May 2003
High-Speed CMOS Logic
8-Bit Universal Shift Register; Three-State
Features
Description
The ’HC259 and ’HCT299 are 8-bit shift/storage registers
with three-state bus interface capability. The register has four
synchronous-operating modes controlled by the two select
inputs as shown in the mode select (S0, S1) table. The mode
select, the serial data (DS0, DS7) and the parallel data (I/O0
- I/O7) respond only to the low-to-high transition of the clock
(CP) pulse. S0, S1 and data inputs must be stable one setup time prior to the clock positive transition.
• Buffered Inputs
• Four Operating Modes: Shift Left, Shift Right, Load
and Store
• Can be Cascaded for N-Bit Word Lengths
• I/O0 - I/O7 Bus Drive Capability and Three-State for
Bus Oriented Applications
• Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC
The Master Reset (MR) is an asynchronous active low input.
When MR output is low, the register is cleared regardless of
the status of all other inputs. The register can be expanded
by cascading same units by tying the serial output (Q0) to
the serial data (DS7) input of the preceding register, and
tying the serial output (Q7) to the serial data (DS0) input of
the following register. Recirculating the (n x 8) bits is
accomplished by tying the Q7 of the last stage to the DS0 of
the first stage.
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
The three-state input/output I(/O) port has three modes of
operation:
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
1. Both output enable (OE1 and OE2) inputs are low and S0
or S1 or both are low, the data in the register is presented
at the eight outputs.
2. When both S0 and S1 are high, I/O terminals are in the
high impedance state but being input ports, ready for parallel data to be loaded into eight registers with one clock
transition regardless of the status of OE1 and OE2.
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
3. Either one of the two output enable inputs being high will
force I/O terminals to be in the off-state. It is noted that
each I/O terminal is a three-state output and a CMOS
buffer input.
Pinout
Ordering Information
CD54HC299, CD54HCT299
(CERDIP)
CD74HC299, CD74HCT299
(PDIP, SOIC)
TOP VIEW
TEMP. RANGE (oC)
PACKAGE
CD54HC299F3A
-55 to 125
20 Ld CERDIP
CD54HCT299F3A
-55 to 125
20 Ld CERDIP
CD74HC299E
-55 to 125
20 Ld PDIP
CD74HC299M
-55 to 125
20 Ld SOIC
PART NUMBER
S0
1
20 VCC
OE1
2
19 S1
OE2
3
18 DS7
I/O6
4
17 Q7
CD74HC299M96
-55 to 125
20 Ld SOIC
I/O4
5
16 I/O7
CD74HCT299E
-55 to 125
20 Ld PDIP
I/O2
6
15 I/O5
CD74HCT299M
-55 to 125
20 Ld SOIC
I/O0
7
14 I/O3
Q0
8
13 I/O1
CD74HCT299M96
-55 to 125
20 Ld SOIC
MR
9
12 CP
GND 10
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
11 DS0
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Functional Diagram
CP OE1 OE2
12
2 3
MR
9
20
THREESTATE
CONTROL
VCC
7
I/O 0
I/O 2
BUS LINE
OUTPUTS
I/O
THREE-STATE
OUTPUTS
6
5
SHIFT
REGISTER
I/O
THREE-STATE
OUTPUTS
I/O 4
4
I/O 6
8
STANDARD
OUTPUT Q0
1
S0
MODE SELECTION
10
GND
13
I/O 1
14
I/O 3
BUS LINE
15
I/O 5 OUTPUTS
16
I/O7
17
STANDARD
Q7 OUTPUT
19
S1
11
18
DS0 DS7
MODE SELECT FUNCTION TABLE THREE-STATE I/O PORT OPERATING MODE
INPUTS
FUNCTION
INPUTS/OUTPUTS
OE1
OE2
S0
S1
Qn (REGISTER)
I/O0 --- I/O7
L
L
L
X
L
L
L
L
L
X
H
H
L
L
X
L
L
L
L
L
X
L
H
H
Load Register
X
X
H
H
Qn = I/On
I/On = Inputs
Disable I/O
H
X
X
X
X
(Z)
X
H
X
X
X
(Z)
Read Register
TRUTH TABLE
INPUTS
REGISTER OUTPUTS
FUNCTION
MR
CP
S0
S1
DS0
DS7
I/On
Q0
Q1
---
Q6
Q7
RESET (CLEAR)
L
X
X
X
X
X
X
L
L
---
L
L
H
↑
h
l
l
X
X
L
q0
---
q5
q6
H
↑
h
l
h
X
X
H
q0
---
q5
Q6
H
↑
l
h
X
l
X
q1
q2
---
q7
L
H
↑
l
h
X
h
X
q1
q2
---
q7
H
Hold (Do Nothing)
H
↑
l
l
X
X
X
q0
q1
---
q6
q7
Parallel Load
H
↑
h
h
X
X
l
L
L
---
L
L
H
↑
h
h
X
X
h
H
H
---
H
H
Shift Right
Shift Left
H = Input Voltage High Level, h = Input voltage high one set-up timer prior clock transition; L = Input Voltage Low Level; l = Input voltage
low one set-up time prior to clock transition; qn = Lower case letter indicates the state of the reference output one set-up time prior to clock
transition; X - Voltage level on logic status don’t care; Z = Output in high impedance state, ↑ = Low to High Clock Transition.
2
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO, For -0.5V < VO < VCC + 0.5V
For Q Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
For I/O Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
SYMBOL
VI (V)
IO (mA)
High Level Input
Voltage
VIH
-
-
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
PARAMETER
VCC
(V)
25oC
-40oC TO 85oC -55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
HC TYPES
-
-
VIH or VIL
High Level Output
Voltage
TTL Loads
-0.02
VOL
Input Leakage
Current
VCC or
GND
-
1.5
-
1.5
-
V
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
2
1.9
-
-
1.9
-
1.9
-
V
4.5
4.4
-
-
4.4
-
4.4
-
V
6
5.9
-
-
5.9
-
5.9
-
V
I/On
-
-
-
-
-
-
-
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
-7.8
0.02
6
5.48
-
-
5.34
-
5.2
-
V
2
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.1
-
0.1
-
0.1
V
6
-
-
0.1
-
0.1
-
0.1
V
I/On
-
-
-
-
-
-
-
-
V
4
6
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
7.8
6
-
-
0.26
-
0.33
-
0.4
V
6
-
-
±0.1
-
±1
-
±1
µA
Qn
II
-
-4
VIH or VIL
Low Level Output
Voltage
TTL Loads
1.5
3.15
Qn
-5.2
Low Level Output
Voltage
CMOS Loads
2
4.5
-
3
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
25oC
-40oC TO 85oC -55oC TO 125oC
PARAMETER
SYMBOL
VI (V)
IO (mA)
VCC
(V)
Quiescent Device
Current
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
-
6
-
-
±0.5
-
±5
-
±10
µA
Three- State Leak- VIL or VIH VO = VCC
or GND
age Current
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
HCT TYPES
High Level Input
Voltage
VIH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
VIL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
VOH
VIH or VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
±0.1
-
±1
-
±1
µA
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
II
VCC and
GND
0
5.5
-
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
-
6
-
-
±0.5
-
±5
-
±10
µA
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
Three- State Leak- VIL or VIH VO = VCC
age Current
or GND
Additional Quiescent Device Current Per
Input Pin: 1 Unit
Load
∆ICC
(Note 2)
VCC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
S1, MR
0.25
I/O0 - I/O7
0.25
DS0, DS7
0.25
S0, CP
0.6
OE1, OE2
0.3
NOTE: Unit Load is ∆ICC limit specific in Static Specifications Table,
e.g., 360µA max. at 25oC.
4
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Prerequisite for Switching Specifications
25oC
PARAMETER
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
fMAX
2
6
-
-
5
-
-
4
-
-
MHz
4.5
30
-
-
25
-
-
20
-
-
MHz
6
35
-
-
29
-
-
23
-
-
MHz
2
50
-
-
65
-
-
75
-
-
ns
4.5
10
-
-
13
-
-
15
-
-
ns
6
9
-
-
11
-
-
13
-
-
ns
2
80
-
-
100
-
-
120
-
-
ns
4.5
16
-
-
20
-
-
24
-
-
ns
6
14
-
-
17
-
-
20
-
-
ns
2
100
-
-
125
-
-
150
-
-
ns
4.5
20
-
-
25
-
-
30
-
-
ns
6
17
-
-
21
-
-
26
-
-
ns
2
0
-
-
0
-
-
0
-
-
ns
4.5
0
-
-
0
-
-
0
-
-
ns
6
0
-
-
0
-
-
0
-
-
ns
2
5
-
-
5
-
-
5
-
-
ns
4.5
5
-
-
5
-
-
5
-
-
ns
6
5
-
-
5
-
-
5
-
-
ns
2
120
-
-
150
-
-
180
-
-
ns
4.5
24
-
-
30
-
-
36
-
-
ns
6
20
-
-
26
-
-
31
-
-
ns
HC TYPES
Maximum Clock
Frequency
MR Pulse Width
Clock Pulse Width
Setup Time
DS0, DS7, I/On to Clock
Hold Time DS0, DS7,
I/On, S0, S1 to Clock
Recovery Time
MR to Clock
Setup Time
S1, S0 to Clock
tW
tW
tSU
tH
tREC
tSU
HCT TYPES
Maximum Clock
Frequency
fMAX
4.5
25
-
-
20
-
-
16
-
-
MHz
MR Pulse Width
tW
4.5
15
-
-
19
-
-
22
-
-
ns
Clock Pulse Width
tW
4.5
20
-
-
25
-
-
30
-
-
ns
Setup Time DS0, DS7,
I/On, S0, S1 to Clock
tSU
4.5
20
-
-
25
-
-
30
-
-
ns
Hold Time DS0, DS7,
I/On, S0, S1 to Clock
tH
4.5
0
-
-
0
-
-
0
-
-
ns
Recovery Time MR to
Clock
tREC
4.5
5
-
-
5
-
-
5
-
-
ns
Setup Time S1, S0 to
Clock
tSU
4.5
27
-
-
34
-
-
41
-
-
ns
5
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Switching Specifications
CL = 50pF, Input tr, tf = 6ns
-40oC TO
85oC
25oC
PARAMETER
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
-55oC TO
125oC
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
200
-
250
-
300
ns
4.5
-
-
40
-
50
-
60
ns
CL = 15pF
5
-
17
-
-
-
-
-
ns
CL = 50pF
6
-
-
34
-
43
-
51
ns
CL = 15pF
5
-
10
-
-
-
-
-
ns
tPZH, tPLZ
-
13
-
-
-
-
-
ns
tPHZ
-
15
-
-
-
-
-
ns
2
-
-
155
-
195
-
235
ns
4.5
-
-
31
-
39
-
47
ns
6
-
-
26
-
33
-
40
ns
2
-
-
185
-
230
-
280
ns
4.5
-
-
37
-
46
-
56
ns
6
-
-
31
-
39
-
48
ns
2
-
-
155
-
195
-
235
ns
4.5
-
-
31
-
39
-
47
ns
6
-
-
26
-
33
-
40
ns
2
-
-
130
-
165
-
195
ns
4.5
-
-
26
-
33
-
39
ns
6
-
-
22
-
28
-
33
ns
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
2
-
-
60
-
75
-
90
ns
4.5
-
-
12
-
15
-
18
ns
6
-
-
10
-
13
-
15
ns
HC TYPES
Propagation Delay
Clock to I/O Output,
Clock to Q0 and Q7,
MR to Output
Output Enable and Disable
Times
Output High-Z to High Level
Output High Level to High-Z
Output Low Level to High-Z
Output High-Z to Low Level
Output Transition Time
tPZL
tPZH
tPHZ
tPLZ
tPZL
tTHL, tTLH
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
Q0, Q7
I/O0 to I/O7
tTHL, tTLH
CL = 50pF
Input Capacitance
CI
CL = 50pF
-
10
-
10
-
10
-
10
pF
Three-State Output
Capacitance
CO
-
-
20
-
20
-
20
-
20
pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
CL = 15pF
5
-
150
-
-
-
-
-
pF
6
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Switching Specifications
CL = 50pF, Input tr, tf = 6ns (Continued)
-40oC TO
85oC
25oC
PARAMETER
SYMBOL
-55oC TO
125oC
TEST
CONDITIONS
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
CL = 50pF
4.5
-
-
45
-
56
-
68
ns
CL = 15pF
5
-
19
-
-
-
-
-
ns
HCT TYPES
Propagation Delay
tPHL, tPLH
Clock to I/O Output,
Clock to Q0 and Q7
MR to Output
tPHL, tPLH
CL = 50pF
4.5
-
-
46
-
58
-
69
ns
Output Enable and Disable
Times
tPZL,tPZH,
tPLZ, tPHZ
CL = 15pF
5
-
10,
13, 15
-
-
-
-
-
ns
Output High-Z to High Level
tPZH
CL = 50pF
4.5
-
-
32
-
40
-
48
ns
Output High Level to High-Z
tPHZ
CL = 50pF
4.5
-
-
37
-
46
-
56
ns
Output Low Level to High-Z
tPLZ
CL = 50pF
4.5
-
-
32
-
40
-
48
ns
Output High-Z to Low Level
tPZL
CL = 50pF
4.5
-
-
30
-
38
-
45
ns
Q0, Q7
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
I/O0 to I/O7
CL = 50pF
4.5
-
-
12
-
15
-
18
ns
Output Transition Time
tTLH, tTHL
Input Capacitance
CIN
CL = 50pF
-
10
-
10
-
10
-
10
pF
Three-State Output
Capacitance
CO
-
-
20
-
20
-
20
-
20
pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
CL = 15pF
5
-
170
-
-
-
-
-
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per register.
4. PD = CPD VCC2 fi + ∑ (CL VCC2 fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance,
VCC = Supply Voltage.
Test Circuits and Waveforms
tfCL
trCL
CLOCK
90%
10%
tWL + tWH =
I
fCL
tWL
50%
tfCL = 6ns
I
fCL
3V
VCC
50%
10%
tWL + tWH =
trCL = 6ns
CLOCK
50%
2.7V
0.3V
GND
1.3V
0.3V
tWL
tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
1.3V
1.3V
GND
tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
7
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Test Circuits and Waveforms
tr = 6ns
(Continued)
tf = 6ns
90%
50%
10%
INPUT
GND
tTLH
90%
INVERTING
OUTPUT
tPHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
trCL
VCC
90%
GND
tH(H)
3V
2.7V
1.3V
0.3V
GND
tH(H)
tH(L)
VCC
DATA
INPUT
DATA
INPUT
50%
tH(L)
3V
1.3V
1.3V
1.3V
GND
tSU(H)
tSU(H)
tSU(L)
tTLH
90%
OUTPUT
tTHL
90%
50%
10%
tTLH
90%
1.3V
OUTPUT
tREM
3V
SET, RESET
OR PRESET
GND
tTHL
1.3V
10%
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
tPHL
1.3V
GND
IC
CL
50pF
GND
90%
tPLH
50%
IC
tSU(L)
tPHL
tPLH
tREM
VCC
SET, RESET
OR PRESET
tfCL
CLOCK
INPUT
50%
10%
tPLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tfCL
trCL
tTLH
1.3V
10%
tPLH
tPHL
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
CLOCK
INPUT
tf = 6ns
tr = 6ns
VCC
CL
50pF
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
8
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Test Circuits and Waveforms
6ns
(Continued)
6ns
OUTPUT
DISABLE
tr
VCC
90%
50%
10%
OUTPUTS
ENABLED
OUTPUT HIGH
TO OFF
50%
OUTPUTS
DISABLED
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
IC WITH
THREESTATE
OUTPUT
GND
1.3V
tPZH
90%
OUTPUTS
ENABLED
OUTPUTS
ENABLED
0.3
10%
tPHZ
tPZH
90%
3V
tPZL
tPLZ
OUTPUT LOW
TO OFF
50%
OUTPUT HIGH
TO OFF
6ns
GND
10%
tPHZ
tf
2.7
1.3
tPZL
tPLZ
OUTPUT LOW
TO OFF
6ns
OUTPUT
DISABLE
1.3V
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OUTPUT
RL = 1kΩ
CL
50pF
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZH
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to
VCC, CL = 50pF.
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
9
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-8780601RA
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
5962-8943601MRA
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
CD54HC299F
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
CD54HC299F3A
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
CD54HCT299F3A
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
CD74HC299E
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC299EE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC299M
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC299M96
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC299M96E4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC299M96G4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC299ME4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC299MG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT299E
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HCT299EE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HCT299M
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT299M96
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT299M96E4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT299M96G4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT299ME4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT299MG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD74HC299M96
DW
20
SITE 41
330
24
10.8
13.0
2.7
12
24
Q1
CD74HCT299M96
DW
20
SITE 41
330
24
10.8
13.0
2.7
12
24
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
CD74HC299M96
DW
20
SITE 41
346.0
346.0
41.0
CD74HCT299M96
DW
20
SITE 41
346.0
346.0
41.0
Pack Materials-Page 2
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