MCP3905/06 Energy-Metering ICs with Active (Real) Power Pulse Output Features Description • Supplies active (real) power measurement for single-phase, residential energy-metering • Supports the IEC 62053 International Energy Metering Specification and legacy IEC 1036/61036/687 Specifications • Two multi-bit, Digital-to-Analog Converters (DACs), second-order, 16-bit, Delta-Sigma Analog-to-Digital Converters (ADCs) • 0.1% typical measurement error over 500:1 dynamic range (MCP3905) • 0.1% typical measurement error over 1000:1 dynamic range (MCP3906) • Programmable Gain Amplifier (PGA) for smallsignal inputs supports low-value shunt current sensor - 16:1 PGA - MCP3905 - 32:1 PGA - MCP3906 • Ultra-low drift on-chip reference: 15 ppm/°C (typ.) • Direct drive for electromagnetic mechanical counter and two-phase stepper motors • Low IDD of 4 mA (typ.) • Tamper output pin for negative power indication • Industrial Temperature Range: -40°C to +85°C • Supplies instantaneous active (real) power on HFOUT for meter calibration The MCP3905/06 devices are energy-metering ICs designed to support the IEC 62053 International Metering Standard Specification. They supply a frequency output proportional to the average active (real) power, as well as a higher-frequency output proportional to the instantaneous power for meter calibration. They include two 16-bit, delta-sigma ADCs for a wide range of IB and IMAX currents and/or small shunt (< 200 µOhms) meter designs. It includes an ultra-low drift voltage reference with < 15 ppm/°C through a specially designed band gap temperature curve for the minimum gradient across the industrial temperature range. A fixed-function DSP block is onchip for active (real) power calculation. Strong output drive for mechanical counters are on-chip to reduce field failures and mechanical counter sticking. A noload threshold block prevents any current creep measurements. A Power-On Reset (POR) block restricts meter performance during low-voltage situations. These accurate energy-metering ICs with high field reliability are available in the industry-standard pinout. Package Type DVDD HPF AVDD NC CH0+ CH0CH1CH1+ MCLR REFIN/OUT AGND F2 24-Pin SSOP US Patents Pending 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FOUT0 FOUT1 HFOUT DGND NEG NC OSC2 OSC1 G0 G1 F0 F1 Functional Block Diagram G0 G1 HPF OSC1 OSC2 HFOUT CH0+ CH0- + PGA – 16-bit Multi-level ΔΣ ADC REFIN/ OUT X 2.4V Reference CH1+ + CH1- – © 2007 Microchip Technology Inc. F2 HPF1 16-bit Multi-level ΔΣ ADC HPF1 F1 F0 FOUT0 FOUT1 NEG E-to-F conversion LPF1 POR MCLR DS21948D-page 1 MCP3905/06 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † VDD ...................................................................................7.0V Digital inputs and outputs w.r.t. AGND ........ -0.6V to VDD +0.6V Analog input w.r.t. AGND ..................................... ....-6V to +6V VREF input w.r.t. AGND ............................... -0.6V to VDD +0.6V Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................-65°C to +125°C Soldering temperature of leads (10 seconds) ............. +300°C ESD on the analog inputs (HBM,MM) .................5.0 kV, 500V † Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ESD on all other pins (HBM,MM) ........................5.0 kV, 500V ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V, Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C. Parameter Sym Overall Measurement Accuracy Energy Measurement Error E Min Typ. — 0.1 — 0.1 Max Units Comment % FOUT Channel 0 swings 1:500 range, MCP3905 only (Note 1, Note 4) — % FOUT Channel 0 swings 1:1000 range, MCP3906 only (Note 1, Note 4) — % FOUT Disabled when F2, F1, F0 = 0, 1, 1 Max (Note 5, Note 6) 1/MCLK s HPF = 0 and 1, < 1 MCLK (Note 4, Note 6, Note 7) — % FOUT F2, F1, F0 = 0, 1, 1 (Note 3) — No-Load Threshold/ NLT — 0.0015 Minimum Load Phase Delay Between — — Channels AC Power Supply AC PSRR — 0.01 Rejection Ratio (Output Frequency Variation) DC Power Supply DC PSRR — 0.01 — % FOUT HPF = 1, Gain = 1 (Note 3) Rejection Ratio (Output Frequency Variation) System Gain Error — 3 10 % FOUT Note 2, Note 5 ADC/PGA Specifications — 2 5 mV Referred to Input Offset Error VOS Gain Error Match — 0.5 — % FOUT Note 8 Internal Voltage Reference Voltage — 2.4 — V Tolerance — ±2 — % Tempco — 15 — ppm/°C Note 1: Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 65 Hz. See Section 2.0 “Typical Performance Curves” for higher frequencies and increased dynamic range. 2: Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between measured output frequency and expected transfer function. 3: Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @ 50 Hz, CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V ±500 mV. 4: Error applies down to 60° lead (PF = 0.5 capacitive) and 60° lag (PF = 0.5 inductive). 5: Refer to Section 4.0 “Device Overview” for complete description. 6: Specified by characterization, not production tested. 7: 1 MCLK period at 3.58 MHz is equivalent to less than <0.005 degrees at 50 or 60 Hz. 8: Gain error match is measured from CH0 G = 1 to any other gain setting. DS21948D-page 2 © 2007 Microchip Technology Inc. MCP3905/06 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V, Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C. Parameter Sym Min Typ. Max Units Comment Reference Input Input Range 2.2 — 2.6 V Input Impedance 3.2 — — kΩ Input Capacitance — — 10 pF Analog Inputs Maximum Signal Level — — ±1 V CH0+,CH0-,CH1+,CH1- to AGND Differential Input Voltage — — ±470/G mV G = PGA Gain on Channel 0 Range Channel 0 Differential Input Voltage — — ±660 mV Range Channel 1 Input Impedance 390 — — kΩ Proportional to 1/MCLK frequency Bandwidth — 14 — kHz Proportional to MCLK frequency, (Notch Frequency) MCLK/256 Oscillator Input Frequency Range MCLK 1 — 4 MHz Power Specifications Operating Voltage 4.5 — 5.5 V AVDD, DVDD IDD,A IDD,A — 2.7 3.0 mA AVDD pin only IDD,D IDD,D — 1.2 2.0 mA DVDD pin only Note 1: Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 65 Hz. See Section 2.0 “Typical Performance Curves” for higher frequencies and increased dynamic range. 2: Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between measured output frequency and expected transfer function. 3: Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @ 50 Hz, CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V ±500 mV. 4: Error applies down to 60° lead (PF = 0.5 capacitive) and 60° lag (PF = 0.5 inductive). 5: Refer to Section 4.0 “Device Overview” for complete description. 6: Specified by characterization, not production tested. 7: 1 MCLK period at 3.58 MHz is equivalent to less than <0.005 degrees at 50 or 60 Hz. 8: Gain error match is measured from CH0 G = 1 to any other gain setting. TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = 4.5V – 5.5V, AGND, DGND = 0V. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 — +85 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Conditions Temperature Ranges Note: Note The MCP3905/06 operate over this extended temperature range, but with reduced performance. In any case, the Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C. © 2007 Microchip Technology Inc. DS21948D-page 3 MCP3905/06 TIMING CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V, AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C. Parameter Sym Min Typ Max Units Comment FOUT0 and FOUT1 Pulse Width (Logic-Low) tFW — 275 — ms 984376 MCLK periods (Note 1) HFOUT Pulse Width tHW — 90 — ms 322160 MCLK periods (Note 2) Frequency Output FOUT0 and FOUT1 Pulse Period tFP Refer to Equation 4-1 s HFOUT Pulse Period tHP Refer to Equation 4-2 s FOUT0 to FOUT1 Falling-Edge Time tFS2 — 0.5 tFP — FOUT0 to FOUT1 Min Separation tFS — 4/MCLK — FOUT0 and FOUT1 Output High Voltage VOH 4.5 — — V IOH = 10 mA, DVDD = 5.0V FOUT0 and FOUT1 Output Low Voltage VOL — — 0.5 V IOL = 10 mA, DVDD = 5.0V HFOUT Output High Voltage VOH 4.0 — — V IOH = 5 mA, DVDD = 5.0V HFOUT Output Low Voltage VOL — — 0.5 V IOL = 5 mA, DVDD = 5.0V High-Level Input Voltage (All Digital Input Pins) VIH 2.4 — — V DVDD = 5.0V Low-Level Input Voltage (All Digital Input Pins) VIL — — 0.85 V DVDD = 5.0V Input Leakage Current — — µA VIN = 0, VIN = DVDD Pin Capacitance — — pF Note 3 Note 1: 2: 3: ±3 10 If output pulse period (tFP) falls below 984376*2 MCLK periods, then tFW = 1/2 tFP. If output pulse period (tHP) falls below 322160*2 MCLK periods, then tHW = 1/2 tHP. Specified by characterization, not production tested. tFP tFW FOUT0 tFS tFS2 FOUT1 tHW HFOUT tHP NEG FIGURE 1-1: DS21948D-page 4 Output Timings for Pulse Outputs and Negative Power Pin. © 2007 Microchip Technology Inc. MCP3905/06 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.0000 0.6 +85°C Measurement Error Measurement Error Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode), MCLK = 3.58 MHz. +25°C -40°C 0.5 0.4 0.2 0.1 -0.1 0.0001 0.0010 0.0100 -0.3 0.0000 0.1000 Measurement Error, +25°C 0.1 0 -0.1 - 40°C Measurement Error Measurement Error 0.3 0.2 -0.2 0.0001 0.0010 0.0100 0.1000 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.0000 FIGURE 2-2: Measurement Error, Gain = 16, PF = 1. +25°C 0.2 0 - 40°C -0.2 -0.4 -0.6 0.0100 CH1 Vp-p Amplitude (V) FIGURE 2-3: Measurement Error, Gain = 32, PF = 1. © 2007 Microchip Technology Inc. 0.1000 Measurement Error +85°C 0.4 0.0010 0.1000 +85°C +25°C -40°C 0.0001 0.0010 0.0100 0.1000 FIGURE 2-5: Measurement Error, Gain = 16, PF = 0.5. 0.8 0.0001 0.0100 CH1 Vp-p Amplitude (V) CH1 Vp-p Amplitude (V) 0.6 0.0010 FIGURE 2-4: Measurement Error, Gain = 8, PF = 0.5. +85°C 0.4 0.0001 CH1 Vp-p Amplitude (V) 0.5 Measurement Error -40°C -0.2 FIGURE 2-1: Gain = 8, PF = 1. -0.8 0.0000 +25°C 0 CH1 Vp-p Amplitude (V) -0.3 0.0000 +85°C 0.3 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0.0000 +85°C +25°C -40°C 0.0001 0.0010 0.0100 0.1000 CH1 Vp-p Amplitude (V) FIGURE 2-6: Measurement Error, Gain = 32, PF = 0.5. DS21948D-page 5 MCP3905/06 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.0001 Measurement Error Measurement Error Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode), MCLK = 3.58 MHz. +85°C +25°C - 40°C 0.0010 0.0100 0.1000 1.0000 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.0001 CH0 Vp-p Amplitude (V) 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.0001 Measurement Error, +25°C - 40°C 0.0100 0.1000 CH0 Vp-p Amplitude (V) FIGURE 2-8: Gain = 2, PF = 1. DS21948D-page 6 -40°C 0.0010 0.0100 0.1000 1.0000 FIGURE 2-9: Measurement Error, Gain = 1, PF = + 0.5. +85°C 0.0010 +25°C CH1 Vp-p Amplitude (V) Measurement Error Measurement Error FIGURE 2-7: Gain = 1, PF = 1. +85°C Measurement Error, 1.0000 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.0001 +85°C +25°C -40°C 0.0010 0.0100 0.1000 1.0000 CH1 Vp-p Amplitude (V) FIGURE 2-10: Measurement Error, Gain = 2, PF = + 0.5. © 2007 Microchip Technology Inc. MCP3905/06 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 PF = 0.5 Occurance PF = 1.0 45 50 55 60 65 70 4000 3500 3000 2500 2000 1500 1000 500 0 16384 Samples Mean = - 1.28 mV Std. dev = - 18.1 µV -1.38E-03 -1.37E-03 -1.36E-03 -1.35E-03 -1.34E-03 -1.33E-03 -1.32E-03 -1.31E-03 -1.30E-03 -1.29E-03 -1.28E-03 -1.27E-03 -1.26E-03 -1.25E-03 -1.24E-03 -1.23E-03 -1.22E-03 % Error Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode), MCLK = 3.58 MHz. 75 Frequency (Hz) FIGURE 2-11: Input Frequency. Bin (mV) Measurement Error vs. FIGURE 2-14: Channel 0 Offset Error (DC Mode, HPF Off), G = 16. 3000 2000 0.3 16384 Samples Mean = -1.57 mV Std. Dev = 52.5 µV Measurement Error Occurance 2500 1500 1000 500 0.2 0.1 VDD=5.0V 0 -0.1 -0.2 VDD=4.5V -0.3 VDD=5.5V -0.4 -0.5 0.0001 -1.38 -1.43 -1.47 -1.52 -1.56 -1.61 -1.65 -1.70 -1.75 0 0.0010 Channel 0 Offset (mV) FIGURE 2-15: (G = 16). 1200 600 400 200 -1.59 -1.60 -1.62 -1.63 -1.64 -1.65 -1.66 -1.67 -1.68 -1.69 0 -1.71 0.1000 1.0000 Measurement Error vs. VDD 0.3 0.25 16384 Samples Mean = -1.64 mV Std. Dev = 17.4 µV Measurement Error Occurance 800 0.0100 CH0 Vp-p Amplitude (V) FIGURE 2-12: Channel 0 Offset Error (DC Mode, HPF off), G = 1. 1000 VDD=4.75V VDD=5.25V Channel 0 Offset (mV) FIGURE 2-13: Channel 0 Offset Error (DC Mode, HPF off), G = 8. © 2007 Microchip Technology Inc. 0.2 0.15 VDD=4.75V VDD=4.5V 0.1 0.05 0 VDD=5.0V VDD=5.25V -0.05 -0.1 -0.15 0.0001 VDD=5.5V 0.0010 0.0100 0.1000 1.0000 CH0 Vp-p Amplitude (V) FIGURE 2-16: Measurement Error vs. VDD, G = 16, External VREF . DS21948D-page 7 MCP3905/06 0.3 0.3 0.2 0.2 0.1 +85°C 0 +25°C - 40°C -0.1 -0.2 -0.3 0.0001 0.0010 0.0100 0.1000 1.0000 CH0 Vp-p Amplitude (V) Measurement Error Measurement Error Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode), MCLK = 3.58 MHz. +85°C +25°C 0.1 0 - 40°C -0.1 -0.2 -0.3 0.0000 0.0001 0.0010 0.0100 0.1000 CH1 Vp-p Amplitude (V) FIGURE 2-17: Measurement Error w/ External VREF, (G = 1). FIGURE 2-19: Measurement Error w/ External VREF (G = 16). Measurement Error 0.3 0.2 +85°C 0.1 +25°C 0 -40°C -0.1 -0.2 -0.3 0.0000 0.0001 0.0010 0.0100 0.1000 CH1 Vp-p Amplitude (V) FIGURE 2-18: Measurement Error w/ External VREF, (G = 8). DS21948D-page 8 © 2007 Microchip Technology Inc. MCP3905/06 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: 3.1 PIN FUNCTION TABLE Pin No. Symbol Function 1 DVDD Digital Power Supply Pin 2 HPF High-Pass Filters Control Logic Pin 3 AVDD 4 NC 5 CH0+ Non-Inverting Analog Input Pin for Channel 0 (Current Channel) 6 CH0- Inverting Analog Input Pin for Channel 0 (Current Channel) Analog Power Supply Pin No Connect 7 CH1- Inverting Analog Input Pin for Channel 1 (Voltage Channel) 8 CH1+ Non-Inverting Analog Input Pin for Channel 1 (Voltage Channel) 9 MCLR Master Clear Logic Input Pin 10 REFIN/OUT Voltage Reference Input/Output Pin Analog Ground Pin, Return Path for internal analog circuitry 11 AGND 12 F2 Frequency Control for HFOUT Logic Input Pin 13 F1 Frequency Control for FOUT0/1 Logic Input Pin 14 F0 Frequency Control for FOUT0/1 Logic Input Pin 15 G1 Gain Control Logic Input Pin 16 G0 Gain Control Logic Input Pin 17 OSC1 Oscillator Crystal Connection Pin or Clock Input Pin 18 OSC2 Oscillator Crystal Connection Pin or Clock Output Pin 19 NC 20 NEG Negative Power Logic Output Pin No Connect 21 DGND Digital Ground Pin, Return Path for Internal Digital Circuitry 22 HFOUT High-Frequency Logic Output Pin (Intended for Calibration) 23 FOUT1 Differential Mechanical Counter Logic Output Pin 24 FOUT0 Differential Mechanical Counter Logic Output Pin Digital VDD (DVDD) DVDD is the power supply pin for the digital circuitry within the MCP3905/06. DVDD requires appropriate bypass capacitors and should be maintained to 5V ±10% for specified operation. Please refer to Section 5.0 “Applications Information”. 3.2 High-Pass Filter Input Logic Pin (HPF) HPF controls the state of the high-pass filter in both input channels. A logic ‘1’ enables both filters, removing any DC offset coming from the system or the device. A logic ‘0’ disables both filters, allowing DC voltages to be measured. 3.3 Analog VDD (AVDD) AVDD is the power supply pin for the analog circuitry within the MCP3905/06. AVDD requires appropriate bypass capacitors and should be maintained to 5V ±10% for specified operation. Please refer to Section 5.0 “Applications Information”. 3.4 Current Channel (CH0-, CH0+) CH0- and CH0+ are the fully differential analog voltage input channels for the current measurement, containing a PGA for small-signal input, such as shunt currentsensing. The linear and specified region of this channel is dependant on the PGA gain. This corresponds to a maximum differential voltage of ±470 mV/GAIN and maximum absolute voltage, with respect to AGND, of ±1V. Up to ±6V can be applied to these pins without the risk of permanent damage. Refer to Section 1.0 “Electrical Characteristics”. © 2007 Microchip Technology Inc. DS21948D-page 9 MCP3905/06 3.5 Voltage Channel (CH1-,CH1+) CH1- and CH1+ are the fully differential analog voltage input channels for the voltage measurement. The linear and specified region of these channels have a maximum differential voltage of ±660mV and a maximum absolute voltage of ±1V, with respect to AGND. Up to ±6V can be applied to these pins without the risk of permanent damage. Refer to Section 1.0 “Electrical Characteristics”. 3.6 Master Clear (MCLR) MCLR controls the reset for both delta-sigma ADCs, all digital registers, the SINC filters for each channel and all accumulators post multiplier. A logic ‘0’ resets all registers and holds both ADCs in a Reset condition. The charge stored in both ADCs is flushed and their output is maintained to 0x0000h. The only block consuming power on the digital power supply during Reset is the oscillator circuit. 3.7 Reference (REFIN/OUT) REFIN/OUT is the output for the internal 2.4V reference. This reference has a typical temperature coefficient of 15 ppm/°C and a tolerance of ±2%. In addition, an external reference can also be used by applying voltage to this pin within the specified range. REFIN/OUT requires appropriate bypass capacitors to AGND, even when using the internal reference only. Refer to Section 5.0 “Applications Information”. 3.8 Analog Ground (AGND) AGND is the ground connection to the internal analog circuitry (ADCs, PGA, band gap reference, POR). To ensure accuracy and noise cancellation, this pin must be connected to the same ground as DGND, preferably with a star connection. If an analog ground plane is available, it is recommended that this device be tied to this plane of the Printed Circuit Board (PCB). This plane should also reference all other analog circuitry in the system. 3.9 Frequency Control Logic Pins (F2, F1, F0) F2, F1 and F0 select the high-frequency output and low-frequency output pin ranges by changing the value of the constants FC and HFC used in the device transfer function. FC and HFC are the frequency constants that define the period of the output pulses for the device. 3.10 Gain Control Logic Pins (G1, G0) G1 and G0 select the PGA gain on Channel 0 from three different values: 1, 8 and 16. DS21948D-page 10 3.11 Oscillator (OSC1, OSC2) OSC1 and OSC2 provide the master clock for the device. A resonant crystal or clock source with a similar sinusoidal waveform must be placed across these pins to ensure proper operation. The typical clock frequency specified is 3.579545 MHz. However, the clock frequency can be with the range of 1 MHz to 4 MHz without disturbing measurement error. Appropriate load capacitance should be connected to these pins for proper operation. A full-swing, single-ended clock source may be connected to OSC1 with proper resistors in series to ensure no ringing of the clock source due to fast transient edges. 3.12 Negative Power Output Logic Pin (NEG) NEG detects the phase difference between the two channels and will go to a logic ‘1’ state when the phase difference is greater than 90° (i.e., when the measured active (real) power is negative). The output state is synchronous with the rising-edge of HFOUT and maintains the logic ‘1’ until the active (real) power becomes positive again and HFOUT shows a pulse. 3.13 Ground Connection (DGND) DGND is the ground connection to the internal digital circuitry (SINC filters, multiplier, HPF, LPF, Digital-toFrequency (DTF) converter and oscillator). To ensure accuracy and noise cancellation, DGND must be connected to the same ground as AGND, preferably with a star connection. If a digital ground plane is available, it is recommended that this device be tied to this plane of the PCB. This plane should also reference all other digital circuitry in the system. 3.14 High-Frequency Output (HFOUT) HFOUT is the high-frequency output of the device and supplies the instantaneous real-power information. The output is a periodic pulse output, with its period proportional to the measured active (real) power, and to the HFC constant defined by F0, F1 and F2 pin logic states. This output is the preferred output for calibration due to faster output frequencies, giving smaller calibration times. Since this output gives instantaneous active (real) power, the 2ω ripple on the output should be noted. However, the average period will show minimal drift. 3.15 Frequency Output (FOUT0, FOUT1) FOUT0 and FOUT1 are the frequency outputs of the device that supply the average real-power information. The outputs are periodic pulse outputs, with its period proportional to the measured active (real) power, and to the Fc constant, defined by the F0 and F1 pin logic states. These pins include high-output drive capability for direct use of electromechanical counters and 2phase stepper motors. Since this output supplies average active (real) power, any 2ω ripple on the output pulse period is minimal. © 2007 Microchip Technology Inc. MCP3905/06 4.0 DEVICE OVERVIEW The instantaneous power signal contains the realpower information; it is the DC component of the instantaneous power. The averaging technique can be used with both sinusoidal and non-sinusoidal waveforms, as well as for all power factors. The instantaneous power is thus low-pass filtered in order to produce the instantaneous real-power signal. The MCP3905/06 is an energy-metering IC that supplies a frequency output proportional to active (real) power, and higher frequency output proportional to the instantaneous power for meter calibration. Both channels use 16-bit, second-order, delta-sigma ADCs that oversample the input at a frequency equal to MCLK/4, allowing for wide dynamic range input signals. A Programmable Gain Amplifier (PGA) increases the usable range on the current input channel (Channel 0). The calculation of the active (real) power, as well as the filtering associated with this calculation, is performed in the digital domain, ensuring better stability and drift performance. Figure 4-1 represents the simplified block diagram of the MCP3905/06, detailing its main signal-processing blocks. A DTF converter accumulates the instantaneous active (real) power information to produce output pulses with a frequency proportional to the average active (real) power. The low-frequency pulses presented at the FOUT0 and FOUT1 outputs are designed to drive electromechanical counters and two-phase stepper motors displaying the real-power energy consumed. Each pulse corresponds to a fixed quantity of real energy, selected by the F2, F1 and F0 logic settings. The HFOUT output has a higher frequency setting and lower integration period such that it can represent the instantaneous active (real) power signal. Due to the shorter accumulation time, it enables the user to proceed to faster calibration under steady load conditions (refer to Section 4.7 “FOUT0/1 and HFOUT Output Frequencies”). Two digital high-pass filters cancel the system offset on both channels such that the real-power calculation does not include any circuit or system offset. After being high-pass filtered, the voltage and current signals are multiplied to give the instantaneous power signal. This signal does not contain the DC offset components, such that the averaging technique can be efficiently used to give the desired active (real) power output. MCP3905/06 CH0+ + CH0- – PGA ΔΣ ADC ANALOG HPF X DIGITAL ..0101... LPF CH1+ + CH1- – ΔΣ ADC FOUT0 FOUT1 HFOUT DTF HPF Frequency Content 0 Input Signal with System Offset and Line Frequency FIGURE 4-1: 0 ADC Output Code Contains System and ADC Offset 0 DC Offset Removed by HPF 0 Instantaneous Power 0 Instantaneous Active (Real) Power Simplified MCP3905/06 Block Diagram with Frequency Contents. © 2007 Microchip Technology Inc. DS21948D-page 11 MCP3905/06 Analog Inputs The MCP3905/06 analog inputs can be connected directly to the current and voltage transducers (such as shunts or current transformers). Each input pin is protected by specialized Electrostatic Discharge (ESD) structures that are certified to pass 5 kV HBM and 500V MM contact charge. These structures also allow up to ±6V continuous voltage to be present at their inputs without the risk of permanent damage. Both channels have fully differential voltage inputs for better noise performance. The absolute voltage at each pin relative to AGND should be maintained in the ±1V range during operation in order to ensure the measurement error performance. The common mode signals should be adapted to respect both the previous conditions and the differential input voltage range. For best performance, the common mode signals should be referenced to AGND. The current channel comprises a PGA on the front-end to allow for smaller signals to be measured without additional signal conditioning. The maximum differential voltage specified on Channel 0 is equal to ±470 mV/Gain (see Table 4-1). The maximum peak voltage specified on Channel 1 is equal to ±660 mV. TABLE 4-1: The clocking signals for the ADCs are equally distributed between the two channels in order to minimize phase delays to less than 1 MCLK period (see Section 3.2 “High-Pass Filter Input Logic Pin (HPF)”). The SINC filters main notch is positioned at MCLK/256 (14 kHz with MCLK = 3.58 MHz), allowing the user to be able to measure wide harmonic content on either channel. The magnitude response of the SINC filter is shown in Figure 4-2. MCP3905 GAIN SELECTIONS G1 G0 CH0 Gain Maximum CH0 Voltage 0 0 1 1 0 1 0 1 1 2 8 16 ±470 mV ±235 mV ±60 mV ±30 mV TABLE 4-2: MCP3906 GAIN SELECTIONS G1 G0 CH0 Gain Maximum CH0 Voltage 0 0 1 1 0 1 0 1 1 32 8 16 ±470 mV ±15 mV ±60 mV ±30 mV 4.2 Both ADCs have a 16-bit resolution, allowing wide input dynamic range sensing. The oversampling ratio of both converters is 64. Both converters are continuously converting during normal operation. When the MCLR pin is low, both converters will be in Reset and output code 0x0000h. If the voltage at the inputs of the ADC is larger than the specified range, the linearity is no longer specified. However, the converters will continue to produce output codes until their saturation point is reached. The DC saturation point is around 700 mV for Channel 0 and 1V for Channel 1, using internal voltage reference. Normal Mode Rejection (dB) 4.1 16-Bit Delta-Sigma ADCs The ADCs used in the MCP3905/06 for both current and voltage channel measurements are delta-sigma ADCs. They comprise a second-order, delta-sigma modulator using a multi-bit DAC and a third-order SINC filter. The delta-sigma architecture is very appropriate for the applications targeted by the MCP3905, because it is a waveform-oriented converter architecture that can offer both high linearity and low distortion performance throughout a wide input dynamic range. It also creates minimal requirements for the anti-aliasing filter design. The multi-bit architecture used in the ADC minimizes quantization noise at the output of the converters without disturbing the linearity. DS21948D-page 12 0 -20 -40 -60 -80 -100 -120 0 5 10 15 20 25 30 Frequency (kHz) FIGURE 4-2: SINC Filter Magnitude Response (MCLK = 3.58 MHz). 4.3 Ultra-Low Drift VREF The MCP3905/06 contains an internal voltage reference source specially designed to minimize drift over temperature. This internal VREF supplies reference voltage to both current and voltage channel ADCs. The typical value of this voltage reference is 2.4V, ±100 mV. The internal reference has a very low typical temperature coefficient of ±15 ppm/°C, allowing the output frequencies to have minimal variation with respect to temperature since they are proportional to (1/VREF)². REFIN/OUT is the output pin for the voltage reference. Appropriate bypass capacitors must be connected to the REFIN/OUT pin for proper operation (see Section 5.0 “Applications Information”). The voltage reference source impedance is typically 4 kΩ, which enables this voltage reference to be overdriven by an external voltage reference source. © 2007 Microchip Technology Inc. MCP3905/06 4.4 Power-On Reset (POR) The MCP3905/06 contains an internal POR circuit that monitors analog supply voltage AVDD during operation. This circuit ensures correct device startup at system power-up/power-down events. The POR circuit has built-in hysteresis and a timer to give a high degree of immunity to potential ripple and noise on the power supplies, allowing proper settling of the power supply during power-up. A 0.1 µF decoupling capacitor should be mounted as close as possible to the AVDD pin, providing additional transient immunity (see Section 5.0 “Applications Information”). The threshold voltage is typically set at 4V, with a tolerance of about ±5%. If the supply voltage falls below this threshold, the MCP3905/06 will be held in a Reset condition (equivalent to applying logic ‘0’ on the MCLR pin). The typical hysteresis value is approximately 200 mV in order to prevent glitches on the power supply. Once a power-up event has occurred, an internal timer prevents the part from outputting any pulse for approximately 1s (with MCLK = 3.58 MHz), thereby preventing potential metastability due to intermittent resets caused by an unsettled regulated power supply. Figure 4-3 illustrates the different conditions for a power-up and a power-down event in the typical conditions. AVDD 5V 4.2V 4V 1s 0V DEVICE MODE RESET FIGURE 4-3: NO PULSE OUT 4.5 High-Pass Filters and Multiplier The active (real) power value is extracted from the DC instantaneous power. Therefore, any DC offset component present on Channel 0 and Channel 1 affects the DC component of the instantaneous power and will cause the real-power calculation to be erroneous. In order to remove DC offset components from the instantaneous power signal, a high-pass filter has been introduced on each channel. Since the highpass filtering introduces phase delay, identical highpass filters are implemented on both channels. The filters are clocked by the same digital signal, ensuring a phase difference between the two channels of less than one MCLK period. Under typical conditions (MCLK = 3.58 MHz), this phase difference is less than 0.005°, with a line frequency of 50 Hz. The cut-off frequency of the filter (4.45 Hz) has been chosen to induce minimal gain error at typical line frequencies, allowing sufficient settling time for the desired applications. The two high-pass filters can be disabled by applying a logic ‘0’ to the HPF pin. Normal Mode Rejection (dB) If an external voltage reference source is connected to the REFIN/OUT pin, the external voltage will be used as the reference for both current and voltage channel ADCs. The voltage across the source resistor will then be the difference between the internal and external voltage. The allowed input range for the external voltage source goes from 2.2V to 2.6V for accurate measurement error. A VREF value outside of this range will cause additional heating and power consumption due to the source resistor, which might affect measurement error. 0 -5 -10 -15 -20 -25 -30 -35 -40 0.1 1 10 100 1000 Frequency (Hz) FIGURE 4-4: HPF Magnitude Response (MCLK = 3.58 MHz). The multiplier output gives the product of the two highpass-filtered channels, corresponding to instantaneous active (real) power. Multiplying two sine wave signals by the same ω frequency gives a DC component and a 2ω component. The instantaneous power signal contains the active (real) power of its DC component, while also containing 2ω components coming from the line frequency multiplication. These 2ω components come for the line frequency (and its harmonics) and must be removed in order to extract the real-power information. This is accomplished using the low-pass filter and DTF converter. Time PROPER OPERATION RESET Power-on Reset Operation. © 2007 Microchip Technology Inc. DS21948D-page 13 MCP3905/06 4.6 Low-Pass Filter and DTF Converter The MCP3905/06 low-pass filter is a first-order IIR filter that extracts the active (real) power information (DC component) from the instantaneous power signal. The magnitude response of this filter is detailed in Figure 45. Due to the fact that the instantaneous power signal has harmonic content (coming from the 2ω components of the inputs), and since the filter is not ideal, there will be some ripple at the output of the low-pass filter at the harmonics of the line frequency. Normal Mode Rejection (dB) The cut-off frequency of the filter (8.9 Hz) has been chosen to have sufficient rejection for commonly-used line frequencies (50 Hz and 60 Hz). With a standard input clock (MCLK = 3.58 MHz) and a 50 Hz line frequency, the rejection of the 2ω component (100 Hz) will be more than 20 dB. This equates to a 2ω component containing 10 times less power than the main DC component (i.e., the average active (real) power). The output of the low-pass filter is accumulated in the DTF converter. This accumulation is compared to a different digital threshold for FOUT0/1 and HFOUT, representing a quantity of real energy measured by the part. Every time the digital threshold on FOUT0/1 or HFOUT is crossed, the part will output a pulse (See Section 4.7 “FOUT0/1 and HFOUT Output Frequencies”). The equivalent quantity of real energy required to output a pulse is much larger for the FOUT0/1 outputs than the HFOUT. This is such that the integration period for the FOUT0/1 outputs is much larger. This larger integration period acts as another low-pass filter so that the output ripple due to the 2ω components is minimal. However, these components are not totally removed, since realized low-pass filters are never ideal. This will create a small jitter in the output frequency. Averaging the output pulses with a counter or a Microcontroller Unit (MCU) in the application will then remove the small sinusoidal content of the output frequency and filter out the remaining 2ω ripple. HFOUT is intended to be used for calibration purposes due to its instantaneous power content. The shorter integration period of HFOUT demands that the 2ω component be given more attention. Since a sinusoidal signal average is zero, averaging the HFOUT signal in steady-state conditions will give the proper real energy value. 0 -5 -10 -15 -20 -25 -30 -35 -40 0.1 1 10 100 1000 Frequency (Hz) FIGURE 4-5: LPF Magnitude Response (MCLK = 3.58 MHz). DS21948D-page 14 © 2007 Microchip Technology Inc. MCP3905/06 4.7 FOUT0/1 and HFOUT Output Frequencies The thresholds for the accumulated energy are different for FOUT0/1 and HFOUT (i.e., they have different transfer functions). The FOUT0/1 allowed output frequencies are quite low in order to allow superior integration time (see Section 4.6 “Low-Pass Filter and DTF Converter”). The FOUT0/1 output frequency can be calculated with the following equation: EQUATION 4-1: For a given DC input V, the DC and RMS values are equivalent. For a given AC input signal with peak-topeak amplitude of V, the equivalent RMS value is V/sqrt(2), assuming purely sinusoidal signals. Note that since the active (real) power is the product of two RMS inputs, the output frequencies of an AC signal is half that of the DC equivalent signal, again assuming purely sinusoidal AC signals. The constant FC depends on the FOUT0 and FOUT1 digital settings. Table 4-3 shows FOUT0/1 output frequencies for the different logic settings. FOUT FREQUENCY OUTPUT EQUATION 8.06 × V0 × V 1 × G × F C F OUT ( Hz ) = ---------------------------------------------------------2 ( VREF ) Where: V0 = the RMS differential voltage on Channel 0 V1 = the RMS differential voltage on Channel 1 G = the PGA gain on Channel 0 (current channel) FC = the frequency constant selected VREF = the voltage reference TABLE 4-3: OUTPUT FREQUENCY CONSTANT FC FOR FOUT0/1 (VREF = 2.4V) F1 F0 FC (Hz) FC (Hz) (MCLK = 3.58 MHz) FOUT Frequency (Hz) with Full-Scale DC Inputs FOUT Frequency (Hz) with Full-Scale AC Inputs 0 0 MCLK/221 1.71 0.74 0.37 0 1 20 MCLK/2 3.41 1.48 0.74 1 0 MCLK/219 6.83 2.96 1.48 1 18 13.66 5.93 2.96 1 MCLK/2 © 2007 Microchip Technology Inc. DS21948D-page 15 MCP3905/06 MINIMAL OUTPUT FREQUENCY FOR NO-LOAD THRESHOLD The high-frequency output HFOUT has lower integration times and, thus, higher frequencies. The output frequency value can be calculated with the following equation: EQUATION 4-2: The MCP3905/06 also includes, on each output frequency, a no-load threshold circuit that will eliminate any creep effects in the meter. The outputs will not show any pulse if the output frequency falls below the no-load threshold. The minimum output frequency on FOUT0/1 and HFOUT is equal to 0.0015% of the maximum output frequency (respectively FC and HFC) for each of the F2, F1 and F0 selections (see Table 4-3 and Table 4-4); except when F2, F1, F0 = 011. In this last configuration, the no-load threshold feature is disabled. The selection of FC will determine the start-up current load. In order to respect the IEC standards requirements, the meter will have to be designed to allow start-up currents compatible with the standards by choosing the FC value matching these requirements. For additional applications information on no-load threshold, startup current and other meter design points, refer to AN994, "IEC Compliant Active Energy Meter Design Using The MCP3905/6”, (DS00994). HFOUT FREQUENCY OUTPUT EQUATION 8.06 × V0 × V 1 × G × HFC HF OUT ( Hz ) = --------------------------------------------------------------2 ( VREF ) Where: V0 = the RMS differential voltage on Channel 0 V1 = the RMS differential voltage on Channel 1 G = the PGA gain on Channel 0 (current channel) FC = the frequency constant selected VREF = the voltage reference The constant HFC depends on the FOUT0 and FOUT1 digital settings with the Table 4-4. The detailed timings of the output pulses are described in the Timing Characteristics table (see Section 1.0 “Electrical Characteristics” and Figure 1-1). TABLE 4-4: OUTPUT FREQUENCY CONSTANT HFC FOR HFOUT (VREF = 2.4V) F2 F1 F0 HFC HFC (Hz) HFC (Hz) (MCLK = 3.58 MHz) HFOUT Frequency (Hz) with full-scale AC Inputs 0 0 0 64 x FC MCLK/215 109.25 27.21 0 0 1 32 x FC MCLK/215 109.25 27.21 0 1 0 16 x FC MCLK/215 109.25 27.21 2048 x FC MCLK/27 27968.75 6070.12 128 x FC MCLK/216 219.51 47.42 0 1 1 0 1 0 1 0 1 64 x FC MCLK/216 219.51 47.42 1 1 0 32 x FC MCLK/216 219.51 47.42 16 x FC 16 219.51 47.42 1 1 DS21948D-page 16 1 MCLK/2 © 2007 Microchip Technology Inc. MCP3905/06 5.0 APPLICATIONS INFORMATION 5.1 Meter Design using the MCP3905/06 For all applications information, refer to AN994, "IEC Compliant Active Energy Meter Design Using The MCP3905/6” (DS00994). This application note includes all required energy meter design information, including the following: • • • • • • • • • • • • Meter rating and current sense choices Shunt design PGA selection F2, F1, F0 selection Meter calibration Anti-aliasing filter design Compensation for parasitic shunt inductance EMC design Power supply design No-load threshold Start-up current Accuracy testing results from MCP3905-based meter • EMC testing results from MCP3905-based meter © 2007 Microchip Technology Inc. DS21948D-page 17 MCP3905/06 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 24-Lead SSOP Examples: XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: DS21948D-page 18 MCP3905 e3 I/SS^^ 0739256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007 Microchip Technology Inc. MCP3905/06 24-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 1 2 NOTE 1 b e c φ A2 A A1 L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 24 Pitch e Overall Height A – 0.65 BSC – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.20 Molded Package Width E1 5.00 5.30 5.60 Overall Length D 7.90 8.20 8.50 Foot Length L 0.55 0.75 0.95 Footprint L1 1.25 REF Lead Thickness c 0.09 – Foot Angle φ 0° 4° 0.25 8° Lead Width b 0.22 – 0.38 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-132B © 2007 Microchip Technology Inc. DS21948D-page 19 MCP3905/06 NOTES: DS21948D-page 20 © 2007 Microchip Technology Inc. MCP3905/06 APPENDIX A: REVISION HISTORY Revision A (July 2005) Original Release of this Document. Revision B (August 2005) Replace Figures 2-1 thru 2-6 in Section 2.0 “Typical Performance Curves” Revision C (October 2005) Added references to MCP3905/06 throughout document. Revision D (February 2007) This revision includes updates to the packaging diagrams. © 2007 Microchip Technology Inc. DS21948D-page 21 MCP3905/06 NOTES: DS21948D-page 22 l © 2007 Microchip Technology Inc. MCP3905/06 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. –X /XX Device Temperature Range Package Device: MCP3905: MCP3905T: MCP3906: MCP3906T: Energy-Metering IC Energy-Metering IC (Tape and Reel) Energy-Metering IC Energy-Metering IC (Tape and Reel) Examples: a) b) Industrial Temperature, 24LD SSOP. MCP3905T-I/SS: Tape and Reel, Industrial Temperature, 24LD SSOP. a) MCP3906-I/SS: b) Temperature Range: I = -40°C to +85°C Package: SS = Plastic Shrink Small Outline (209 mil Body), 24-lead © 2007 Microchip Technology Inc. MCP3905-I/SS: Industrial Temperature, 24LD SSOP. MCP3906T-I/SS: Tape and Reel, Industrial Temperature, 24LD SSOP. DS21948D-page 23 MCP3905/06 NOTES: DS21948D-page 24 © 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. 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