MICROCHIP MCP4801T-E/SN

MCP4801/4811/4821
8/10/12-Bit Voltage Output Digital-to-Analog Converter
with Internal VREF and SPI Interface
Features
Description
•
•
•
•
•
•
The MCP4801/4811/4821 devices are single channel
8-bit, 10-bit and 12-bit buffered voltage output
Digital-to-Analog Converters (DACs), respectively. The
devices operate from a single 2.7V to 5.5V supply with
an SPI compatible Serial Peripheral Interface.
The devices have a high precision internal voltage
reference (VREF = 2.048V). The user can configure the
full-scale range of the device to be 2.048V or 4.096V by
setting the Gain Selection Option bit (gain of 1 of 2).
The devices can be operated in Active or Shutdown
mode by setting a Configuration register bit or using the
SHDN pin. In Shutdown mode, most of the internal
circuits, including the output amplifier, are turned off for
power savings, while the amplifier output (VOUT) stage is
configured to present a known high resistance output
load (500 k typical.
The devices include double-buffered registers,
allowing a synchronous update of the DAC output
using the LDAC pin. These devices also incorporate a
Power-on Reset (POR) circuit to ensure reliable powerup.
The devices utilize a resistive string architecture, with
its inherent advantages of low DNL error, low ratio
metric temperature coefficient and fast settling time.
These devices are specified over the extended
temperature range (+125°C).
The devices provide high accuracy and low noise
performance for consumer and industrial applications
where calibration or compensation of signals (such as
temperature, pressure and humidity) are required.
The MCP4801/4811/4821 devices are available in the
PDIP, SOIC, MSOP and DFN packages.
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•
•
•
•
•
MCP4801: 8-Bit Voltage Output DAC
MCP4811: 10-Bit Voltage Output DAC
MCP4821: 12-Bit Voltage Output DAC
Rail-to-Rail Output
SPI Interface with 20 MHz Clock Support
Simultaneous Latching of the DAC Output
with LDAC Pin
Fast Settling Time of 4.5 µs
Selectable Unity or 2x Gain Output
2.048V Internal Voltage Reference
50 ppm/°C VREF Temperature Coefficient
2.7V to 5.5V Single-Supply Operation
Extended Temperature Range: -40°C to +125°C
Applications
•
•
•
•
•
Set Point or Offset Trimming
Sensor Calibration
Precision Selectable Voltage Reference
Portable Instrumentation (Battery-Powered)
Calibration of Optical Communication Devices
Related Products(1)
P/N
DAC
Resolution
No. of
Channel
MCP4801
8
1
MCP4811
10
1
MCP4821
12
1
MCP4802
8
2
MCP4812
10
2
MCP4822
12
2
MCP4901
8
1
MCP4911
10
1
MCP4921
12
1
MCP4902
8
2
MCP4912
10
2
MCP4922
12
2
Voltage
Reference
(VREF)
Internal
(2.048V)
External
Note 1: The products listed here have similar
AC/DC performances.
 2010 Microchip Technology Inc.
DS22244B-page 1
MCP4801/4811/4821
Package Types
DFN (2x3)*
VDD 1
CS 2
SCK 3
SDI 4
MCP48X1
PDIP, SOIC, MSOP
8 VOUT
VDD
1
CS
2
7 VSS
6 SHDN
SCK 3
5 LDAC
SDI 4
8 VOUT
9
7 VSS
6 SHDN
5 LDAC
MCP4801: 8-bit single DAC
MCP4811: 10-bit single DAC
MCP4821: 12-bit single DAC
* Includes Exposed Thermal Pad (EP); see Table 3-1.
Block Diagram
LDAC
CS
SDI
SCK
Interface Logic
Power-on
Reset
Input
Register
DAC
Register
VDD
VSS
VREF
(2.048V)
String
DAC
Gain
Logic
Output
Op Amp
Output
Logic
SHDN
DS22244B-page 2
VOUT
 2010 Microchip Technology Inc.
MCP4801/4811/4821
1.0
ELECTRICAL
CHARACTERISTICS
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
Absolute Maximum Ratings †
VDD ............................................................................................................. 6.5V
All inputs and outputs .....................VSS – 0.3V to VDD + 0.3V
Current at Input Pins ....................................................±2 mA
Current at Supply Pins ...............................................±50 mA
Current at Output Pins ...............................................±25 mA
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-55°C to +125°C
ESD protection on all pins  4 kV (HBM), 400V (MM)
Maximum Junction Temperature (TJ) . .........................+150°C
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V,
Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85°C. Typical values are at +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Operating Voltage
VDD
2.7
—
5.5
Operating Current
IDD
—
330
400
µA
All digital inputs are grounded,
analog output (VOUT) is
unloaded. Code = 000h
Hardware Shutdown Current
ISHDN
—
0.3
2
µA
POR circuit is turned off
Software Shutdown Current
ISHDN_SW
—
VPOR
—
3.3
6
µA
POR circuit remains turned on
2.0
—
V
n
8
—
—
Bits
Power Requirements
Power-on Reset Threshold
DC Accuracy
MCP4801
Resolution
INL Error
INL
-1
±0.125
1
LSb
DNL
DNL
-0.5
±0.1
+0.5
LSb
n
10
—
—
Bits
Note 1
MCP4811
Resolution
INL Error
INL
-3.5
±0.5
3.5
LSb
DNL
DNL
-0.5
±0.1
+0.5
LSb
Note 1
MCP4821
Resolution
n
12
—
—
Bits
INL Error
INL
-12
±2
12
LSb
DNL
DNL
-0.75
±0.2
+0.75
LSb
Offset Error
Offset Error Temperature
Coefficient
Gain Error
Gain Error Temperature
Coefficient
Note 1:
2:
VOS
VOS/°C
-1
±0.02
1
—
0.16
—
—
-0.44
—
gE
-2
-0.10
2
G/°C
—
-3
—
Note 1
% of FSR Code = 0x000h
ppm/°C
-45°C to +25°C
ppm/°C
+25°C to +85°C
% of FSR Code = 0xFFFh,
not including offset error
ppm/°C
Guaranteed monotonic by design over all codes.
This parameter is ensured by design, and not 100% tested.
 2010 Microchip Technology Inc.
DS22244B-page 3
MCP4801/4811/4821
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V,
Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85°C. Typical values are at +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
2.008
2.048
2.088
V
—
125
325
ppm/°C
—
0.25
0.65
LSb/°C
-40°C to 0°C
—
45
160
ppm/°C
0°C to +85°C
0°C to +85°C
Internal Voltage Reference (VREF)
Internal Reference Voltage
Temperature Coefficient
(Note 2)
VREF
VREF/°C
VOUT when G = 1x and
Code = 0xFFFh
-40°C to 0°C
—
0.09
0.32
LSb/°C
ENREF
(0.1-10 Hz)
—
290
—
µVp-p
Code = 0xFFFh, G = 1x
eNREF
(1 kHz)
—
1.2
—
µV/Hz
Code = 0xFFFh, G = 1x
eNREF
(10 kHz)
—
1.0
—
µV/Hz
Code = 0xFFFh, G = 1x
fCORNER
—
400
—
Hz
Output Swing
VOUT
—
0.01 to
VDD – 0.04
—
V
Phase Margin
PM
—
66
—
Slew Rate
SR
—
0.55
—
V/µs
ISC
—
15
24
mA
tSETTLING
—
4.5
—
µs
Within ½ LSb of final value
from ¼ to ¾ full-scale range
Major Code Transition Glitch
—
45
—
nV-s
1 LSb change around major
carry (0111...1111 to
1000...0000)
Digital Feedthrough
—
<10
—
nV-s
Output Noise (VREF Noise)
Output Noise Density
1/f Corner Frequency
Output Amplifier
Short Circuit Current
Settling Time
Accuracy is better than 1 LSb
for VOUT = 10 mV to
(VDD – 40 mV)
Degree (°) CL = 400 pF, RL = 
Dynamic Performance (Note 2)
Note 1:
2:
Guaranteed monotonic by design over all codes.
This parameter is ensured by design, and not 100% tested.
DS22244B-page 4
 2010 Microchip Technology Inc.
MCP4801/4811/4821
ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x,
RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Parameters
Sym
Min
Typ
Max
VDD
Units
Conditions
2.7
—
5.5
IDD
—
350
—
µA
All digital inputs are grounded,
analog output (VOUT) is
unloaded. Code = 000h
ISHDN
—
1.5
—
µA
POR circuit is turned off
ISHDN_SW
—
VPOR
—
5
—
µA
POR circuit remains turned on
1.85
—
V
Power Requirements
Operating Voltage
Operating Current
Hardware Shutdown
Current
Software Shutdown Current
Power-on Reset threshold
DC Accuracy
MCP4801
Resolution
n
8
—
—
Bits
INL Error
INL
—
±0.25
—
LSb
DNL
DNL
—
±0.2
—
LSb
Note 1
MCP4811
Resolution
n
10
—
—
Bits
INL Error
INL
—
±1
—
LSb
DNL
DNL
—
±0.2
—
LSb
Note 1
MCP4821
Resolution
n
12
—
—
Bits
INL Error
INL
—
±4
—
LSb
DNL
DNL
—
±0.25
—
VOS
—
±0.02
—
VOS/°C
—
-5
—
gE
—
-0.10
—
G/°C
—
-3
—
ppm/°C
VREF
—
2.048
—
V
VREF/°C
—
125
—
ppm/°C
-40°C to 0°C
—
0.25
—
LSb/°C
-40°C to 0°C
—
45
—
ppm/°C
0°C to +85°C
Offset Error
Offset Error Temperature
Coefficient
Gain Error
Gain Error Temperature
Coefficient
LSb
Note 1
% of FSR Code = 0x000h
ppm/°C
+25°C to +125°C
% of FSR Code = 0xFFFh,
not including offset error
Internal Voltage Reference (VREF)
Internal Reference Voltage
Temperature Coefficient
(Note 2)
Output Noise (VREF Noise)
—
0.09
—
LSb/°C
ENREF
(0.1 – 10 Hz)
—
290
—
µVp-p
Code = 0xFFFh, G = 1x
eNREF
(1 kHz)
—
1.2
—
µV/Hz
Code = 0xFFFh, G = 1x
eNREF
(10 kHz)
—
1.0
—
µV/Hz
Code = 0xFFFh, G = 1x
fCORNER
—
400
—
Hz
Output Noise Density
1/f Corner Frequency
Note 1:
2:
VOUT when G = 1x and
Code = 0xFFFh
0°C to +85°C
Guaranteed monotonic by design over all codes.
This parameter is ensured by design, and not 100% tested.
 2010 Microchip Technology Inc.
DS22244B-page 5
MCP4801/4811/4821
ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x,
RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Parameters
Sym
Min
Typ
Max
Units
Output Swing
VOUT
—
0.01 to
VDD – 0.04
—
V
Phase Margin
PM
—
66
—
Conditions
Output Amplifier
Accuracy is better than 1 LSb
for VOUT = 10 mV to (VDD –
40 mV)
Degree (°) CL = 400 pF, RL = 
Slew Rate
SR
—
0.55
—
V/µs
Short Circuit Current
ISC
—
17
—
mA
tSETTLING
—
4.5
—
µs
Major Code Transition
Glitch
—
45
—
nV-s
Digital Feedthrough
—
<10
—
nV-s
Settling Time
Within ½ LSb of final value from
¼ to ¾ full-scale range
Dynamic Performance (Note 2)
Note 1:
2:
1 LSb change around major
carry (0111...1111 to
1000...0000)
Guaranteed monotonic by design over all codes.
This parameter is ensured by design, and not 100% tested.
AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)
Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125°C. Typical values are at +25°C.
Parameters
Sym
Min
Typ
Max
Units
Schmitt Trigger High-Level Input
Voltage (All digital input pins)
VIH
0.7 V
—
—
V
Schmitt Trigger Low-Level Input
Voltage (All digital input pins)
VIL
—
—
0.2 VDD
V
VHYS
—
0.05 VDD
—
Input Leakage Current
ILEAKAGE
-1
—
1
A
SHDN = LDAC = CS = SDI =
SCK = VDD or VSS
Digital Pin Capacitance
(All inputs/outputs)
CIN,
COUT
—
10
—
pF
VDD = 5.0V, TA = +25°C,
fCLK = 1 MHz (Note 1)
Clock Frequency
FCLK
—
—
20
MHz
Clock High Time
tHI
15
—
—
ns
Note 1
Clock Low Time
tLO
15
—
—
ns
Note 1
tCSSR
40
—
—
ns
Applies only when CS falls with
CLK high. (Note 1)
Data Input Setup Time
tSU
15
—
—
ns
Note 1
Data Input Hold Time
tHD
10
—
—
ns
Note 1
SCK Rise to CS Rise Hold Time
tCHS
15
—
—
ns
Note 1
CS High Time
tCSH
15
—
—
ns
Note 1
LDAC Pulse Width
tLD
100
—
—
ns
Note 1
LDAC Setup Time
tLS
40
—
—
ns
Note 1
tIDLE
40
—
—
ns
Note 1
Hysteresis of Schmitt Trigger Inputs
CS Fall to First Rising CLK Edge
SCK Idle Time before CS Fall
Note 1:
Conditions
DD
TA = +25°C (Note 1)
This parameter is ensured by design and not 100% tested.
DS22244B-page 6
 2010 Microchip Technology Inc.
MCP4801/4811/4821
tCSH
CS
tIDLE
tCSSR
Mode 1,1
tHI
tLO
tCHS
SCK Mode 0,0
tSU
tHD
SDI
MSb in
LSb in
LDAC
tLS
FIGURE 1-1:
tLD
SPI Input Timing Data.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Note 1
Thermal Package Resistances
Thermal Resistance, 8L-DFN (2x3)
JA
—
68
—
°C/W
Thermal Resistance, 8L-MSOP
JA
—
211
—
°C/W
Thermal Resistance, 8L-PDIP
JA
—
90
—
°C/W
Thermal Resistance, 8L-SOIC
JA
—
150
—
°C/W
Note 1:
The MCP4801/4811/4821 devices operate over this extended temperature range, but with reduced
performance. Operation in this range must not cause TJ to exceed the maximum junction temperature
of +150°C.
 2010 Microchip Technology Inc.
DS22244B-page 7
MCP4801/4811/4821
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
0.3
0.2
INL (LSB)
DNL (LSB)
0.1
0
-0.1
-0.2
-0.3
0
1024
2048
3072
5
4
3
2
1
0
-1
-2
-3
-4
-5
Ambient Temperature
125C
4096
0
1024
DNL vs. Code (MCP4821).
2.5
Absolute INL (LSB)
0.1
DNL (LSB)
4096
FIGURE 2-4:
INL vs. Code and
Temperature (MCP4821).
0.2
0
-0.1
2
1.5
1
0.5
0
-0.2
0
1024
2048
3072
Code (Decimal)
-40
4096
125C
85C
-20
0
20
40
60
80
100
120
Ambient Temperature (ºC)
25C
FIGURE 2-2:
DNL vs. Code and
Temperature (MCP4821).
FIGURE 2-5:
Absolute INL vs.
Temperature (MCP4821).
2
0.0766
0.0764
0
0.0762
INL (LSB)
Absolute DNL (LSB)
3072
25
Code (Decimal)
Code (Decimal)
FIGURE 2-1:
2048
85
0.076
0.0758
0.0756
-2
-4
0.0754
0.0752
-6
0.075
-40
-20
0
20
40
60
80
0
100 120
1024
DS22244B-page 8
3072
4096
Code (Decimal)
Ambient Temperature (ºC)
FIGURE 2-3:
Absolute DNL vs.
Temperature (MCP4821).
2048
FIGURE 2-6:
Note:
INL vs. Code (MCP4821).
Single device graph for illustration of 64
code effect.
 2010 Microchip Technology Inc.
MCP4801/4811/4821
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
0.3
0.6
o
- 40 C
0.4
0.1
INL (LSB)
DNL (LSB)
- 40oC
0.5
0.2
0
-0.1
o
85 C
0.3
0.2
0.1
0
125oC
-0.1
-0.2
-0.3
-0.3
0
128
256
384
512
640
768
25oC
-0.2
+25oC to +125oC
0
896 1024
32
64
96
FIGURE 2-7:
DNL vs. Code and
Temperature (MCP4811).
INL (LSB)
Full Scale VOUT (V)
1
85oC
0
-0.5
-1
-1.5
25oC
-2
o
- 40 C
-2.5
o
125 C
-3
0
128
256
384
512
640
768
2.050
2.049
2.048
2.047
2.046
2.045
2.044
2.043
2.042
2.041
2.040
192
224
256
VDD: 4V
VDD: 3V
VDD: 2.7V
-40
896 1024
-20
0
20
40
60
80
100 120
Ambient Temperature (°C)
Code
FIGURE 2-8:
INL vs. Code and
Temperature (MCP4811).
0.15
160
FIGURE 2-10:
INL vs. Code and
Temperature (MCP4801).
1.5
0.5
128
Code
Code
o
FIGURE 2-11:
Full-Scale VOUT vs. Ambient
Temperature and VDD. Gain = 1x.
4.100
o
DNL (LSB)
0.1
0.05
0
34
-0.05
-0.1
Full Scale VOUT (V)
Temperature: - 40 C to +125 C
4.096
4.092
VDD: 5.5V
4.088
VDD: 5V
4.084
4.080
-0.15
4.076
0
32
64
96 128 160 192 224 256
Code
FIGURE 2-9:
DNL vs. Code and
Temperature (MCP4801).
 2010 Microchip Technology Inc.
-40
-20
0
20
40
60
80
100 120
Ambient Temperature (°C)
FIGURE 2-12:
Full-Scale VOUT vs. Ambient
Temperature and VDD. Gain = 2x.
DS22244B-page 9
MCP4801/4811/4821
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
10
1E+1
100
1E+2
1k
1E+3
10k
1E+4
FIGURE 2-16:
320
315
310
305
300
IDD Histogram (VDD = 2.7V).
18
1.E-02
10.0
Output Noise Voltage (mV)
16
Occurrence
14
Eni (in VP-P)
0.10
1.E-04
12
10
8
6
4
Eni (in VRMS)
2
FIGURE 2-14:
Output Noise Voltage
(VREF Noise Voltage) vs. Bandwidth. Gain = 2x.
340
FIGURE 2-17:
350
345
340
335
>350
IDD (µA)
330
325
320
315
310
1M
1E+6
305
10k
100k
1E+4
1E+5
Bandwidth (Hz)
300
1k
1E+3
0
295
0.01
1.E-05
100
1E+2
290
Maximum Measurement Time = 10s
285
1.E-03
1.00
IDD Histogram (VDD = 5.0V).
5.5V
5.0V
4.0V
3.0V
2.7V
VDD
320
300
IDD (µA)
295
IDD (µA)
Frequency (Hz)
FIGURE 2-13:
Output Noise Voltage
Density (VREF Noise Density) vs. Frequency.
Gain = 1x.
290
285
100k
1E+5
>320
1
1E+0
280
0.1
1.E-07
0.1
1E-1
265
1
1.E-06
275
1.E-05
10
20
18
16
14
12
10
8
6
4
2
0
270
Occurrence
Output Noise Voltage Density
(µV/Hz)
100
1.E-04
280
260
240
220
200
180
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (°C)
FIGURE 2-15:
DS22244B-page 10
IDD vs. Temperature and VDD.
 2010 Microchip Technology Inc.
MCP4801/4811/4821
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
0.7
0.4
0.3
0.2
-0.1
VDD
-0.15
Gain Error (%)
4.0V
3.0V
2.7V
VDD
0.5
ISHDN (µA)
-0.05
5.5V
5.0V
0.6
5.5V
5.0V
4.0V
3.0V
2.7V
-0.2
-0.25
-0.3
-0.35
-0.4
0.1
-0.45
-0.5
0
-40
-20
0
20
40
60
80
100
-40
120
-20
Ambient Temperature (ºC)
FIGURE 2-18:
Hardware Shutdown Current
vs. Temperature and VDD.
4
20
40
60
80
100
120
5.0V
3
4.0V
2.5
3.0V
2.7V
2
V DD
1.5
Gain Error vs. Temperature
VDD
4
5.5V
3.5
VIN Hi Threshold (V)
ISHDN_SW (µA)
FIGURE 2-21:
and VDD.
5.5V
3.5
1
5.0V
3
4.0V
2.5
2
3.0V
2.7V
1.5
1
-40
-20
0
20
40
60
80
100
120
-40
-20
Ambient Temperature (ºC)
0
20
40
60
80
100
120
Ambient Temperature (ºC)
FIGURE 2-19:
Software Shutdown Current
vs. Temperature and VDD.
FIGURE 2-22:
VIN High Threshold vs.
Temperature and VDD.
1.6
0.09
0.07
0.05
5.5V
0.03
VDD
0.01
5.0V
4.0V
3.0V
2.7V
-0.01
-0.03
-40 -20
0
20
40
60
80
100 120
Ambient Temperature (ºC)
FIGURE 2-20:
and VDD.
Offset Error vs. Temperature
 2010 Microchip Technology Inc.
VIN Low Threshold (V)
0.11
Offset Error (%)
0
Ambient Temperature (ºC)
VDD
1.5
5.5V
1.4
5.0V
1.3
1.2
4.0V
1.1
1
3.0V
2.7V
0.9
0.8
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (ºC)
FIGURE 2-23:
VIN Low Threshold vs.
Temperature and VDD.
DS22244B-page 11
MCP4801/4811/4821
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
16
2.5
5.5V
2
5.0V
1.75
1.5
4.0V
1.25
1
3.0V
2.7V
0.75
0.5
15
IOUT_HI_SHORTED (mA)
VIN_SPI Hysteresis (V)
5.5V
5.0V
4.0V
3.0V
2.7V
VDD
2.25
14
VDD
13
12
11
0.25
10
0
-40
-20
0
20
40
60
80
-40
100 120
-20
Ambient Temperature (ºC)
FIGURE 2-24:
Input Hysteresis vs.
Temperature and VDD.
40
60
80
100
120
6.0
4.0V
0.033
0.031
5.0
0.029
4.0
VREF = 4.096V
0.027
0.025
3.0V
0.023
2.7V
0.021
VDD
0.019
VOUT (V)
VOUT_HI Limit (VDD-Y)(V)
20
FIGURE 2-27:
IOUT High Short vs.
Temperature and VDD.
0.035
Output Shorted to VDD
3.0
2.0
1.0
Output Shorted to VSS
0.017
0.0
0.015
-40
-20
0
20
40
60
80
0
100 120
2
Ambient Temperature (ºC)
FIGURE 2-25:
VOUT High Limit
vs.Temperature and VDD.
0.0028
VOUT_LOW Limit (Y-AVSS)(V)
0
Ambient Temperature (ºC)
FIGURE 2-28:
4
6
8
10
IOUT (mA)
12
14
16
IOUT vs. VOUT. Gain = 2x.
VDD
0.0026
0.0024
5.5V
0.0022
5.0V
0.0020
4.0V
3.0V
2.7V
0.0018
0.0016
0.0014
0.0012
0.0010
-40
-20
0
20
40
60
80
100 120
Ambient Temperature (ºC)
FIGURE 2-26:
VOUT Low Limit vs.
Temperature and VDD.
DS22244B-page 12
 2010 Microchip Technology Inc.
MCP4801/4811/4821
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
VOUT
VOUT
SCK
LDAC
LDAC
Time (1 µs/div)
FIGURE 2-29:
VOUT Rise Time.
Time (1 µs/div)
FIGURE 2-32:
VOUT Rise Time.
VOUT
VOUT
SCK
SCK
LDAC
LDAC
Time (1 µs/div)
VOUT Fall Time.
FIGURE 2-33:
Shutdown.
VOUT Rise Time Exit
Ripple Rejection (dB)
FIGURE 2-30:
Time (1 µs/div)
VOUT
SCK
LDAC
Time (1 µs/div)
FIGURE 2-31:
VOUT Rise Time.
 2010 Microchip Technology Inc.
Frequency (Hz)
FIGURE 2-34:
PSRR vs. Frequency.
DS22244B-page 13
MCP4801/4811/4821
NOTES:
DS22244B-page 14
 2010 Microchip Technology Inc.
MCP4801/4811/4821
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE FOR MCP4801/4811/4821
MCP4801/4811/4821
Symbol
MSOP, PDIP,
SOIC, DFN
DFN
1
1
3.1
Description
VDD
Supply Voltage Input (2.7V to 5.5V)
2
2
CS
Chip Select Input
3
3
SCK
Serial Clock Input
4
4
SDI
5
5
LDAC
DAC Output Synchronization Input. This pin is used to transfer the input
register (DAC settings) to the output register (VOUT)
6
6
SHDN
Hardware Shutdown Input
7
7
VSS
8
8
VOUT
—
9
EP
Serial Data Input
Ground reference point for all circuitry on the device
DAC Analog Output
Exposed thermal pad. This pad must be connected to VSS in application
Supply Voltage Pins (VDD, VSS)
VDD is the positive supply voltage input pin. The input
supply voltage is relative to VSS and can range from
2.7V to 5.5V. The power supply at the VDD pin should
be as clean as possible for good DAC performance.
Using an appropriate bypass capacitor of about 0.1 µF
(ceramic) to ground is recommended. An additional
10 µF capacitor (tantalum) in parallel is also recommended to further attenuate high-frequency noise
present in application boards.
VSS is the analog ground pin and the current return
path of the device. The user must connect the VSS pin
to a ground plane through a low-impedance
connection. If an analog ground path is available in the
application Printed Circuit Board (PCB), it is highly
recommended that the VSS pin be tied to the analog
ground path or isolated within an analog ground plane
of the circuit board.
3.2
Chip Select (CS)
CS is the Chip Select input pin, which requires an
active low to enable serial clock and data functions.
3.3
Serial Clock Input (SCK)
3.4
Serial Data Input (SDI)
SDI is the SPI compatible serial data input pin.
3.5
Latch DAC Input (LDAC)
LDAC (latch DAC synchronization input) pin is used to
transfer the input latch register to the DAC register (output latches, VOUT). When this pin is low, VOUT is
updated with input register content. This pin can be tied
to low (VSS) if the VOUT update is desired at the rising
edge of the CS pin. This pin can be driven by an external control device such as an MCU I/O pin.
3.6
Analog Output (VOUT)
VOUT is the DAC analog output pin. The DAC output
has an output amplifier. The full-scale range of the DAC
output is from VSS to G*VREF, where G is the gain
selection option (1x or 2x). The DAC analog output
cannot go higher than the supply voltage (VDD).
3.7
Exposed Thermal Pad (EP)
There is an internal electrical connection between the
exposed thermal pad (EP) and the VSS pin. They must
be connected to the same potential on the PCB.
SCK is the SPI compatible serial clock input pin.
 2010 Microchip Technology Inc.
DS22244B-page 15
MCP4801/4811/4821
NOTES:
DS22244B-page 16
 2010 Microchip Technology Inc.
MCP4801/4811/4821
4.0
GENERAL OVERVIEW
The MCP4801, MCP4811 and MCP4821 are single
channel voltage-output 8-bit, 10-bit and 12-bit DAC
devices, respectively. These devices include rail-to-rail
output amplifier, internal voltage reference, shutdown
and reset-management circuitry. The devices use an
SPI serial communication interface and operate with a
single supply voltage from 2.7V to 5.5V.
The DAC input coding of these devices is straight
binary. Equation 4-1 shows the DAC analog output
voltage calculation.
EQUATION 4-1:
V OUT
ANALOG OUTPUT
VOLTAGE (VOUT)
 2.048V  Dn 
= ----------------------------------G
n
2
Where:
2.048V
=
Internal voltage reference
Dn
=
DAC input code
G
n
=
Gain selection
=
2 for <GA> bit = 0
=
1 for <GA> bit = 1
=
DAC Resolution
=
8 for MCP4801
=
10 for MCP4811
=
12 for MCP4821
1 LSb is the ideal voltage difference between two
successive codes. Table 4-1 illustrates the LSb
calculation of each device.
TABLE 4-1:
MCP4801
(n = 8)
MCP4811
(n = 10)
MCP4821
(n = 12)
(a) 0.0V to 255/256 * 2.048V when gain setting = 1x.
1x
2x
1x
2x
1x
2x
LSb Size
2.048V/256 = 8 mV
4.096V/256 = 16 mV
2.048V/1024 = 2 mV
4.096V/1024 = 4 mV
2.048V/4096 = 0.5 mV
4.096V/4096 = 1 mV
INL ACCURACY
Integral Non-Linearity (INL) error is the maximum
deviation between an actual code transition point and
its corresponding ideal transition point once offset and
gain errors have been removed. The two endpoints
method (from 0x000 to 0xFFF) is used for the
calculation. Figure 4-1 shows the details.
A positive INL error represents transition(s) later than
ideal. A negative INL error represents transition(s) earlier than ideal.
INL < 0
111
110
Actual
Transfer
Function
101
The ideal output range of each device is:
• MCP4801 (n = 8)
Gain
Selection
Device
4.0.1
LSb OF EACH DEVICE
Digital
Input
Code
100
011
Ideal Transfer
Function
(b) 0.0V to 255/256 * 4.096V when gain setting = 2x.
• MCP4811 (n = 10)
010
(a) 0.0V to 1023/1024 * 2.048V when gain setting = 1x.
001
(b) 0.0V to 1023/1024 * 4.096V when gain setting = 2x.
• MCP4821 (n = 12)
000
INL < 0
(a) 0.0V to 4095/4096 * 2.048V when gain setting = 1x.
DAC Output
(b) 0.0V to 4095/4096 * 4.096V when gain setting = 2x.
Note:
See the output swing voltage specification in
Section 1.0 “Electrical Characteristics”.
 2010 Microchip Technology Inc.
FIGURE 4-1:
Example for INL Error.
DS22244B-page 17
MCP4801/4811/4821
4.0.2
DNL ACCURACY
4.1
A Differential Non-Linearity (DNL) error is the measure
of the variations in code widths from the ideal code
width. A DNL error of zero indicates that every code is
exactly 1 LSb wide.
111
110
Actual
Transfer
Function
101
Digital
Input
Code
100
Ideal Transfer
Function
011
001
Wide Code, >1 LSb
000
Narrow Code, <1 LSb
DAC Output
4.0.3
Example for DNL Error.
OFFSET ERROR
Offset error is the deviation from zero voltage output
when the digital input code is zero.
4.0.4
OUTPUT AMPLIFIER
The analog DAC output is buffered with a low-power,
precision CMOS amplifier. This amplifier provides low
offset voltage and low noise. The output stage enables
the device to operate with output voltages close to the
power supply rails. Refer to Section 1.0 “Electrical
Characteristics” for the analog output voltage range
and load conditions.
In addition to resistive load-driving capability, the
amplifier will also drive high capacitive loads without
oscillation. The amplifier’s strong output allows VOUT to
be used as a programmable voltage reference in a
system.
4.1.1.1
010
FIGURE 4-2:
4.1.1
Circuit Descriptions
Programmable Gain Block
The rail-to-rail output amplifier has two configurable
gain options: a gain of 1x (<GA> = 1) or a gain of 2x
(<GA> = 0). The default setting is a gain of 2x. This
results in an ideal full-scale output of 0.000V to 4.096V
due to the internal reference (VREF = 2.048V).
4.1.2
VOLTAGE REFERENCE
The MCP4801/4811/4821 devices utilize internal
2.048V voltage reference. The voltage reference has a
low temperature coefficient and low noise
characteristics. Refer to Section 1.0 “Electrical Characteristics” for the voltage reference specifications.
GAIN ERROR
Gain error is the deviation from the ideal output,
VREF – 1 LSb, excluding the effects of offset error.
DS22244B-page 18
 2010 Microchip Technology Inc.
MCP4801/4811/4821
4.1.3
POWER-ON RESET CIRCUIT
The internal Power-on Reset (POR) circuit monitors the
power supply voltage (VDD) during the device
operation. The circuit also ensures that the DAC
powers up with high output impedance (<SHDN> = 0,
typically 500 k. The devices will continue to have a
high-impedance output until a valid write command is
received, and the LDAC pin meets the input low
threshold.
If the power supply voltage is less than the POR
threshold (VPOR = 2.0V, typical), the DAC will be held
in the Reset state. It will remain in that state until
VDD > VPOR and a subsequent write command is
received.
Supply Voltages
Figure 4-3 shows a typical power supply transient
pulse and the duration required to cause a reset to
occur, as well as the relationship between the duration
and trip voltage. A 0.1 µF decoupling capacitor,
mounted as close as possible to the VDD pin, can
provide additional transient immunity.
5V
VPOR
SHUTDOWN MODE
The user can shut down the device using a software
command (<SHDN> = 0) or SHDN pin. During
shutdown mode, most of the internal circuits, including
the output amplifier, are turned off for power savings.
The internal reference is not affected by the shutdown
command. The serial interface also remains active,
allowing a write command to bring the device out of
Shutdown mode. There will be no analog output at the
VOUT pin, which is internally switched to a known resistive load (500 ktypical. Figure 4-4 shows the analog
output stage during Shutdown mode.
The condition of the Power-on Reset circuit during
Shutdown is as follows:
a)
b)
Turned off if shutdown occurred from the SHDN
pin
Remains turned on if the shutdown occurred
through software
The device will remain in Shutdown mode until the
<SHDN> bit = 1 is latched into the device or SHDN pin
is changed to logic high. When the device is changed
from Shutdown to Active mode, the output settling time
takes < 10 µs, but greater than the standard active
mode settling time (4.5 µs).
VDD - VPOR
Transient Duration
10
VOUT
OP
Amp
Power-Down
Control Circuit
Time
Transient Duration (µs)
4.1.4
TA = +25°C
Resistive
Load
8
500 k
Resistive String DAC
6
4
FIGURE 4-4:
Mode.
Transients above the curve
will cause a reset
2
0
FIGURE 4-3:
Output Stage for Shutdown
Transients below the curve
will NOT cause a reset
1
2
3
4
VDD - VPOR (V)
5
Typical Transient Response.
 2010 Microchip Technology Inc.
DS22244B-page 19
MCP4801/4811/4821
NOTES:
DS22244B-page 20
 2010 Microchip Technology Inc.
MCP4801/4811/4821
5.0
SERIAL INTERFACE
5.1
Overview
The MCP4801/4811/4821 devices are designed to
interface directly with the Serial Peripheral Interface
(SPI) port, available on many microcontrollers, and
supports Mode 0,0 and Mode 1,1. Commands and data
are sent to the device via the SDI pin, with data being
clocked-in on the rising edge of SCK. The
communications are unidirectional and, thus, data
cannot be read out of the MCP4801/4811/4821
devices. The CS pin must be held low for the duration
of a write command. The write command consists of
16 bits and is used to configure the DAC’s control and
data latches. Register 5-1 to Register 5-3 detail the
input register that is used to configure and load the
DAC register for each device. Figure 5-1 to Figure 5-3
show the write command for each device.
Refer to Figure 1-1 and the SPI Timing Specifications
Table for detailed input and output timing specifications
for both Mode 0,0 and Mode 1,1 operation.
 2010 Microchip Technology Inc.
5.2
Write Command
The write command is initiated by driving the CS pin
low, followed by clocking the four Configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The CS pin is then raised, causing the data to be
latched into the DAC’s input register.
The MCP4801/4811/4821 devices utilize a doublebuffered latch structure to allow the DAC output to be
synchronized with the LDAC pin, if desired.
By bringing down the LDAC pin to a low state, the
content stored in the DAC’s input register is transferred
into the DAC’s output register (VOUT), and VOUT is
updated.
All writes to the MCP4801/4811/4821 devices are
16-bit words. Any clocks after the first 16th clock will be
ignored. The Most Significant four bits are
Configuration bits. The remaining 12 bits are data bits.
No data can be transferred into the device with CS
high. The data transfer will only occur if 16 clocks have
been transferred into the device. If the rising edge of
CS occurs prior, shifting of data into the input register
will be aborted.
DS22244B-page 21
MCP4801/4811/4821
REGISTER 5-1:
WRITE COMMAND REGISTER FOR MCP4821 (12-BIT DAC)
W-x
W-x
W-x
W-0
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
0
—
GA
SHDN
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
bit 15
bit 0
REGISTER 5-2:
WRITE COMMAND REGISTER FOR MCP4811 (10-BIT DAC)
W-x
W-x
W-x
W-0
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
0
—
GA
SHDN
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
bit 15
W-x
x
bit 0
REGISTER 5-3:
WRITE COMMAND REGISTER FOR MCP4801 (8-BIT DAC)
W-x
W-x
W-x
W-0
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
0
—
GA
SHDN
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
bit 15
bit 0
Where:
bit 15 ( 1) 0 = Write to DAC register
1 = Ignore this command
bit 14
—
Don’t Care
bit 13
GA: Output Gain Selection bit
1 = 1x (VOUT = VREF * D/4096)
0 = 2x (VOUT = 2 * VREF * D/4096), where internal VREF = 2.048V.
bit 12
SHDN: Output Shutdown Control bit
1 = Active mode operation. VOUT is available. 
0 = Shutdown the device. Analog output is not available. VOUT pin is connected to 500 ktypical)
bit 11-0
D11:D0: DAC Input Data bits. Bit x is ignored.
Legend
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
1 = bit is set
0 = bit is cleared
Note 1:
x = bit is unknown
This bit must be ‘0’. The device ignores the write command if this MSB bit is not ‘0’.
DS22244B-page 22
 2010 Microchip Technology Inc.
MCP4801/4811/4821
CS
0
1
2
3
4
5
6
7
8
9
10 11
12
(Mode 1,1)
13 14 15
SCK
(Mode 0,0)
config bits
0
SDI
12 data bits
— GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LDAC
VOUT
FIGURE 5-1:
Write Command for MCP4821 (12-bit DAC).
CS
0
1
2
3
4
5
6
7
8
9
10 11
12
(Mode 1,1)
13 14 15
SCK
(Mode 0,0)
config bits
0
SDI
12 data bits
— GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
LDAC
VOUT
Note:
X = “don’t care” bits.
FIGURE 5-2:
Write Command for MCP4811 (10-bit DAC).
CS
0
1
2
3
4
5
6
7
8
9
10 11
12
(Mode 1,1)
13 14 15
SCK
(Mode 0,0)
config bits
0
SDI
12 data bits
— GA SHDN D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
LDAC
VOUT
Note:
FIGURE 5-3:
X = “don’t care” bits.
Write Command for MCP4801 (8-bit DAC).
 2010 Microchip Technology Inc.
DS22244B-page 23
MCP4801/4811/4821
NOTES:
DS22244B-page 24
 2010 Microchip Technology Inc.
MCP4801/4811/4821
6.0
TYPICAL APPLICATIONS
6.3
Output Noise Considerations
The MCP4801/4811/4821 family of devices are general
purpose, single channel voltage output DACs for
various applications where a precision operation with
low-power and internal voltage reference is required.
The voltage noise density (in µV/Hz) is illustrated in
Figure 2-13. This noise appears at VOUT, and is
primarily a result of the internal reference voltage.
Its 1/f corner (fCORNER) is approximately 400 Hz.
Applications generally suited for the devices are:
Figure 2-14 illustrates the voltage noise (in mVRMS or
mVP-P). A small bypass capacitor on VOUT is an
effective method to produce a single-pole Low-Pass
Filter (LPF) that will reduce this noise. For instance, a
bypass capacitor sized to produce a 1 kHz LPF would
result in an ENREF of about 100 µVRMS. This would be
necessary when trying to achieve the low DNL error
performance (at G = 1x) that the MCP4801/4811/4821
devices are capable of. The tested range for stability
is .001 µF through 4.7 µF.
Digital Interface
The MCP4801/4811/4821 devices utilize a 3-wire
synchronous serial protocol to transfer the DAC’s setup
and input codes from the digital devices. The serial
protocol can be interfaced to SPI or Microwire
peripherals which are common on many microcontroller units (MCUs), including Microchip’s PIC® MCUs
and dsPIC® DSCs.
In addition to the three serial connections (CS, SCK
and SDI), the LDAC signal synchronizes the DAC
output with LDAC pin event. By bringing the LDAC pin
down “low”, the DAC input codes and settings in the
DAC input register are latched into the output register,
and the DAC analog output is updated. Figure 6-1
shows an example of the pin connections. Note that the
LDAC pin can be tied low (VSS) to reduce the required
connections from 4 to 3 I/O pins. In this case, the DAC
output can be immediately updated when a valid
16 clock transmission has been received and the CS
pin has been raised.
6.2
VDD
C1 = 10 µF
C2 = 0.1 µF
VDD
C1
VOUT
1 µF
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS of the device should reside on the analog plane.
C2
C1
C2
C1
VOUT
CS
1 µF
C2
SDI
AVSS
SDI
SDO
SCK
LDAC
CS0
Power Supply Considerations
The typical application will require a bypass capacitor
to filter out noise in the power supply traces. The noise
can be induced onto the power supply’s traces from
various events such as digital switching or as a result
of changes on the DAC’s output. The bypass capacitor
helps minimize the effect of these noise sources.
Figure 6-1 illustrates an appropriate bypass strategy. In
this example, two bypass capacitors are used in parallel: (a) 0.1 µF (ceramic) and (b)10 µF (tantalum). These
capacitors should be placed as close to the device
power pin (VDD) as possible (within 4 mm).
VDD
PIC® Microcontroller
6.1
MCP48x1
Set Point or Offset Trimming
Sensor Calibration
Precision Selectable Voltage Reference
Portable Instrumentation (Battery-Powered)
Calibration of Optical Communication Devices
MCP48x1
•
•
•
•
•
AVSS
FIGURE 6-1:
Diagram.
6.4
VSS
Typical Connection
Layout Considerations
Inductively-coupled AC transients and digital switching
noises can degrade the output signal integrity, and
potentially reduce the device performance. Careful
board layout will minimize these effects and increase
the Signal-to-Noise Ratio (SNR). Bench testing has
shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs and
isolated outputs with proper decoupling, is critical for
the best performance. Particularly harsh environments
may require shielding of critical signals.
Breadboards and wire-wrapped boards are not
recommended if low noise is desired.
 2010 Microchip Technology Inc.
DS22244B-page 25
MCP4801/4811/4821
6.5
6.5.1.1
Single-Supply Operation
Decreasing Output Step Size
The MCP4801/4811/4821 devices are rail-to-rail
voltage output DAC devices designed to operate with a
VDD range of 2.7V to 5.5V. Its output amplifier is robust
enough to drive small-signal loads directly. Therefore, it
does not require any external output buffer for most
applications.
If the application is calibrating the bias voltage of a
diode or transistor, a bias voltage range of 0.8V may be
desired with about 200 µV resolution per step. Two
common methods to achieve a 0.8V range are to either
reduce VREF to 0.82V (using the MCP49XX family
device that uses external reference) or use a voltage
divider on the DAC’s output.
6.5.1
Using a VREF is an option if the VREF is available with
the desired output voltage range. However,
occasionally, when using a low-voltage VREF, the noise
floor causes SNR error that is intolerable. Using a
voltage divider method is another option and provides
some advantages when VREF needs to be very low or
when the desired output voltage is not available. In this
case, a larger value VREF is used while two resistors
scale the output range down to the precise desired
level.
DC SET POINT OR CALIBRATION
A common application for the devices is a digitallycontrolled set point and/or calibration of variable
parameters, such as sensor offset or slope. For
example, the MCP4821 and MCP4822 provide
4096 output steps. If G = 1x is selected, the internal
2.048V VREF would produce 500 µV of resolution. If
G = 2x is selected, the internal 2.048 VREF would
produce 1 mV of resolution.
Example 6-1 illustrates this concept. Note that the
bypass capacitor on the output of the voltage divider
plays a critical function in attenuating the output noise
of the DAC and the induced noise from the
environment.
EXAMPLE 6-1:
EXAMPLE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION
VDD
(a) Single Output DAC:
MCP4801
MCP4811
MCP4821
(b) Dual Output DAC:
MCP4802
VCC+
RSENSE
VDD
MCP4812
MCP4822
DAC
Comparator
R1
VOUT
VTRIP
R2
0.1 µF
VCC–
SPI
3-wire
Dn
VOUT = 2.048  G  -----N
2
 R2 
V trip = VOUT  --------------------
 R1 + R2
DS22244B-page 26
G
=
Gain selection (1x or 2x)
Dn
=
Digital value of DAC (0-255) for MCP4801/MCP4802
=
Digital value of DAC (0-1023) for MCP4811/MCP4812
N
=
Digital value of DAC (0-4095) for MCP4821/MCP4822
=
DAC bit resolution
 2010 Microchip Technology Inc.
MCP4801/4811/4821
6.5.1.2
Building a “Window” DAC
If the threshold is not near VREF, 2VREF or VSS, then
creating a “window” around the threshold has several
advantages. One simple method to create this
“window” is to use a voltage divider network with a pullup and pull-down resistor. Example 6-2 and
Example 6-4 illustrate this concept.
When calibrating a set point or threshold of a sensor,
typically only a small portion of the DAC output range is
utilized. If the LSb size is adequate enough to meet the
application’s accuracy needs, the unused range is
sacrificed without consequences. If greater accuracy is
needed, then the output range will need to be reduced
to increase the resolution around the desired threshold.
EXAMPLE 6-2:
SINGLE-SUPPLY “WINDOW” DAC
(a) Single Output DAC:
MCP4801
MCP4811
MCP4821
(b) Dual Output DAC:
MCP4802
MCP4812
VCC+
MCP4822
VDD
DAC
VCC+
RSENSE
R3
VOUT
Comparator
R1
VTRIP
0.1 µF
R2
VCC-
SPI
3-wire
VCC-
Dn
V OUT = 2.048  G  -----N
2
G
=
Gain selection (1x or 2x)
Dn
=
Digital value of DAC (0-255) for MCP4801/MCP4802
=
Digital value of DAC (0-1023) for MCP4811/MCP4812
N
=
Digital value of DAC (0-4095) for MCP4821/MCP4822
=
DAC bit resolution
Thevenin
Equivalent
R2R3
R 23 = ------------------R2 + R3
V 23
R1
VOUT
VO
 VCC+ R2  +  VCC- R 3 
= -----------------------------------------------------R2 + R3
VOUT R 23 + V 23 R 1
V trip = --------------------------------------------R1 + R 23
 2010 Microchip Technology Inc.
R23
V23
DS22244B-page 27
MCP4801/4811/4821
6.6
Bipolar Operation
Example 6-3 illustrates a simple bipolar voltage source
configuration. R1 and R2 allow the gain to be selected,
while R3 and R4 shift the DAC’s output to a selected
offset. Note that R4 can be tied to VDD, instead of VSS,
if a higher offset is desired. Also note that a pull-up to
VDD could be used instead of R4, or in addition to R4, if
a higher offset is desired.
Bipolar operation is achievable using the
MCP4801/4811/4821 family of devices by utilizing an
external operational amplifier (op amp). This
configuration is desirable due to the wide variety and
availability of op amps. This allows a general purpose
DAC, with its cost and availability advantages, to meet
almost any desired output voltage range, power and
noise performance.
EXAMPLE 6-3:
DIGITALLY-CONTROLLED BIPOLAR VOLTAGE SOURCE
R2
(a) Single Output DAC:
VDD
MCP4801
VDD
MCP4811
R1
MCP4821
VOUT
(b) Dual Output DAC:
MCP4812
MCP4822
VO
R3
DAC
MCP4802
VCC+
VIN+
R4
VCC–
0.1 µF
SPI
3-wire
Dn
V OUT = 2.048  G  -----N
2
V OUT R 4
V IN+ = -------------------R3 + R4
R2
R2
VO = VIN+  1 + ------ – VDD  ------
R1
R1
6.6.1
G
=
Gain selection (1x or 2x)
Dn
=
Digital value of DAC (0-255) for MCP4801/MCP4802
=
Digital value of DAC (0-1023) for MCP4811/MCP4812
=
Digital value of DAC (0-4095) for MCP4821/MCP4822
=
DAC bit resolution
N
DESIGN EXAMPLE: DESIGN A
BIPOLAR DAC USING EXAMPLE 6-3
WITH 12-BIT MCP4821 OR
MCP4822
An output step magnitude of 1 mV, with an output range
of ±2.05V, is desired for a particular application.
The equation can be simplified to:
– R2
– 2.05
--------- = ----------------R1
4.096V
R2
1
------ = --R1
2
If R1 = 20 k and R2 = 10 k, the gain will be 0.5.
Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V.
Step 2: Calculate the resolution needed:
Step 4: Next solve for R3 and R4 by setting the DAC to
4096, knowing that the output needs to be +2.05V.
4.1V/1 mV = 4100
Since 212 = 4096, 12-bit resolution is desired.
Step 3: The amplifier gain (R2/R1), multiplied by fullscale VOUT (4.096V), must be equal to the desired
minimum output to achieve bipolar operation.
Since any gain can be realized by choosing
resistor values (R1+R2), the VREF value must be
selected first. If a VREF of 4.096V is used (G=2),
solve for the amplifier’s gain by setting the DAC to
0, knowing that the output needs to be -2.05V.
DS22244B-page 28
R4
2
2.05V +  0.5  4.096V 
------------------------ = ------------------------------------------------------- = -- R3 + R4 
1.5  4.096V
3
If R4 = 20 k, then R3 = 10 k
 2010 Microchip Technology Inc.
MCP4801/4811/4821
6.7
Selectable Gain and Offset Bipolar
Voltage Output
This circuit is typically used for linearizing a sensor
whose slope and offset varies.
The equation to design a bipolar “window” DAC would
be utilized if R3, R4 and R5 are populated.
In some applications, precision digital control of the
output range is desirable. Example 6-4 illustrates how
to use the MCP4801/4811/4821 family of devices to
achieve this in a bipolar or single-supply application.
EXAMPLE 6-4:
BIPOLAR VOLTAGE SOURCE WITH SELECTABLE GAIN AND OFFSET
R2
VDD
VCC+
VOUTA
R1
DACA
(DACA for Gain Adjust)
VDD
VOUTB
VCC+
VO
R5
R3
VIN+
DACB
(DACB for Offset Adjust)
SPI
R4
3
VCC–
VCC–
Dn
VOUTA = 2.048  G A  -----N
2
Dn
V OUTB = 2.048  G B  -----N
2
V IN+
0.1 µF
V OUTB R4 + V CC- R3
= ------------------------------------------------R3 + R4
G
=
Gain selection (1x or 2x)
N
=
DAC bit resolution
Dn
=
Digital value of DAC (0-255) for MCP4801
=
Digital value of DAC (0-1023) for MCP4811
=
Digital value of DAC (0-4095) for MCP4821
R2
R2
VO = V IN+  1 + ------ – VOUTA  ------

 R 1
R 1
Offset Adjust Gain Adjust
Bipolar “Window” DAC using R4 and R5
Thevenin
Equivalent
V CC+ R 4 + VCC- R 5
V 45 = --------------------------------------------R 4 + R5
V OUTB R 45 + V 45 R3
VIN+ = -----------------------------------------------R3 + R45
R4 R5
R 45 = ------------------R4 + R5
R2
R2
VO = VIN+  1 + ------ – V OUTA  ------
R1
R1
Offset Adjust Gain Adjust
 2010 Microchip Technology Inc.
DS22244B-page 29
MCP4801/4811/4821
6.8
Designing a Double-Precision
DAC
Step 1: Calculate the resolution needed:
Example 6-5 illustrates how to design a single-supply
voltage output capable of up to 24-bit resolution by
using 12-bit DACs. This design is simply a voltage
divider with a buffered output.
As an example, if an application similar to the one
developed in Section 6.6.1 “Design Example:
Design a Bipolar DAC Using Example 6-3 with 12bit MCP4821 or MCP4822” required a resolution of
1 µV instead of 1 mV, and a range of 0V to 4.1V, then
12-bit resolution would not be adequate.
EXAMPLE 6-5:
4.1V/1 µV = 4.1 x 106. Since 222 = 4.2 x 106,
22-bit
resolution
is
desired.
Since
DNL = ±0.75 LSb, this design can be done with
the 12-bit MCP4821 or MCP4822 DAC devices.
Step 2: Since DACB’s VOUTB has a resolution of 1 mV,
its output only needs to be “pulled” 1/1000 to meet
the 1 µV target. Dividing VOUTA by 1000 would
allow the application to compensate for DACB’s
DNL error.
Step 3: If R2 is 100, then R1 needs to be 100 k.
Step 4: The resulting transfer function is shown in the
equation of Example 6-5.
SIMPLE, DOUBLE-PRECISION DAC WITH MCP4821
VDD
VCC+
DACA
VOUTA for Fine Adjustment
VO
R1
R1 >> R2
VDD
DACB
VOUTB for Fine Adjustment
R2
0.1 µF
VCC–
SPI
3-wire
DA
VOUTA = 2.048  G A  ------12
2
DB
V OUTB = 2.048  GB  ------12
2
Gx
=
Gain selection (1x or 2x)
Dn
=
Digital value of DAC (0-4096)
V OUTA R 2 + VOUTB R 1
VO = -----------------------------------------------------R 1 + R2
DS22244B-page 30
 2010 Microchip Technology Inc.
MCP4801/4811/4821
6.9
Building Programmable Current
Source
However, this also reduces the resolution that the
current can be controlled with. The voltage divider, or
“window”, DAC configuration would allow the range to
be reduced, thus increasing resolution around the
range of interest. When working with very small sensor
voltages, plan on eliminating the amplifier’s offset error
by storing the DAC’s setting under known sensor
conditions.
Example 6-6 shows an example of building a
programmable current source using a voltage follower.
The current sensor (sensor resistor) is used to convert
the DAC voltage output into a digitally-selectable
current source.
Adding the resistor network from Example 6-2 would
be advantageous in this application. The smaller
RSENSE is, the less power dissipated across it.
EXAMPLE 6-6:
DIGITALLY-CONTROLLED CURRENT SOURCE
VDD or VREF
VDD
(a) Single Output DAC:
MCP4801
MCP4811
IL
VOUT
DAC
MCP4821
(b) Dual Output DAC:
MCP4802
Load
VCC+
Ib
SPI
MCP4812
VCC–
3-wire
MCP4822
RSENSE
IL
I b = ----

G
=
Gain selection (1x or 2x)
Dn
=
Digital value of DAC (0-255) for MCP4801/MCP4802
=
Digital value of DAC (0-1023) for MCP4811/MCP4812
V OUT

I L = ---------------  ------------R sense  + 1
where Common-Emitter Current Gain
 2010 Microchip Technology Inc.
N
=
Digital value of DAC (0-4095) for MCP4821/MCP4822
=
DAC bit resolution
DS22244B-page 31
MCP4801/4811/4821
NOTES:
DS22244B-page 32
 2010 Microchip Technology Inc.
MCP4801/4811/4821
7.0
DEVELOPMENT SUPPORT
7.1
Evaluation & Demonstration
Boards
The Mixed Signal PICtail™ Demo Board supports the
MCP4801/4811/4821 family of devices. Refer to
www.microchip.com for further information on this
product’s capabilities and availability.
 2010 Microchip Technology Inc.
DS22244B-page 33
MCP4801/4811/4821
NOTES:
DS22244B-page 34
 2010 Microchip Technology Inc.
MCP4801/4811/4821
8.0
PACKAGING INFORMATION
8.1
Package Marking Information
8-Lead DFN (2x3)
AHS
010
25
XXX
YWW
NN
Example:
8-Lead MSOP
XXXXXX
YWWNNN
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
4801E
010256
Example:
MCP4821
E/P e^3 256
1010
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
Example:
Example:
MCP4811E
e3 1010
SN^^
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2010 Microchip Technology Inc.
DS22244B-page 35
MCP4801/4811/4821
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BOTTOM VIEW
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 2010 Microchip Technology Inc.
MCP4801/4811/4821
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 2010 Microchip Technology Inc.
DS22244B-page 37
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 2010 Microchip Technology Inc.
MCP4801/4811/4821
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010 Microchip Technology Inc.
DS22244B-page 39
MCP4801/4811/4821
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 2010 Microchip Technology Inc.
MCP4801/4811/4821
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 2010 Microchip Technology Inc.
DS22244B-page 41
MCP4801/4811/4821
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DS22244B-page 42
 2010 Microchip Technology Inc.
MCP4801/4811/4821
APPENDIX A:
REVISION HISTORY
Revision A (April 2010)
• Original Release of this Document.
Revision B (April 2010)
• Corrected the “Related Products” table on
page 1.
 2010 Microchip Technology Inc.
DS22244B-page 43
MCP4801/4811/4821
NOTES:
DS22244B-page 44
 2010 Microchip Technology Inc.
MCP4801/4811/4821
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
Device
Temperature
Range
Package
Examples:
a)
Device
b)
MCP4801:
MCP4801T:
8-Bit Voltage Output DAC
8-Bit Voltage Output DAC
(Tape and Reel, DFN, MSOP and SOIC only)
10-Bit Voltage Output DAC
10-Bit Voltage Output DAC
(Tape and Reel, DFN, MSOP and SOIC only)
12-Bit Voltage Output DAC
12-Bit Voltage Output DAC
(Tape and Reel, DFN, MSOP and SOIC only)
MCP4811:
MCP4811T:
MCP4821:
MCP4821T:
c)
d)
e)
f)
g)
Temperature Range
E
= -40C to +125C
Package
MC
=
MS
P
SN
=
=
=
(Extended)
8-Lead Plastic Dual Flat, No Lead Package 2x3x0.9 mm Body (DFN)
8-Lead Plastic Micro Small Outline (MSOP)
8-Lead Plastic Dual In-Line (PDIP)
8-Lead Plastic Small Outline - Narrow, 150 mil
(SOIC)
a)
b)
c)
d)
e)
f)
g)
a)
b)
c)
d)
e)
f)
g)
 2010 Microchip Technology Inc.
MCP4801-E/MC:
Extended temperature,
DFN package
MCP4801T-E/MC: Extended temperature,
DFN package,
Tape and Reel
MCP4801-E/MS:
Extended temperature,
MSOP package.
MCP4801T-E/MS: Extended temperature,
MSOP package,
Tape and Reel.
MCP4801-E/P:
Extended temperature,
PDIP package.
MCP4801-E/SN:
Extended temperature,
SOIC package.
MCP4801T-E/SN: Extended temperature,
SOIC package,
Tape and Reel.
MCP4811-E/MC:
Extended temperature,
DFN package
MCP4811T-E/MC: Extended temperature,
DFN package,
Tape and Reel
MCP4811-E/MS:
Extended temperature,
MSOP package.
MCP4811T-E/MS: Extended temperature,
MSOP package,
Tape and Reel.
MCP4811-E/P:
Extended temperature,
PDIP package.
MCP4811-E/SN:
Extended temperature,
SOIC package.
MCP4811T-E/SN: Extended temperature,
SOIC package,
Tape and Reel.
MCP4821-E/MC:
Extended temperature,
DFN package
MCP4821T-E/MC: Extended temperature,
DFN package,
Tape and Reel
MCP4821-E/MS:
Extended temperature,
MSOP package.
MCP4821T-E/MS: Extended temperature,
MSOP package,
Tape and Reel.
MCP4821-E/P:
Extended temperature,
PDIP package.
MCP4821-E/SN:
Extended temperature,
SOIC package.
MCP4821T-E/SN: Extended temperature,
SOIC package,
Tape and Reel.
DS22244B-page 45
MCP4801/4811/4821
NOTES:
DS22244B-page 46
 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-124-6
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2010 Microchip Technology Inc.
DS22244B-page 47
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
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EUROPE
Corporate Office
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Tel: 480-792-7200
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Technical Support:
http://support.microchip.com
Web Address:
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Tel: 91-11-4160-8631
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Tel: 86-592-2388138
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Tel: 86-756-3210040
Fax: 86-756-3210049
01/05/10
DS22244B-page 48
 2010 Microchip Technology Inc.