MICREL MIC2131-1YML

MIC2130/1
High Voltage Synchronous Buck
Control IC with Low EMI Option
General Description
Features
The MIC2130/1 is a high voltage input PWM synchronous
buck controller IC. It is a voltage mode controller with a
fast hysteretic control loop (FHyCL) employed during fast
line and load transients. The internal gate drivers are
designed to drive high current MOSFETs.
The MIC2130/1 can produce output voltages down to 0.7V
with input voltage from 8V to 40V. The MIC2130 family of
control ICs implements fixed frequency PWM control. The
active anti-shoot through drive scheme means a wide
range of external MOSFETs may be used while
maintaining optimum efficiency.
The MIC2131 is the fully functional version of the family
and implements a new feature to minimize EMI. This
function is critical for systems that need to be compliant
with EMI standards throughout the world.
The MIC2130/1 is available in small size 16-pin 4mm x
4mm MLF® package, as well as 16-pin e-TSSOP at a
junction temperature range of –40°C to +125°C.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
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8V to 40V input voltage range
Adjustable output voltages down to 0.7V
LOW EMI option MIC2131
Fixed 150kHz and 400kHz frequency options
Excellent line and load regulation due to fast hysteretic
control loop during transients
Adaptive gate drive allows efficiencies over 95%
Programmable current limit with no sense resistor
Senses low-side MOSFET current
Internal drivers allow 15A output current
Power Good output allow simple sequencing
Programmable soft-start pin
100% increase in current limit (MIC2131)
Output over-voltage protection
Programmable Input UVLO
16-pin e-TSSOP and 16-pin 4mm x 4mm MLF®
Junction temperature range of –40°C to +125°C
Applications
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Industrial/Medical DC/DC point of use power
Printer head drivers
Automotive Systems
Telecom systems
LCD/ Plasma TV
Gaming Machines
Typical Application
98
Efficiency VOUT = 3.3V
@ +25°C
8V
96 12V
94
92
10V
20V
90
88
86
84
82
80
30V
24V
40V
4 5 6 7
OUTPUT CURRENT (A)
MIC2130/1 High Input Voltage Converter
MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 2008
M9999-042108-C
Micrel, Inc.
MIC2130/1
Ordering Information
Part Number
Frequency
Output
Voltage
Low EMI
Junction Temp.
Range
Package
MIC2130-1YML
150kHz
Adj.
No
–40° to +125°C
16-Pin 4x4 MLF®
Pb-Free
®
Pb-Free
Lead Finish
MIC2130-4YML
400kHz
Adj.
No
–40° to +125°C
16-Pin 4x4 MLF
MIC2130-1YTSE
150kHz
Adj.
No
–40° to +125°C
16-Pin e-TSSOP
Pb-Free
MIC2130-4YTSE
400kHz
Adj.
No
–40° to +125°C
16-Pin e-TSSOP
Pb-Free
–40° to +125°C
16-Pin 4x4 MLF
®
Pb-Free
®
Pb-Free
MIC2131-1YML
150kHz
Adj.
Yes
MIC2131-4YML
400kHz
Adj.
Yes
–40° to +125°C
16-Pin 4x4 MLF
MIC2131-1YTSE
150kHz
Adj.
Yes
–40° to +125°C
16-Pin e-TSSOP
Pb-Free
MIC2131-4YTSE
400kHz
Adj.
Yes
–40° to +125°C
16-Pin e-TSSOP
Pb-Free
AVDD
BST
CS
AVDD
PGOOD
Pin Configuration
HSD
HCL/AGND2
SS
SW
FB
PGND
LSD
®
15 BST
HCL/AGND2 3
14 HSD
SS 4
13 SW
FB 5
12 PGND
COMP 6
11 LSD
AGND1 7
10 VDD
9 VIN
16-Pin e-TSSOP (TS)
16-Pin 4mm x 4mm MLF (ML)
April 2008
16 CS
PGOOD 2
EN/UVLO 8
VDD
VIN
AGND1
EN/UVLO
COMP
1
2
M9999-042108-C
Micrel, Inc.
MIC2130/1
Pin Description
Pin Number
MLF-16
Pin Number
e-TSSOP-16
Pin Name
1
3
HCL*
AGND2
2
4
SS
Soft Start (Output): Active at Power-up, Enable, and Current
Limit recovery.
3
5
FB
Feedback (Output): Input to error amplifier. Regulates to
0.7V.
4
6
COMP
Compensation (Output): Pin for external compensation.
5
7
AGND1
Analog Ground.
6
8
EN/UVLO
7
9
VIN
Supply Voltage (Input): 8V to 40V.
8
10
VDD
5V Internal Linear Regulator from VIN. When VIN is <8V,
this regulator operates in drop-out mode. Connect external
bypass capacitor.
9
11
LSD
Low-Side Drive (Output): High-current driver output for
external low-side MOSFET.
10
12
PGND
11
13
SW
Switch Node (Output): High current output driver return.
12
14
HSD
High-Side Drive (Output): High current output-driver for ext.
high-side MOSFET.
13
15
BST
Boost (Output): Provides voltage for high-side MOSFET
driver. The gate drive voltage is higher than the source
voltage by VDD minus a diode drop.
14
16
CS
Current Sense (Output): Current-limit comparator non
inverting input. The current limit is sensed across the lowside FET during the OFF time. Current limit is set by the
resistor in series with the CS pin.
15
1
AVDD
16
2
PGOOD
Pin Function
High Current Limit (Output): The capacitor on this pin sets
the duration of time so that the current limit will be set to
200% of its nominal set current. AGND2 for MIC2130
Enable (Input): Logic low turns the IC off. When the voltage
drops below the band gap reference voltage of the IC the
device turns off. This accurate threshold allows the pin to be
used as an accurate under voltage lockout.
Power Ground: High current return for ext. Low side driver.
Analog Supply Voltage (internal 5V LDO): Connect external
By pass capacitor.
Power Good (Output): High output when VOUT > 90%
nominal.
Note: * indicates that is only used on MIC2131.
April 2008
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Micrel, Inc.
MIC2130/1
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VIN) .......................................................42V
Boot Strapped Voltage (VBST).................................. VIN + 5V
Logic Inputs ...................................................................6.5V
EN Input .........................................................................42V
Ambient Storage Temperature (Ts) ...........–65°C to +150°C
ESD Rating(3) ............................................................... 1.5kV
Supply Voltage (VIN1, VIN2)................................ +8V to +40V
Output Voltage Range.................................. 0.7V to 0.85VIN
Junction Temperature (TJ) ..................–40°C ≤ TJ ≤ +125°C
Package Thermal Resistance
e-TSSOP (θJA) ................................................97.5°C/W
e-TSSOP (θJC) ................................................29.9°C/W
4x4 MLF-16 (θJA) ............................................50.6°C/W
4x4 MLF-16 (θJC) ............................................15.8°C/W
Electrical Characteristics(4)
TJ = 25°C; VEN = VIN = 24V; Frequency = 150kHz; VOUT = 3.3V, unless otherwise specified.
Bold values indicate –40°C≤ TJ ≤ +125°C.
Parameter
Condition
Min
Typ
Max
Units
4
7.5
mA
300
1.3
4.6
180
1.1
1.0
100
5
5.3
µA
V
V
mV
V
VIN, VEN/UVLO, VDD Supply
Total Supply Current,
PWM Mode Supply Current
Shutdown Current
VEN/UVLO Turn-On Threshold
VEN/UVLO Turn-Off Threshold
VIN UVLO Hysteresis
Internal Bias Voltages (AVDD,)
(IDD = 50mA)
Oscillator/PWM Section
VFB = 0.7V; Comp = 3V
(Outputs switching but excluding external MOSFET gate
current.)
VEN = 0V; VIN = 12V
0.7
PWM Frequency
MIC2130/1-1
130
150
170
kHz
PWM Frequency
MIC2130/1-4
360
400
440
kHz
Maximum Duty Cycle
MIC2130/1-1
92
Maximum Duty Cycle
MIC2130/1-4
80
Minimum On-Time
Note 5
%
%
50
ns
Regulation
Feedback Voltage Reference
700
714
mV
Feedback Bias Current
300
1000
nA
VIN = 8V – 40V
Output Voltage
Line Regulation
Output Voltage
1A ≤ IOUT ≤ 10A
Load Regulation
Error Amplifier (each channel)
0.03
%/V
0.5
%
70
dB
(±2%) -40°C to +125°C
686
DC Gain
Output Impedance
2
Transconductance
MΩ
1.2
1.6
2.5
ms
110
115
120
%Nom
Output Over voltage Protection
VFB Threshold
(Latches LSD High)
Delay Blanking Time
1
µs
Soft Start/HCL
Internal Soft Start
Source Current
HCL (MIC2131) Pin Voltage
High
April 2008
1
ILIMIT set to 200% when HCL charges to2.4V
4
2.75
2.4
5
µA
V
M9999-042108-C
Micrel, Inc.
MIC2130/1
Parameter
Condition
HCL Low
ILIMIT set to normal when HCL is low
Min
Typ
Max
0.5
Units
V
HCL Pin Charge Up Current
2.9
µA
HCL Pin Charge Down Current
12
µA
±12
%
LOW/EMI
Frequency Dither Range
Of center freq
Current Sense
170
CS Over Current Trip Point
Program Current
Temperature Coefficient
CS Comparator Sense
Threshold
Power Good
VFB Threshold
PGOOD Voltage Low
Gate Drivers
Rise/Fall Time
Output Driver Resistance
Driver Non-Overlap Time
(Adaptive)
Thermal Shutdown Threshold
200
230
µA
+2300
–5
0
+5
ppm/°C
mV
86
VDD = 5.0V; VFB = 0V; IPGOOD = 1mA
90
0.1
93
0.5
%Nom
V
Into 3000pF
Source
Sink
HSD: Source; VDD = 5V
HSD: Sink; VDD = 5V
23
16
2
1.47
ns
ns
Ω
Ω
LSD: Source; VDD = 5V
LSD: Sink; VDD = 5V
Note 4
2.2
2.1
60
Ω
Ω
ns
TJ Increasing
155
°C
TJ Decreasing
142
°C
(Senses drop across low-side FET)
40
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. Electrical specifications do not apply when operating the device outside of its operating ratings. The maximum allowable power dissipation is a
function of the maximum junction temperature, TJ(Max), the junction-to-ambient thermal resistance, θ JA, and the ambient temperature, TA. The
maximum allowable power dissipation will result in excessive die temperature, and the regulator will go into thermal shutdown.
3. Devices are ESD sensitive. Handling precautions recommended.
4. Guaranteed by design.
5. Minimum on-time before automatic cycle skipping begins.
April 2008
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MIC2130/1
Typical Characteristics
Supply Current
vs. Temperature
5.4
5.2
1.22
Enable Voltage On
vs. Temperature
1.14
1.12
1.10
5.0
1.20
4.8
4.6
1.18
1.08
1.06
1.16
1.04
1.02
24V
4.4
4.2
40V
42V
4.0
1.14
3.8 12V
3.6
1.12
3.4
8V
Shutdown Current
vs. Temperature
800
1.00
0.98
1.10
20 40 60 80
TEMPERATURE (°C)
20 40 60 80
TEMPERATURE (°C)
CS Current
vs. Temperature
210
24V
700
205
600
40V
500
0.702
42V
0.698
195
12V
190
20 40 60 80
TEMPERATURE (°C)
VFB
vs. Temperature
8V
24V
12V
42V
40V
40V
24V
300
200
0.96
0.94
0.700
200
42V
400
Enable Voltage Off
vs. Temperature
12V
0.696
8V
0.694
100
0
8V
AVDD
vs. Temperature
4.98
4.92
0.30
24V
4.96
4.94
185
20 40 60 80
TEMPERATURE (°C)
PGOOD Low @ IPG = 1mA
vs. Temperature
8V
4.88
0.608
0.607
4.86
0.05
4.82
98
0
20 40 60 80
TEMPERATURE (°C)
Efficiency VOUT = 3.3V
@ +25°C
8V
96 12V
94
92
10V
20V
90
88
86
84
82
80
April 2008
30V
24V
40V
4 5 6 7
OUTPUT CURRENT (A)
0.606
20 40 60 80
TEMPERATURE (°C)
Dithered (Spread) Frequency
vs. Temperature
170
165
160
155
150
145
140
135
130
125
120
115
110
PGOOD Threshold
vs. Temperature
0.609
0.15
0.10
4.84
0.612
20 40 60 80
TEMPERATURE (°C)
0.610
0.20
12V
0.692
0.611
0.25
40V
42V
4.90
20 40 60 80
TEMPERATURE (°C)
0.605
155
20 40 60 80
TEMPERATURE (°C)
Switch Frequency
vs. Temperature
VCOMP=1.1V
150
VCOMP=1.5V
145
140
135
VCOMP=2.1V
VCOMP>2.1V
130
20 40 60 80
TEMPERATURE (°C)
6
125
20 40 60 80
TEMPERATURE (°C)
M9999-042108-C
Micrel, Inc.
MIC2130/1
Typical Characteristics (continued)
Load Regulation
@ +85°C
3.324
3.322
8V
12V
3.364
3.362
20V
3.32
3.318
10V
Line Regulation
@ 2 Amp Load
24V
30V
3.316
40V
3.314
3.312
April 2008
4 5 6 7
OUTPUT CURRENT (A)
3.36
3.358
3.356
3.354
5
10
15 20 25 30 35
INPUT VOLTAGE (V)
7
40
M9999-042108-C
Micrel, Inc.
MIC2130/1
Functional Diagram
Figure 1. MIC2130/1 Block Diagram
Functional Description
large load steps, while nominally operating in fixed
frequency PWM mode. Voltage mode control is used to
allow for maximum flexibility and maintains good
transient regulation. The operating input voltage range is
8V to 40V and output can be set from 0.7V up to
0.85*VIN. Start-up surges are prevented using built in
soft start circuitry as well as resistor-less (LSD RDSON is
used to sense load current) current sensing for overload
protection. Other protection features include UVLO, over
voltage latch off protection, Power good signal.
The MIC2130/31 is a voltage mode synchronous buck
controller built for optimum speed and efficiency. It is
designed for wide input voltage range and for high
output power buck converters. Figure 1 shows the block
diagram.
The control loop has two stages of regulation. During
steady-state to medium output disturbances, the loop
operates in fixed frequency, PWM mode while (gm loop),
during a large output voltage disturbance (~±6%
nominal), the loop becomes hysteretic; meaning that for
a short period, the switching MOSFETs are switched on
and off continuously until the output voltage returns to
it’s nominal level. This maximizes transient response for
April 2008
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MIC2130/1
Theory of Operation
A voltage divider monitors the output voltage of the
converter then sensed at the inverting input of the error
amplifier. The non-inverting input of the error amplifier is
connected to the internal 0.7V reference and the two
inputs are compared to produce an analog error voltage.
This error voltage is then fed into the non-inverting input
of the PWM comparator and compared to the voltage
ramp (1.1V to 2.1V) to create the PWM pulses. The
PWM pulses propagate through to the MOSFET drivers
which drive the external MOSFETs to create the power
switching waveform at the set D (duty cycle). This is then
filtered by a power inductor and low ESR capacitor to
produce the output voltage where VOUT ≈ D*VIN. As an
example, due to a load increase or an input voltage
drop, the output voltage will instantaneously drop. This
will cause the error voltage to rise, resulting in wider
pulses at the output of the PWM comparator. The higher
Duty Cycle power switching waveform will cause an
associated rise in output voltage and will continue to rise
until the feedback voltage is equal to the reference and
the loop is again in equilibrium. As with any control
system, it is necessary to compensate this feedback
loop (by selecting the R and C values at the comp pin) in
order to keep the system stable. One of the tradeoffs for
stability is reduced transient regulation performance.
However, the MIC2130/31 has an additional feature to
correct this problem. The MIC2130/31 family features a
fast hysteretic control loop (FHyCL) which bypasses the
gm amp and the feedback compensation network during
fast line and load transients.
The fast hysteretic control loop (FHyCL) operates during
large transients to provide excellent line and load
regulation. Hysteretic mode is invoked when the output
voltage is detected to be ±6% of its regulated value. If
the input voltage step or output load step is large enough
to cause a 6% deviation in VOUT, then the additional
hysteretic control loop functions to return the output
voltage to its nominal set point in the fastest time
possible. This is limited only by the time constant of the
power inductor and output capacitor (an order of
magnitude faster than the gm loop). This scheme is not
used during normal operation because it creates
switching waveforms whose frequency is dependant on
VIN, passive component values and load current. Due to
its large noise spectrum it is only used during surges to
keep switching noise at a known, fixed frequency.
April 2008
Figure 2. Hysteric Block Diagram
Figure 3. Hysteric Waveforms
Soft Start
Figure 4. Soft Start Circuit
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Micrel, Inc.
MIC2130/1
At startup, the Soft-start MOSFET (SSFET) is released
and CSS starts to charge at the rate dVSS/dt–2µA/CSS.
The PNP transistor’s emitter (COMP) starts to track VSS
(plus a junction voltage ≈0.65). When (COMP) reaches
the lower end of the PWM ramp voltage at 1.10V,
switching pulses will begin to drive the power MOSFETs.
This voltage rise continues on the COMP pin until the
control loop reaches the regulation point. During this soft
start period, the gate drive pulses to the MOSFET will
start at the minimum pulse width and increase up to the
duty cycle D required for regulation. The COMP voltage
can be anywhere from 1.1V to 2.1V which corresponds
to a duty cycle D of 0-85%. VSS will however, continue to
rise as the PNP base-emitter junction becomes reverse
biased. The SS pin is allowed to rise to 2.5V (four diode
drops) max to allow fast response to fault conditions.
During large over current or short circuit conditions, i.e.,
where current limit is detected and VOUT is <60% of
nominal, the SSFET is momentarily switched on. This
discharges CSS to ~150mV at which point, it re-starts the
soft start cycle once again. During soft start, hysteretic
comparators are disabled.
Duty Cycle D can be written in terms of VCOMP
D = (0.85) x VCOMP – (0.935) or VCOMP = (D + 0.935)/0.85
Protection
There exits four different types of output protection.
1. Output “hard short” over current
2. Output “soft short” over current
3. Output under voltage
4. Output over voltage
Current Limit
The MIC2130/31 uses the RDSON of the low-side
MOSFET to sense overcurrent conditions. The lower
MOSFET is used because it displays much lower
parasitic oscillations during switching then the upper
MOSFET. Using the low-side MOSFET RDSON as a
current sense is an excellent method for circuit
protection. This method will avoid adding cost, board
space and power losses taken by discrete current sense
resistors.
Hard Short
Generally, the MIC2130/31 current limit circuit acts to
provide a fixed maximum output current until the
resistance of the load is so low that the voltage across it
is no longer within regulation limits. At this point (60% of
nominal output voltage), the part employs Hiccup mode.
During Hiccup mode, the output pulses stop and the soft
start cap is discharged and soft start mode begins. After
the soft start time, if the output voltage is still 60% low,
then the process repeats again and continues until the
short is removed. Hard short current mode is initiated to
protect down stream loads from excessive current and
also reduces overall power dissipation in the PWM
converter components during a fault.
Example: VIN = 12V; VOUT = 3.3V; D = VOUT/VIN = 0.275
VCOMP = 1.424V; i.e. the steady-state DC Value of VCOMP
when D = 0.275
T1 is the time for VCOMP to charge up to 1.1V, therefore,
VSS is one diode drop below VCOMP.
T2 is the time for VCOMP to charge up to (D + 0.935)/ 0.85
+ 1.1V.
Soft Start time = T1 + T2
Soft Short
Before “Hard Short” mode (also called “hiccup mode”)
occurs “soft short” current limiting is provided to prevent
system shutdown or disturbance if the overload is only
marginal. When the load current exceeds the current
limit by only a few ma for a short time (milliseconds) then
the hard short mode is not desired. Instead, the “Soft
Short” loop is used. When the current limit comparator
senses an over current it then starts to discharge the SS
Cap with a 40µA current source. The current limit
comparator gets reset every cycle so if the short still
exist during the next cycle then the SS cap will continue
to get discharged with the 40µA current source. The
comp pin follows the SS pin (Figure 4) and the gm
control loop will lower the output voltage accordingly for
as long as the short exists. So, instead of shutting down
the output as in a hard short, the output is gently and
slightly reduced until the over current condition
discontinues. If however the short increase to the point
of lowering the output to 60%, then hard short will result.
The fast hysteretic control loop (FHyCL) is initiated by a
6% drop in output voltage and it is not desired during an
over current condition therefore, the FHyCL feature will
Where
T1 = (1.1-Vdiode) x CSS/2µA; the time until output
pulsing starts at minimum duty.
And,
T2 = (1/0.85) x D x CSS/ 2µA; the time until output
pulsing increases to D.
The compensation capacitors at the COMP pin (CCOMP =
Cc1+Cc2 in Figure 4) will also need to charge up to
VCOMP. This charging time starts as soon as MOSFET
(SSFET) is released. Depending upon the size of the
CCOMP, the charging time could be greater than T1+T2.
CCOMP could be used for the Soft Start cap by leaving SS
pin open.
TcCOMP = (1/0.85) x D x CCOMP/5µA: The time until output
pulsing increases to D.
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MIC2130/1
be disabled during an over current condition.
The larger the inductor current, the more negative VDS
becomes. This is utilized for the detection of over current
by passing a known fixed current source (200µA)
through a resistor RCS which sets up an offset voltage
such that when 200µA x RCS = IDRAIN x RDSON the
MIC2130/31’s over current trigger is set. This disables
the next high side gate drive pulse. After missing the
high side pulse, the over current (OC) trigger is reset. If
on the next low side drive cycle, the current is still too
high i.e., VCS is ≤ 0V, another high side pulse is missed
and so on. Thus reducing the overall energy transferred
to the output and VOUT starts to fall. As this successive
missing of pulses results in an effectively lower switching
frequency, power inductor ripple currents can get very
high if left unlimited. The MIC2130/31 therefore limits
Duty Cycle during current limit to prevent currents
building up in the power inductor and output capacitors.
Under Voltage
A ±6% comparator monitors the output voltage and will
initiate the fast hysteretic control loop (FHyCL) to
regulate the output. A comparator monitors the output
voltage and sets PGOOD true when the output reaches
90% of the regulated output.
Over Voltage
If the voltage at the FB pin is detected to be 15% higher
than nominal for >2µs, then the controller is stopped
from switching immediately and latched off. Switching
can be re-started by taking EN below the channel’s
enable threshold and re-enabling or re-cycling power to
the IC.
Current Limit Setting
The Simple Method
RCS = IOUT x RDSON(max)/200µA.
Accurate Method
For designs where ripple current is significant when
compared to IOUT, or for low duty cycle operation,
calculating the current setting resistor RCS should take
into account that one is sensing the peak inductor
current and that there is a blanking delay of
approximately 100ns.
Figure 5.
During the normal operation of a synchronous Buck
regulator, as the lower MOSFET is switched on, its drain
voltage will become negative with respect to ground as
the inductor current continues to flow from Source-toDrain. This negative voltage is proportional to output
load current, inductor ripple current and MOSFET
RDSON.
Figure 7.
I PK = I OUT +
I RIPPLE =
VOUT ⋅ (1 − D )
FSWITCH ⋅ L
I SET = I PK −
RCS =
Figure 6.
I RIPPLE
2
VOUT ⋅ TDLY
L
I SET ⋅ RDSON (max)
I CS (min)
D = Duty Cycle
FSWITCH = Switching Frequency
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MIC2130/1
L = Power inductor value
Power Good Output
The power good output (PG) will go high only when
output is above 90% of the nominal set output voltage.
TDLY = Current limit blanking time ~ 100ns
ICS(min) = 180µA
VDD Regulator
The internal regulator provides a regulated 5V for
supplying the analog circuit power (AVDD). VDD also
powers the MOSFET drivers. VDD is designed to operate
at input voltages down to 8V. The AVDD supply should be
connected to VDD through an RC filter to provide
decoupling of the switching noise generated by the
MOSFET drivers taking large current pulses from the
VDD regulator.
Example:
Consider a 12V to 3.3V @ 5A converter with 7.3µH
power inductor and 93% efficiency at a 5A load and an
LSD FET of RDSON of 10mΩ (typical values).
D=
VIN
VOUT
⋅ Efficiency
I RIPPLE =
I PK
3.3 ⋅ (1 − 0.306 )
= 2.1A
150kHz ⋅ 7.3 µH
Gate Drivers
The MIC2130/31 is designed to drive both high side and
low side N-Channel MOSFETs to enable high switching
speeds with the lowest possible losses. The high side
MOSFET gate driver is supplied by a bootstrap capacitor
CBST connected at the SW pin and the BST pin. A high
speed diode (a Schottky diode is recommended)
between the VDD pin and BST pin is required as shown
in Figure 8. This provides the high side MOSFET with a
constant VGS drive voltage equal to VDD - VDIODE.
2 .1
=5+
= 6.05 A
2
I SET + 6.05 −
RCS =
3.3 ⋅ 100ns
= 6.00 A
7.3 µH
6.00 ⋅ 10mΩ
= 333Ω
180 µA
(332 std. value)
Using the simple method here would result in a current
limit point lower than desired.
This equation sets the minimum current limit point of the
converter, but maximum will depend upon the actual
inductor value and RDSON of the MOSFET under current
limit conditions. This could be in the region of 50%
higher and should be considered to ensure that all the
power components are within their thermal limits unless
thermal protection is implemented separately.
Figure 8.
HCL (MIC2131 only)
The high current limit (HCL) is a function of the MIC2131
only. It allows for twice the output load current (for a time
T determined by the HCL cap) before the current limit
comparator trips. During the time T, the current sense
current source (200µA nominal) is increased to 400µA.
T = CHCL * 2/13µ = CHCL * 153.85 *1e3
Where CHCL is the cap at the HCL pin
When HSD goes high, this turns on the high side
MOSFET and the SW node rises sharply. This is
coupled through the bootstrap capacitor CBST and
Diode DBST becomes reverse biased. The MOSFET
Gate is held at VDD-VDIODE above the Source for as long
as CBST remains charged. This bias current of the High
side driver is <10mA so a 0.1µF to1 µF is sufficient to
hold the gate voltage with minimal droop for the power
stroke (High side switching) cycle, i.e. ∆BST = 10mA x
6µs / 0.1µF = 567mV. When the low side driver turns on
every switching cycle, any lost charge from CBST is
replaced via DBST as it becomes forward biased.
Therefore minimum BST voltage is VDD – 0.5V.
The Low side driver is supplied directly from VDD at
nominal 5V.
Frequency Dithering
The MIC2131 has an additional useful feature. The
switching frequency is dithered ±12% in order to spread
the frequency spectrum over a wider range to lower the
EMI noise peaks generated by the switching
components. A pseudo random generator is used to
generate the ±dithering which further reduces the EMI
noise peaks.
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When the High side driver is turned off, the inductor
forces the voltage at the switching node (low side
MOSFET drain) towards ground to keep current flowing.
When the SW pin is detected to have reached 1V, the
top MOSFET can be assumed to be off and the low side
driver output is immediately turned on. There is also a
short delay between the low side drive turning off and
the high side driver turning on. This is fixed at ~80ns to
allow for large gate charge MOSFETs to be used.
Adaptive Gate Drive
There is a period when both driver outputs are held off
(‘dead time’) to prevent shoot through current flowing.
Shoot through current flows if both MOSFETS are on
momentarily as the same time and reduces efficiency
and can destroy the FETs. This dead time must be kept
to a minimum to reduce losses in the free wheeling
diode which could either be an external Schottky diode
placed across the lower MOSFET or the internal
Schottky diode implemented in some MOSFETs. It is not
recommended, for high current designs, to rely on the
intrinsic body diode of the power MOSFET. These
typically have large forward voltage drops and a slow
reverse recovery characteristic which will add significant
losses to the regulator. Dependant upon the MOSFETs
used, the dead time could be required to be 150ns or
20ns. The MIC2130/31 solves this variability issue by
using an adaptive gate-drive scheme.
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Application Information
VOUTPK −PK ≈ I RIPPLE ⋅ ESR +
144244
3
Passive Component Selection Guide
Transition losses in the power MOSFETs are not defined
by inductor value. However, the inductor value is
responsible for the ripple current which causes some of
the resistive losses. These losses are proportional to
IRIPPLE2. Minimizing inductor ripple current therefore
reduces resistive losses and can be achieved by
choosing a larger value inductor. This will generally
improve efficiency by reducing the RMS current flowing
in all of the power components. The actual value of
inductance is really defined by space limitations, RMS
rating (IRMS) and saturation current (ISAT) of available
inductors. If we look at the newer flat wire inductors,
these have higher saturation current ratings than the
RMS current rating for lower values and as inductance
value increases, these figures get closer in value. This
mirrors what happens in the converter with ISAT
analogous to the maximum peak switch current and IRMS
analogous to output current. As inductance increases, so
ISWITCHpk tends towards IOUT. This is a characteristic that
makes these types of inductor optimal for use in high
power buck converters such as MIC2130/31.
To determine the ISAT and IRMS rating of the inductor, we
should start with a nominal value of ripple current. This
should typically be no more than IOUT(max)/2 to minimize
MOSFET losses due to ripple current mentioned earlier.
Therefore:
LMIN ~ 2
VO
I O ⋅ FSWITCH
⎛
VO
⋅ ⎜⎜1 −
⎝ VIN ⋅ Efficiency
ESR
Noise
For tantalum capacitors, ESR is typically >40mΩ which
usually makes loop stabilization easier by utilizing a
pole-zero (type II) compensator.
Due to the many advantages of multi-layer ceramic
capacitors, among them, cost, size, ripple rating and
ESR, it can be useful to use these in many cases.
However, one disadvantage is the CV product. This is
lower than tantalum. A mixture of one tantalum and one
ceramic can be a good compromise which can still utilize
the simple type II compensator.
With ceramic output capacitors only, a double-pole,
double-zero (type III) compensator is required to ensure
system stability. Loop compensation is described in
more detail later in the data sheet.
Ensure the RMS ripple current rating of the capacitor is
above IRIPPLE ⋅ 0.6 to improve reliability.
Input Capacitor Selection
The input filter needs to supply the load current when the
high-FET is on and should to limit the ripple to the desire
value. The CIN ripple rating for a converter is typically
IOUT/2 under worst case duty cycle conditions of 50%.
⎞
⎟⎟
⎠
IRMSCIN = IOUT × D × (1 − D )
ILSAT > 1.25 x IOUT(max)
Any value chosen above LMIN will ensure these ratings
are not exceeded.
In considering the actual value to choose, we need to
look at the effect of ripple on the other components in
the circuit. The chosen inductor value will have a ripple
current of:
(1 − D )
FSWITCH
⋅
Where D = VOUT/(VINxeff)
It is however, also important to closely decouple the
Power MOSFETs with 2 x 10µF Ceramic capacitors to
reduce ringing and prevent noise related issues from
causing problems in the layout of the regulator. The
ripple rating of CIN may therefore be satisfied by these
decoupling capacitors as they allow the use of perhaps
one more ceramic or tantalum input capacitor at the
input voltage node to decouple input noise and localize
high di/dt signals to the regulator input.
VOUT
L
This value should ideally be kept to a minimum, within
the cost and size constraints of the design, to reduce
unnecessary heat dissipation.
Power MOSFET Selection
The MIC2130/31 drives N-channel MOSFETs in both the
high-side and low-side positions. This is because the
switching speed for a given RDSON in the N-Channel
device is superior to the P-Channel device.
There are different criteria for choosing the high- and
low-side MOSFETs and these differences are more
significant at lower duty cycles such as 12V to 1.8V
conversion. In such an application, the high-side
MOSFET is required to switch as quickly as possible to
minimize transition losses (power dissipated during rise
Output Capacitor Selection
The output capacitor (COUT) will have the full inductor
ripple current ILRMS flowing through it. This creates the
output switching noise which consists of two main
components:
April 2008
Capacitor
Noise
If therefore, the need is for low output voltage noise
(e.g., in low output voltage converters), VOUT ripple can
be directly reduced by increasing inductor value, Output
capacitor value or reducing ESR.
ILRMS > 1.04 x IOUT(max)
I RIPPLE ~
I RIPPLE ⋅ TON
2 ⋅C
1442OUT
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dissipation of 1.2W per MOSFET package. This can be
altered if the final design has higher allowable package
dissipation.
Look at lower MOSFET first:
Pdis_max = 1.2 W = Ps + Pt
For the low side FET, Pt is small because VDSOFF is
clamped to the forward voltage drop of the Schottky
diode. Therefore:
RDSON(max) ~ 1.2/IFETRMS2
Example: For 12V to 1.8V @ 10A
and fall times). Whereas the low-side MOSFET can
switch slower, but must handle larger RMS currents.
When duty cycle approaches 50%, the current carrying
capability of the upper MOSFET starts to become critical
also and can sometimes require external high current
drivers to achieve the necessary switching speeds.
MOSFET loss = Static loss + Transition loss
Static loss (Ps) = IFETRMS2 x RDSON
Transition loss (Pt) = IOUT x (tr+tf) x VDSOFF x FSWITCH/2
tr + tf = Rise time + Fall time
RDSON(max) < 14mΩ
It is important to remember to use the RDSON(max) figure
for the MOSFET at the maximum temperature to help
prevent thermal runaway (as the temperature increases,
the RDSON increases).
Due to the worst case driver currents of the MIC2130/31,
the value of tr + tf simplifies to:
tr + tf (ns) = ∆Qg (nC)
∆Qg can be found in the MOSFET characteristic curves
∆Qg(max) should be limited so that the low side MOSFET
is off within the fixed 80ns delay before the high side
driver turns on.
High side MOSFET:
For the high side FET, the losses should ideally be
evenly spread between transition and static losses. Use
the C of the VIN range to balance the losses.
Pt = Pdis_max/2 = 0.6 = IOUT x ∆Qg x VINMID x FSWITCH/2
∆Qg(max) < 0.6 x 2 / (IOUT x VINMID x FSWITCH)
RDSon is calculated similarly for the high side MOSFET:
VDSOFF = Voltage across MOSFET when it is off
2
IFETRMS =
RDSON(max) ~ 0.6 / IFETRMS2
Using previous example:
2
( I + I X ⋅ IY + IY )
D⋅ X
3
∆Qg(max) < 20nC
RDSON(max) < 35mΩ
Note that these are maximum values based upon
thermal limits and are not targeted at the highest
efficiency. Selection of lower values is recommended to
achieve higher efficiency designs.
Limits to watch out for:
QgTOTAL < 1500 nC/VIN
Total of both high side and low side MOSFET Qg value
at VGS = 5V for both channels.
Example: @ VIN(max) = 13.2V,
QgTOTAL < 1500/13.2 = 114nC
IX = IOUT – IRIPPLE/2
IY = IOUT + IRIPPLE/2
D_on = TON x FSWITCH
high-side FET on time
D_off = TON x FSWITCH
low-side FET on time
D_on = D = VO/(VIN x eff) since it changes depending on
which MOSFET we are calculating losses for.
High-side FET TON = D_on/FSWITCH
The lower MOSFET is not on for the whole time that the
upper MOSFET is off due to the fixed 80ns high side
driver delay. Therefore, there is an 80ns term subtracted
from the lower FET on time equation.
∆QgLOW < 120nC
Maximum turn on gate charge for the low side MOSFET
to ensure proper turn off before high side MOSFET is
switched on.
Low-side FET TON = (1-D_on)/FSWITCH – 80ns
There are many MOSFET packages available which
have varying values of thermal resistance and can
therefore dissipate more power if there is sufficient
airflow or heat sink externally to remove the heat.
However, for this exercise we can assume a maximum
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∆VSW
VOut
VOut
=
=
Gain of the
∆d(s) ∆d(s) * D D Max * D
Control Loop Stability and
Compensation
G PwrS (s) =
Figure 10 shows the simplified system schematic. The
internal transconductance error amplifier is used for
compensating the voltage feedback loop by placing a
capacitor (C1) in series with a resistor (R1) and another
capacitor C2 in parallel from the COMP pin-to-ground.
(Note: Ceramic output caps may require type III
compensation).
Power Stage
PWM
Comparator
VREF
VCOMP
gm
C1
Q=
D (s)
VSW
VRAMP
C2
VOUT
L
C
RESR
E stored
R Load
=
E Lost
L/C out
Figure 10 Simplified System Schematic
H(s) =
R LS
V
= ref
R LS + R HS Vout
=
GPWRS
VSW
GFLT
The phase of the open loop is the phase of all the blocks
in the loop added together.
The phase of T(s) is
VOUT
θ T (s) = θ ea + θ PWMcomp + θ PwrS + θ Flt + θ fb
θ T (s) = θ ea + θ Mod + θ fb
VFB
T(s)
Where
H(s)
θ Zero1 =phase lead due to Zero1
In the system block diagram in figure 11
Gea(s) = gm x Zcomp Gain of the Error amp
where gm =1.5ms and
Z comp
θ pole1 = phase lag due to pole1
θ PWMcomp = 0° ,
⎛ 1 ⎞
⎟⎟
⎜⎜
⎝ sC 2 ⎠
θ PwrS = 0°
θ fb = 0°
therefore;
θ Mod = 0°
The phase of the filter includes the complex poles of LC
and the Zero caused by the ESR of the COUT.
∆D
D
0.85
G PWMcomp (s) =
= Max =
= 0.85
∆Vcomp ∆Vramp 2.1 − 1.1
The filter has 2 poles at F0 and a zero at Fesr
Gain of the PWM comparator
April 2008
θ ea = −θ pole0 + θ Zero1 − θ pole1
θ pole0 = phase lag due to the pole at the origin
Figure 11 System Block Diagram
⎛
1 ⎞
⎟
= ⎜⎜ R1 +
sC1 ⎟⎠
⎝
therefore;
D Max
Vout
Vout
=
*
∆Vramp D * D Max ∆Vramp * D
θ T (s) = θ ea + θ Mod + θ flt + θ fb
∠T(s) = θ T (s) = θ ea + θ PWMcomp + θ PwrS + θ Flt + θ fb
D (s)
Gain of the feedback
T(s) = Gea(s) x GMod(s) x Gflt(s) x Hfb(s) and
And the phase is:
GPWMComp
Fesr =
G Mod (s) = G PWMcomp (s) * G PWRsw (s)
T(s) = Gea(s) x GPWMcomp(s) x GPwrs(s) x Gflt(s) x Hfb(s)
VCOMP
1
2π R esr Cout
1
LCout
network
For simplicity, combine the PWM comparator gain and
the Power stage gain and call it the modulator gain.
In order to have a stable system when the gain of T(s) =
1 ⇒ (0db) the phase has to be greater (less negative)
than -180°. The amount the phase is greater than -180°
is called the phase margin, typically 30 to 60 and is a
key parameter predicting the stability of the system and
how much overshoot and undershoot the system
exhibits during transients.
The open loop transfer function is:
Gea(s) =
gm ZCOMP
(Parallel loaded)
ω0 =
RLS
VE
Gain of the Filter
and
RLOAD
RHS
VREF
1 + sR esr C out
s
s2
+ 2
1+
Qω 0 ω 0
where:
VIN
R1
VFB
G Flt (s) =
θ Flt = −180° at F0 and +90° at Fesr
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The peak Gain equals the low freq gain plus the Q =
26.2 + 13.6 = 39.9db.
It is desired that T(s) (the open loop transfer function)
have a cross over frequency (Fco) of 1/10 the Switching
frequency at 15kHz. It is require that ∠T(j2πFco) (the
phase of T(s) at Fco), to be greater than -180° by at
least the phase margin. By inspecting the Gain plot of
GMod(s) at 15kHz, GMod(s) has a gain of about 3.9db.
Therefore, to make T(j2πFco) = 1→ 0db;
T(s) = Gea(s) x GMod(s) x Hfb(s) = 1 at Fco
Hfb = Vref/Vout = 0.7/3.3 = 0.212 → -13.5db
|Gea|db = |T|db - |GMod|db -|Hfb|db = 0-3.9db – (-13.5db) =
9.6db ═>3.02 The error amp needs 9db of gain at Fco.
Therefore gm x ZComp = 3.02 at 15kHz.
The location of the error amp’s zero and poles are
selected in order to achieve the desired phase margin of
T(s). For the maximum phase boost at the cross over
Frequency (Fco), place the first Zero1 of the EA at
Fco/10 since the effect of its phase boost will be at the
maximum at Fco. Likewise, place the pole of the EA at
least 10 x Fco so the effects of its phase lag will be at a
minimum at Fco. Therefore, use R1 = 2k; C1 = 0.068µF;
C2 = 470pF.
Example:
VIN = 24V; VOUT = 3.3V; IOUT = 10A; L = 7.3µH; COUT =
660µF; Resr = 40mΩ; Fsw = 150KHz
The gain and phase of the modulator and filter is:
GMod(s) x Gflt(s)
This is the gain
VOUT
(s) in Figure 12
Vcomp
A computer generated plot of GMod(s) x Gflt(s) is shown in
Figure 12.
gm Error Amplifier
Usually, it is undesirable to have high error amplifier gain
at high frequencies otherwise high frequency noise
spikes at large amplitude would be present at the output.
Hence, gain should be permitted to fall off at high
frequencies. At low frequency, it is desired to have high
open-loop gain to attenuate the power line ripple. Thus,
the error amplifier gain should be allowed to increase
rapidly at low frequencies.
The transfer function for the internal gm error amplifier
with R1, C1, and C2 at the comp pin is given by the
following equation:
Figure 12. Modulator Transfer Function
There is a -180° phase change near F0. At frequencies
greater then F0 the phase increases towards -90° due to
the zero of Fesr. The phase effects of poles and zeros
start a decade below and finish a decade above the
frequency of a pole or zero. Therefore, at the frequency
of a pole or zero the phase effect is only half of the final
value. At the complex pole 2.3kHz the phase is -90 and
would be -180 at 23kHz if not for the +90 phase lead of
the zero at around 6kHz due to the esr of the filter
capacitors. (Actually, the phase gain plots reach their
final values asymptotically).
By inspecting Figure 12 the DC and low frequency gain
of GMod = 20Log(0.85 x 24) = 26.2db; F0 = 2.3kHz; Fesr =
6kHz and Q is 13.6db.
Gea (s ) = g m
⎡
⎤
⎢
⎥
1
+
R
1
⋅
s
⋅
C
1
⎥
⋅⎢
⎢
C1 ⋅ C 2 ⋅ s ⎞ ⎥
⎛
⎟⎥
⎢ s ⋅ (C1 + C 2) ⋅ ⎜1 + R1 ⋅
C1 ⋅ C 2 ⎠ ⎦
⎝
⎣
The above equation can be simplified by assuming
C2<C1,
⎡
⎤
1 + R1 ⋅ s ⋅ C1
Gea (s ) = g m ⋅ ⎢
⎥
⎣ s ⋅ (C1) ⋅ (1 + R1 ⋅ C 2 ⋅ s ) ⎦
From the above transfer function, one can see that R1
and C1 introduce a zero and R1 and C2 a pole at the
following frequencies:
Fzero1= 1/2 π × R1 × C1 Fpole1 = 1/2 π × C2 × R1
[email protected] = 1/2 π × C1
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Figure 14 shows the gain and phase curves for the
above transfer function with R1 = 2k, C1 = 0.068µF, C2
= 470pF, and gm = 0.0015Ω–1. It can be seen that at
15kHz, the error amplifier exhibits approximately 9.6db
of gain and 170° of phase. Figure 13 shows the open
loop transfer function T(s) with these compensation
values. It has a cross over frequency of 15KHz and
phase margin of 60˚.
Figure 14. The Open Loop T(s)
Gain and Phase
Figure 13. Error Amp Gain and Phase
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Package Information
16-Pin e-TSSOP (TS)
16-Pin 4mm x 4mm MLF® (ML)
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MIC2130/1
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2007 Micrel, Incorporated.
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