SY58611U 3.2Gbps Precision, LVDS 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58611U is a 2.5V, high-speed, fully differential LVDS 2:1 MUX capable of processing clocks up to 2.5GHz and data up to 3.2Gbps. SY58611U is optimized to provide a buffered output of the selected input with less than 20ps of skew and less than 10pspp total jitter. Patented MUX Isolation design reduces crosstalk and provides superior signal integrity. The differential inputs include Micrel’s unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals, (AC- or DC-coupled) as small as 100mVPK (200mVpp) without any levelshifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an integrated reference voltage (VREF-AC) is provided to bias the VT pin. The output is LVDS compatible, with rise/fall times guaranteed to be less than 120ps. The SY58611U operates from a 2.5V ±5% supply and is guaranteed over the full industrial temperature range (–40°C to +85°C). For applications that require CML or LVPECL output, consider the SY58609U and SY58610U, 2:1 MUX with 400mV and 800mV output swings respectively. The SY58611U is part of Micrel’s high-speed, Precision Edge® product line. Datasheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Functional Block Diagram Precision Edge® Features • Selects between two sources and provides buffered copy of the selected input signal • Fail Safe Input – Prevents output from oscillating when input is invalid or removed • Guaranteed AC performance over temperature and voltage: – DC-to > 3.2Gbps throughput – <420ps typical propagation delay (IN-to-Q) – <120ps rise/fall times • Unique, patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS) • Unique, patented MUX input isolation design minimizes adjacent channel crosstalk • Ultra-low jitter design – <1psRMS cycle-to-cycle jitter – <10psPP total jitter – <1psRMS random jitter – <10psPP deterministic jitter • 2.5V ±5% power supply operation • Industrial temperature range: –40°C to +85°C • Available in 16-pin (3mm x 3mm) MLF® package Applications • • • • All SONET clock distribution Fibre Channel clock and data distribution Gigabit Ethernet clock or data distribution Backplane distribution Markets • • • • DataCom and Telecom Storage ATE Test and Measurement Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com March 2007 M9999-030607-A [email protected] or (408) 955-1690 Micrel, Inc. SY58611U Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish SY58611UMG MLF-16 Industrial 611U with Pb-Free bar-line indicator NiPdAu Pb-Free SY58611UMGTR(2) MLF-16 Industrial 611U with Pb-Free bar-line indicator NiPdAu Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. Pin Configuration Truth Table SEL Output 0 IN0 Selected 1 IN1 Selected 16-Pin MLF® (MLF-16) Pin Description Pin Number Pin Name Pin Function 1, 4 VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” subsection. 2, 3 VREF-AC0, VREF-AC1 Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01µF low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is ±0.5mA. See “Input Interface Applications” subsection. Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-Coupled differential signals as small as 100mV (200mVPP). Each pin of the pairs internally terminates with 50Ω to the VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See “Input Interface Applications” subsection. 5, 6 IN1, /IN1 15, 16 IN0, /IN0 7 SEL Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open. The input-switching threshold is VCC/2. 8, 13 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the VCC pins as possible. 9, 12 /Q, Q LVDS Differential Output Pair: Differential buffered output copy of the selected input signal. The output swing is typically 325mV. Normally terminated 100Ω across the output (Q and /Q). See “LVDS Output Interface Applications” subsection. 10, 11 GND, Exposed pad 14 NC March 2007 Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pin. No connect. 2 M9999-030607-A [email protected] or (408) 955-1690 Micrel, Inc. SY58611U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) ............................... –0.5V to +4.0V Input Voltage (VIN) .......................................–0.5V to VCC LVDS Output Current (IOUT)..................................±10mA Input Current Source or Sink Current on (IN, /IN) ...............±50mA Current (VREF) Source or sink current on VREF-AC(4) ..............±0.5mA Maximum operating Junction Temperature ......... 125°C Lead Temperature (soldering, 20sec.) .................. 260°C Storage Temperature (Ts) ....................–65°C to +150°C Supply Voltage (VCC)..................... +2.375V to +2.635V Ambient Temperature (TA) ................... –40°C to +85°C Package Thermal Resistance(3) MLF® Still-air (θJA) ............................................ 60°C/W Junction-to-Board (ψJB)......................... 33°C/W DC Electrical Characteristics(5) TA = –40°C to +85°C unless otherwise stated. Symbol Parameter VCC Power Supply Voltage Range ICC Power Supply Current RIN Condition Min Typ Max Units 2.375 2.5 2.625 V 40 60 mA 45 50 55 Ω 100 110 Ω No load, max. VCC Input Resistance (IN-to-VT, /IN-to-VT) RDIFF_IN Differential Input Resistance (IN-to-/IN) 90 VIH Input HIGH Voltage (IN, /IN) 1.2 VCC V VIL Input LOW Voltage (IN, /IN) 0.2 VIH–0.1 V VIN Input Voltage Swing (IN, /IN) see Figure 3a, Note 6 0.1 1.0 V VDIFF_IN Differential Input Voltage Swing (|IN - /IN|) see Figure 3b 0.2 VIN_FSI Input Voltage Threshold that Triggers FSI VREF-AC AC Reference Voltage VT_IN Voltage from Input to VT V 30 IVREF-AC = + 0.5mA VCC-1.3 100 mV VCC-1.0 V 1.28 V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA values are determined for a 4-layer board in still-air number, unless otherwise stated. 4. Due to the limited drive capability, use for input of the same package only. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIN (max) is specified when VT is floating. March 2007 3 M9999-030607-A [email protected] or (408) 955-1690 Micrel, Inc. SY58611U LVDS Output DC Electrical Characteristics(7) VCC = +2.5V ±5%, RL = 100Ω across the output pair; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Min Typ VOUT Output Voltage Swing (Q, /Q) See Figure 3a 250 325 Max Units mV VDIFF_OUT Differential Output Voltage Swing |Q-/Q| See Figure 3b 500 650 mV VOCM Output Common Mode Voltage (Q, /Q) See Figure 5b 1.125 1.20 ∆VOCM Change in Common Mode Voltage (Q, /Q) See Figure 5b –50 1.275 V 50 mV Max Units LVTTL/CMOS DC Electrical Characteristics(7) VCC = 2.5V ±5%; TA = –40°C to + 85°C, unless otherwise stated. Symbol Parameter Condition Min VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current -125 IIL Input LOW Current -300 Typ 2.0 V 0.8 V 30 µA µA Notes: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. March 2007 4 M9999-030607-A [email protected] or (408) 955-1690 Micrel, Inc. SY58611U AC Electrical Characteristics(8) VCC = +2.5V ±5%, RL = 100Ω across the output pair; Input tr/tf < 300ps, TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Min fMAX Maximum Frequency NRZ Data 3.2 VOUT > 200mV tPD Propagation Delay IN-to-Q Clock VIN: 100mV-200mV VIN: > 200mV SEL-to-Q Typ Max Units Gbps 2.5 3 190 330 150 280 150 470 ps 420 ps 450 ps 20 ps tSkew Input-to-Input Skew Note 9, 10 Part-to-Part Skew Note 11 150 ps tJitter Data Random Jitter Note 12 1 psRMS Deterministic Jitter Note 13 10 psPP Cycle-to-Cycle Jitter Note 14 1 psRMS Clock Total Jitter tr, tf 5 GHz Note 15 Output Rise/Fall Times (20% to 80%) At full output swing. 40 Duty Cycle Differential I/O 47 80 10 psPP 120 ps 53 % Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9. Input-to-Input skew is the time difference between the two inputs and one output, under identical input transitions. 10. Input-to-Input Skew is included in IN-to-Q propagation delay. 11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature, same transition edge, and no skew at the edges at the respective inputs. 12. Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX. 23 13. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 –1 PRBS pattern. 14. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1, where T is the time between rising edges of the output signal. 12 15. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value. March 2007 5 M9999-030607-A [email protected] or (408) 955-1690 Micrel, Inc. SY58611U function will eliminate a metastable condition and latch the output to the last valid state. No ringing and no undetermined state will occur at the output under these conditions. The output recovers to normal operation once the input signal returns to a valid state with a typical swing greater than 30mV. Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to “Typical Operating Characteristics” for detailed information. Functional Description Fail-Safe Input (FSI) The input includes a special fail-safe circuit to sense the amplitude of the input signal and to latch the output when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mVPK (200mVPP), typically 30mVPK. Refer to Figure 1b. Input Clock Failure Case If the input clock fails to a floating, static, or extremely low signal swing such that the voltage swing across the input pair is significantly less than 100mV, FSI Timing Diagrams Figure 1a. Propagation Delay Figure 1b. Fail-Safe Feature March 2007 6 M9999-030607-A [email protected] or (408) 955-1690 Micrel, Inc. SY58611U Figure 1c. SEL-to-Q Delay Input Stage Figure 2. Simplified Differential Input Buffer Single-Ended and Differential Swings Figure 3b. Differential Swing Figure 3a. Single-Ended Swing March 2007 7 M9999-030607-A [email protected] or (408) 955-1690 Micrel, Inc. SY58611U Typical Characteristics VCC = 2.5V, GND = 0V, VIN = 100mV, RL = 100Ω across the output pair, TA = 25°C, unless otherwise stated. March 2007 8 M9999-030607-A [email protected] or (408) 955-1690 Micrel, Inc. SY58611U Functional Characteristics VCC = 2.5V, GND = 0V, VIN = 325mV, RL = 100Ω across the output pair, TA = 25°C, unless otherwise stated. March 2007 9 M9999-030607-A [email protected] or (408) 955-1690 Micrel, Inc. SY58611U Functional Characteristics (continued) VCC = 2.5V, GND = 0V, VIN = 325mV, RL = 100Ω across the output pair, TA = 25°C, unless otherwise stated. March 2007 10 M9999-030607-A [email protected] or (408) 955-1690 Micrel, Inc. SY58611U Input Interface Applications Figure 4a. CML Interface (DC-Coupled) Figure 4b. CML Interface (AC-Coupled) Figure 4c. LVPECL Interface (DC-Coupled) Option: May connect VT to VCC Figure 4d. LVPECL Interface (AC-Coupled) March 2007 Figure 4e. LVDS Interface 11 M9999-030607-A [email protected] or (408) 955-1690 Micrel, Inc. SY58611U LVDS Output Interface Applications LVDS specifies a small swing of 325mV typical, on a nominal 1.2V common mode above ground. The common mode voltage has tight limits to permit large variations in the ground between and LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep EMI low. Figure 5b. LVDS Common Mode Measurement Figure 5a. LVDS Differential Measurement Related Products and Support Documentation Part Number Function Data Sheet Link SY58609U 4.25Gbps Precision, CML 2:1 MUX with Internal Termination and Fail Safe Input http://www.micrel.com/_PDF/HBW/sy58609u.pdf SY58610U 3.2Gbps Precision, LVPECL 2:1 MUX with Internal Termination and Fail Safe Input http://www.micrel.com/_PDF/HBW/sy58610u.pdf HBW Solutions New Products and Termination Application Notes http://www.micrel.com/page.do?page=/productinfo/as/HBWsolutions.shtml March 2007 12 M9999-030607-A [email protected] or (408) 955-1690 Micrel, Inc. SY58611U Package Information 16-Pin (3mm x 3mm) MLF® (MLF-16) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2007 Micrel, Incorporated. March 2007 13 M9999-030607-A [email protected] or (408) 955-1690