PRELIMINARY K6E1004C1B-C/B-L CMOS SRAM Document Title 256Kx4 Bit (with OE) High Speed Static RAM(5V Operating), Evolutionary Pin out. Revision History Rev. No. History Draft Data Rev. 0.0 Initial release with Design Target. Feb. 1st 1997 Design Target Rev.1.0 Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary. Jun. 1st 1997 Preliminary Rev. 2.0 Release to Final Data Sheet. 2.1. Delete Preliminary. 2.2. Delete 17ns, L-version and Industrial Temperature Part. 2.3. Delete VOH1=3.95V. 2.4. Delete Data Retention Characteristics and Wave form. 2.5. Relex operating current. Speed Previous Now 15ns 120mA 120mA 17ns 110mA 20ns 100mA 118mA Feb. 6th 1998 Final Rev.3.0 3.1. Add Low power Version. 3.2. Add Data Retention chcracteristics. Jul. 28th 1998 Final Remark The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev. 3.0 July 1998 PRELIMINARY K6E1004C1B-C/B-L CMOS SRAM 256K x 4 Bit (with OE)High-Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time 15, 20ns(Max.) • Low Power Dissipation Standby (TTL) : 20mA(Max.) (CMOS) : 5mA(Max.) 1mA(Max) L-Ver. Only Operating K6E1004C1B-15 : 120mA(Max.) K6E1004C1B-20 : 118mA(Max.) • Single 5.0V±10% Power Supply • TTL Compatible Inputs and Outputs • Fully Static Operation - No Clock or Refresh required • Three State Outputs • 2V Minimum Data Retention ; L-Ver. only • Standard Pin Configuration K6E1004C1B-J : 28-SOJ-400A The K6E1004C1B is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits. The K6E1004C1B uses 4 common input and output lines and has at output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6E1004C1B is packaged in a 400 mil 28-pin plastic SOJ. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION(Top View) A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O1~I/O4 Row Select Clk Gen. Data Cont. Pre-Charge Circuit Memory Array 512 Rows 512x4 Columns I/O Circuit & Column Select CLK Gen. A0 1 28 Vcc A1 2 27 A17 A2 3 26 A16 A3 4 25 A15 A4 5 24 A14 A5 6 23 A13 A6 7 A7 8 21 A11 A8 9 20 N.C SOJ 22 A12 A9 10 19 I/O4 A10 11 18 I/O3 CS 12 17 I/O2 OE 13 16 I/O1 Vss 14 15 WE A9 A10 A11 A12 A13 A14 A15 A16 A17 PIN FUNCTION CS Pin Name WE A0 - A17 OE Address Inputs WE Write Enable CS Chip Select OE Output Enable I/O1 ~ I/O 4 -2- Pin Function Data Inputs/Outputs VCC Power(+5.0V) VSS Ground N.C No Connection Rev. 3.0 July 1998 PRELIMINARY K6E1004C1B-C/B-L CMOS SRAM ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Voltage on Any Pin Relative to VSS Rating Unit VIN, VOUT -0.5 to 7.0 V VCC -0.5 to 7.0 V Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature PD 1.0 W TSTG -65 to 150 °C TA 0 to 70 °C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C) Parameter Symbol Min Typ Max Unit Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 V Input High Voltage VIH 2.2 - VCC+0.5** V Input Low Voltage VIL -0.5* - 0.8 V * VIL(Min) = -2.0V a.c(Pulse Width ≤ 10ns) for I ≤ 20mA . ** VIH (Max) = VCC + 2.0V a.c (Pulse Width ≤10ns) for I ≤ 20mA DC AND OPERATING CHARACTERISTICS (TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified) Min Max Unit Input Leakage Current Parameter ILI VIN=VSS to VCC -2 2 µA Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC -2 2 µA Operating Current ICC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA 15ns - 120 mA 20ns - 118 - 20 mA Normal - 5 mA L-ver Standby Current Symbol Test Conditions ISB Min. Cycle, CS=VIH ISB1 f=0MHz, CS≥VCC-0.2V, VIN≥VCC-0.2V or VIN≤0.2V - 1 mA Output Low Voltage Level VOL IOL=8mA - 0.4 V Output High Voltage Level VOH IOH=-4mA 2.4 - V CAPACITANCE*(TA=25°C, f=1.0MHz) Symbol Test Conditions MIN Max Unit Input/Output Capacitance Item CI/O VI/O=0V - 8 pF Input Capacitance C IN VIN=0V - 6 pF * Capacitance is sampled and not 100% tested. -3- Rev. 3.0 July 1998 PRELIMINARY K6E1004C1B-C/B-L CMOS SRAM AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.) TEST CONDITIONS Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V +5.0V 480Ω 480Ω DOUT DOUT 255Ω 255Ω 30pF* 5pF* * Including Scope and Jig Capacitance READ CYCLE Parameter Symbol K6E1004C1B-15 K6E1004C1B-20 Min Max Min Max Unit Read Cycle Time tRC 15 - 20 - ns Address Access Time tAA - 15 - 20 ns Chip Select to Output tCO - 15 - 20 ns Output Enable to Valid Output tOE - 8 - 10 ns Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output tLZ 3 - 3 - ns tOLZ 0 - 0 - ns tHZ 0 6 0 8 ns Output Disable to High-Z Output tOHZ 0 6 0 8 ns Output Hold from Address Change tOH 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - ns Chip Selection to Power DownTime tPD - 15 - 20 ns -4- Rev. 3.0 July 1998 PRELIMINARY K6E1004C1B-C/B-L CMOS SRAM WRITE CYCLE Parameter K6E1004C1B-15 Symbol K6E1004C1B-20 Min Max Min Max Unit Write Cycle Time tWC 15 - 20 - ns Chip Select to End of Write tCW 10 - 12 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 10 - 12 - ns Write Pulse Width(OE High) tWP 10 - 12 - ns Write Pulse Width(OE Low) tWP1 15 - 20 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 8 0 10 ns Data to Write Time Overlap tDW 7 - 9 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 3 - 3 - ns TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL , WE=VIH) tRC Address tAA tOH Data Out Valid Data Previous Valid Data TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO CS tHZ(3,4,5) tOHZ tOE OE tOLZ tLZ(4,5) Data out tOH Valid Data VCC ICC Current ISB tPU tPD 50% 50% -5- Rev. 3.0 July 1998 PRELIMINARY K6E1004C1B-C/B-L CMOS SRAM NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV space from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tWR(5) tAW OE tCW(3) CS tWP(2) tAS(4) WE tDW Data in High-Z tDH Valid Data tOHZ(6) High-Z(8) Data out TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tAW tWR(5) tCW(3) CS tAS(4) tWP1(2) WE tDW Data in High-Z tDH Valid Data tWHZ(6) tOW High-Z(8) Data out -6- (10) (9) Rev. 3.0 July 1998 PRELIMINARY K6E1004C1B-C/B-L CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled) tWC Address tAW tWR(5) tCW(3) CS tWP(2) tAS(4) WE tDW Data in High-Z Valid Data tLZ Data out tDH High-Z tWHZ(6) High-Z(8) High-Z NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. -7- Rev. 3.0 July 1998 PRELIMINARY K6E1004C1B-C/B-L CMOS SRAM FUNCTIONAL DESCRIPTION CS WE OE Mode I/O Pin Supply Current H X X* Not Select High-Z ISB, ISB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L L X Write DIN ICC * X means Don′t Care. DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C) Parameter Symbol Test Condition Min. Typ. Max. Unit 2.0 - 5.5 V VCC=3.0V, CS≥VCC-0.2V VIN≥VCC-0.2V or VIN≤0.2V - - 0.4 mA See Data Retention Wave form(below) 0 - - ns 5 - - ms VCC for Data Retention VDR CS≥VCC-0.2V Data Retention Current IDR Data Retention Set-Up Time tSDR Recovery Time tRDR * Data Retention Characteristic is for L-ver only. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 4.5V VIH VDR CS≥VCC - 0.2V CS GND -8- Rev. 3.0 July 1998 PRELIMINARY K6E1004C1B-C/B-L CMOS SRAM Units:millimeters/Inches PACKAGE DIMENSIONS 28-SOJ-400A #28 10.16 0.400 #15 11.18 ±0.12 0.440 ±0.005 9.40 ±0.25 0.370 ±0.010 0.20 #1 18.82 MAX 0.741 0.69 MIN 0.027 18.41 ±0.12 0.725 ±0.005 ( 1.27 ) 0.050 3.76 MAX 1.32 ( ) 0.148 0.052 0.43 ( 0.95 ) 0.0375 +0.10 -0.05 0.008 +0.10 -0.002 #14 0.10 0.004MAX +0.10 -0.05 0.017 +0.004 -0.002 1.27 0.050 +0.10 -0.05 0.028+0.004 -0.002 0.71 -9- Rev. 3.0 July 1998