SANYO LV23200T

Ordering number : ENN8301
Bi-CMOS IC
LV23200T
For Home Stereo System
1-chip Tuner IC Incorporating PLL
Overview
The LV23200T is a one-chip tuner IC incorporating PLL for home stereo system.
Functions
• AM tuner
Changeover of the constant in RFAMP, MIX, OSC, IF AMP, DET, AGC, SD, OSC BUFF, IF BUFF, and
AGC modes.
• FM tuner
1stIFAMP, IF limiter AMP, DET (COIL type) , S-METER, SD, AFC, IF BUFF.
• MPX
PLL STEREO DECODER, forced MONO, AUDIO MUTE, function to prevent interference from a
neighboring station, PILOT canceling function.
• PLL frequency synthesizer.
Features
• Tuner IC and PLL IC integrated into one chip.
• MPX-VCO incorporated and without need of adjustment.
• FM/AM output level independent setting possible.
• MOS transistor for active LPF incorporated.
Specitications
Maximum Ratings at Ta = 25 °C
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
Unit
VCC max
VCC
7.0
V
VDD max
VDD
6.0
V
Operating temperature
Topr
-20 to +80
°C
Storage temperature
Tstg
-40 to +125
°C
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
92706 / 72005 MS PC B8-8475 No.8301-1/17
LV23200T
Operating Condition at Ta = 25 °C
Parameter
Symbol
Recommended supply voltage
Operating supply voltage range
Conditions
Ratings
Unit
VCC
5.0
V
VDD
3.0
V
4.5 to 6.0
V
2.7 to 3.3
V
VCC op
VDD op1
X’tal oscillation = 4.5MHz
* Handle pin 34 with care because its electrostatic voltage at C = 200pF and R = 0Ω is 110 V.
Operating Characteristics at Ta = 25°C, VCC = 5.0V, VDD = 3.0V
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
[Current dissipation]
FM tuner block
ICCFM
No input in FM mode
25
35
45
mA
AM tuner block
ICCAM
No input in AM mode
14
24
34
mA
PLL block
IDDFM
X’tal = 4.5MHz, No input at tuner
2.0
3.0
4.0
mA
550
650
mVrms
28
33
dBµV
35
40
dBµV
0.4
1.5
[FM-FE characteristics (MPX)] : FM-IF (5PIN) input, fc = 10.7MHz, fm = 1kHz, 75kHzdev (L+R = 90%, Pilot = 10%)
Demodulation output
3dB sensitivity 1
VO
LS1
VIN = 100dBµV
VIN = 70dBµV reference, input at -3dB
450
∗at input of FIFA (pin 1)
3dB sensitivity 2
LS2
VIN = 100dBµV reference, input at -3dB
∗at input of FMFA (pin 5)
Total harmonic distortion
THD1
VIN = 100dBµV, MONO
Signal-to-noise ratio
S/N
VIN = 100dBµV
AM suppression ratio
AMR
VIN = 100dBµV, AM = 30%
36
40
SD sensitivity
SD-1
0%mod, SD sensitivity mode 1
43
50
57
dBµV
Total harmonic distortion
THD2
VIN = 100dBµV, MAIN-MOD
0.5
1.5
%
Separation
SEP
VIN = 100dBµV, L output/R output
ST sensitivity
VL
VIN = 100dBµV, (L+R)+Pilot
3.0
Mute attenuation
MUTE
VIN = 100dBµV, L output
60
dB
Carrier leakage
CL
VIN = 100dBµV, (L+R)+Pilot
40
dB
70
30
30
76
%
dB
dB
45
dB
5.5
%
[AM characteristics] : fc = 999kHz, fm = 1kHz, 30%mod
Demodulation output 1
VO1
VIN = 23dBµV, 30%mod, fm = 1kHz
50
80
130
mVrms
Demodulation output 2
VO2
VIN = 80dBµV, 30%mod, fm = 1kHz
170
240
310
mVrms
Signal-to-noise ratio 1
S/N1
VIN = 23dBµV
15
20
Signal-to-noise ratio 2
S/N2
VIN = 80dBµV
48
54
Total harmonic distortion
THD
VIN = 80dBµV
SD sensitivity
SD-ON
0%mod (Internally fixed sensitivity)
Internal return resistance
Rf
XIN
Built-in output resistance
Rd
XOUT
Hysteresis width
VHIS
CE, CL, DI
Output high level voltage
VOH
PD ; IO = -1mA
Output low level voltage
VOL1
VOL2
PD ; IO = 1mA
1.0
V
BO ; IO = 1mA
0.25
V
BO ; IO = 5mA
1.25
V
VOL3
DO ; IO = 1mA
0.25
V
VOL4
AOUT ; IO = 1mA, AIN = 2.0V
0.5
V
5.0
µA
0.9
µA
14
dB
dB
0.4
1.3
%
24
34
dBµV
[PLL characteristics]
Output high level voltage
Input high level current
IIH1
CE, CL, DI ; VI = 6.0V
IIH2
XIN ; VI = VDD
8
MΩ
250
kΩ
0.1VDD
V
VDD-1.0
0.16
V
IIH3
AIN ; VI = 6.0V
200
nA
IIL1
CE, CL, DI ; VI = 0V
5.0
µA
IIL2
XIN ; VI = 0V
0.9
µA
IIL3
AIN ; VI = 0V
200
nA
0.16
Continued on next page.
No.8301-2/17
LV23200T
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
Output off-leak current
typ
Unit
max
IOFF1
BO, AOUT ; VO = 10V
5.0
µA
IOFF2
DO ; VO = 6.0V
5.0
µA
”H” level 3-state off-leak current
IOFFH
PD ; VO = 6.0V
0.01
200
nA
”L” level 3-state off-leak current
IOFFL
PD ; VO = 0V
0.01
200
nA
Package Dimensions
unit : mm
3253B
No.8301-3/17
LV23200T
Description of Pin Functions
No.
1
Functions
FM 1stIF-AMP input
Voltage (V)
Internal Equivalent Circuit
Remarks
1.6V
Input impedance ri (Rin).
Rin = 330Ω
1
Rin
2
REG
2.2V
Reference voltage of AM/FM IF/MPX
2
3
FM 1st IF-AMP output
3.0V
block.
Vreg = 2.2V
Output impedance ro (Rout).
Rout = 300Ω
3
Rout
4
AM MIX output
VCC
MIX coil used between pins 4 and 8
(VCC voltage).
4
5
FM IF input
Vreg
Input impedance ri (Rin).
Rin = 330Ω
5
Rin
2
6
GND
7
AM IF input
0V
AM/FM IF/MPX block GND
2.2V
Input impedance ri (Rin).
Rin = 2kΩ
7
Rin
2
8
VCC
5.0V
AM/FM IF/MPX block VCC
Continued on next page.
No.8301-4/17
LV23200T
Continued from preceding page.
No.
9
Functions
FM DET
Voltage (V)
Internal Equivalent Circuit
Remarks
VCC
Recommended detection coil.
600BCAS−10790Z
10
Phase comparator filter
VCC-1.0V
R = 10kΩ
10
R
11
Pilot filter
VCC-1.0V
R = 10kΩ
11
R
12
L output
13
R output
2.5V
Output impedance ro (Rout).
Rout = 7.7kΩ
12
Rout
15
CE
( 13 )
−
Chip enable pin
At changeover from “L” to “H”:
15
Address latching.
S
At changeover from “H” to “L”:
Data latching.
16
DI
−
Serial data input pin
Sets data in synchronization with rise
16
17
CL
−
Data clock input pin.
17
18
DO
of data clock.
S
S
−
Data output pin
18
Outputs various data in
synchronization with fall of data clock
in the OUT mode.
Continued on next page.
No.8301-5/17
LV23200T
Continued from preceding page.
No.
Functions
Voltage (V)
Internal Equivalent Circuit
Remarks
19
X IN
−
Clock for internal reference
20
X OUT
−
Connect a 4.5 MHz crystal oscillator.
19
20
21
VDD
3.0V
AM/FM IF/MPX block VDD
22
Pilot canceling output
Vreg
Output impedance ro (Rout).
Rout = 30kΩ
22
2
Rout
23
AM detection output
0.8V (FM)
Output impedance ro (Rout).
Vreg (AM)
Rout = 10kΩ
Rout
23
24
MPX input
Vreg
MPX inverse input pin.
RNF = 20kΩ
RNF
24
25
PLL input
Vreg
Input impedance ri (Rin).
Rin = 20kΩ
25
Rin
26
FM detection output
Vreg+0.7V
Output impedance ro (Rout).
26
Rout = 3.3kΩ
Adjusts separation using the
Rout
capacitance value of a section
between this pin and GND.
Continued on next page.
No.8301-6/17
LV23200T
Continued from preceding page.
No.
27
Functions
SD monitor
Voltage (V)
Internal Equivalent Circuit
VDD
Remarks
Active “L”
VDD
Open collector.
27
28
FMS meter and AM AGC
0.2V (FM)
Internal load resistance R = 13.9kΩ
outputs
0.8V (AM)
Determines the SD response speed
during SEEK by a capacitor externally
connected to pin 28.
28
R
29
PD
−
PLL charge pump output pin.
29
30
AIN
−
31
AOUT
−
Nch MOS transistor for PLL active low
30
pass filter.
31
32
AM OSC
VCC
OSC coil used between pins 32 and 8
(VCC voltage).
32
33
AFC
Vreg
Enables adjustment of the FM SD
band width by external resistor
between pins 33 and 2 (Vreg voltage).
33
Continued on next page.
No.8301-7/17
LV23200T
Continued from preceding page.
No.
34
Functions
AM RF input
Voltage (V)
Internal Equivalent Circuit
Remarks
Vreg
Use pin 34 with the same potential as
for pin 32 (AFC voltage).
34
35
FM OSC input
VCC
V CC
35
36
BO
−
Use pin 35 through pull-up to pin 8
(VCC voltage) by resistance load.
Pin dedicated for output.
36
No.8301-8/17
LV23200T
Composition of DI control data (serial data input)
(1) IN1 mode
Address
R3
R1
(2)R-CTR
R2
R0
TEST0
DNC
IFS
CTE
(11)IFS
(13)Don’t care
DLC
(10)PD-C
DVS
(3)IF-CTR
SDC1
SNS
GT1
(15)SDC
P15
GT0
P14
DZ1
P13
P12
DZ0
P11
UL0
UL1
P10
DOC2
P9
DOC1
P8
(1)P-CTR
P7
P6
P5
P4
P3
P2
P1
0 0 0 1 0 1 0 0
P0
DI
(2) IN2 mode
Address
TEST2
TEST1
(12)TEST
(3)IF-CTR
(8)DZ-C
(7)UNLOCK
(6)DO-C
SDC0
(15)SDC
DOC0
STSW
(5)BDSW
(14)STSW
BDSW1
DNC
(4)IFSW
(13)Don’t care
IFSW
BO
(9)O-PORT
0
1
1 0 0 1 0 1 0 0
0
DI
Description of DI control Data
No.
Control block data
(1)
Programmable
divider data
Description
Related data
• Data to set the dividing number of programmable divider
Binary value with P15 assumed to be MSB. LSB varies according to DVS and SNS.
(* : Don’t care)
P0 to P15
DVS
DVS, SNS
SNS
LSB
set dividing number (N)
Actual dividing
1
*
P0
272 to 65535
Twice the set value
0
1
P0
272 to 65535
Set value
0
0
P4
4 to 4095
Set value
* P0 to P3 invalid when LSB : P4
• To select the signal input (FMIN, AMIN) to the programmable divider and to change the input
frequency range.
(* : Don’t care)
DVS
SNS
Input
Operation frequency range
10 to 160MHz
1
*
FMIN
0
1
AMIN
2 to 40MHz
0
0
AMIN
0.5 to 10MHz
Continued on next page.
No.8301-9/17
LV23200T
Continued from preceding page.
No.
Control block data
(2)
Reference
divider data
R0 to R3
Description
Related data
• Reference frequency (fref) selection data
R3
R2
R1
R0
Reference frequency
0
0
0
0
25kHz
0
0
0
1
25kHz
0
0
1
0
25kHz
0
0
1
1
25kHz
0
1
0
0
12.5kHz
0
1
0
1
6.25kHz
0
1
1
0
3.125kHz
0
1
1
1
3.125kHz
1
0
0
0
5kHz
1
0
0
1
5kHz
1
0
1
0
5kHz
1
0
1
1
1kHz
1
1
0
0
3kHz
1
1
0
1
15kHz
1
1
1
0
PLL INHIBIT+X’tal OSC
1
1
1
1
PLL INHIBIT
* PLL INHIBIT
• The programmable divider and IF counter stop, with FMIN, AMIN, HCTR and LCTR inputs being in
the pull-down condition (GND), and the charge pump has the high impedance.
(3)
IF counter
• IF counter counting start data
control data
CTE = 1 : Counting start
IFS
= 0 : Counting start
CTE
GT0, GT1
(4)
MUTE
control data
• Determines the counting time of universal counter
GT1
GT0
Counting time
Wait time
0
0
4ms
3 to 4ms
0
1
8ms
3 to 4ms
1
0
16ms
3 to 4ms
1
1
32ms
3 to 4ms
• Data to determine the output of output port IFSW, controlling the MUTE function.
“Data” = 0 : at receiving
1 : MUTE
IFSW
(5)
FM/AM BAND
selection
control data
• Data to determine the output of output port BDSW, controlling selection of BAND.
“Data” = 0 : AM
1 : FM
BDSW
Continued on next page.
No.8301-10/17
LV23200T
Continued from preceding page.
No.
Control block data
(6)
DO pin
control data
Description
Related data
• Data to control DO pin output
UL0, UL1
DOC2
DOC1
DOC0
DOC0
0
0
0
Open
DOC1
0
0
1
Low when unlock is detected.
DOC2
0
1
0
end-UC (See the item with asterisk below)
0
1
1
Open
1
0
0
Open
1
0
1
Low when SDON
1
1
0
Low when stereo
1
1
1
Open
CTE
DO pin condition
• The open condition is selected at power ON/reset.
~
~
* IF counter counting end check
~
~
DO pin
1 Counting start
2 Counting end
3 CE : HI
1 With end-UC set and IF counter starting (CTE = 0→1), DO pin opens automatically.
2 At end of counting of the IF counter, DO pin goes LOW and check on counting end can be made.
3 DO pin opens when serial data is entered/output (CE pin : Hi)
Note : DO pin is always in the open condition during data input (IN1 and IN2 modes, during CE : Hi
period), regardless of DO pin control data (DOC0 to 2). In the DO pin condition during data output
(OUT mode, CE-Hi period), the content of internal DO serial data is output in synchronization with
CL pin signal, regardless of DO pin control data (DOC).
(7)
Unlock detection
data
• Phase error (φE) detection width selection data to judge if PLL is locked.
DOC0
Phase error exceeding the detection width is judged to mean that PLL is locked
DOC1
(* : don’t care)
UL0, UL1
UL1
UL0
φE Detection width
0
0
Stop
Open
0
1
0
Direct output of φE
1
*
±6.67µs
φE extended by 1 to 2 ms
DOC2
Detection output
* DO pin is LOW. Serial data output : UL = 0.
(8)
Phase
comparator
control data
DZ0, DZ1
• Data to control the dead zone of phase comparator
DZ1
DZ0
Dead zone mode
0
0
DZA
0
1
DZB
1
0
DZC
1
1
DZD
Dead zone width : DZA<DZB<DZC<DZD
(9)
Output port data
• Data to determine the output of output ports BO1 and BO2
“Data” = 0 : OPEN
BO
(10)
Charge pump
control data
DLC
1 : Low
• Data to enforce control of charge pump output
DLC
Charge pump output
0
Normal
1
Forced to LOW
* In case of dead lock because of VCO oscillation stop when the VCO control voltage (Vtune) is 0V, it
is possible to clear dead lock by setting the charge pump output to LOW and V tune to VCC. (Dead
lock clear circuit)
(11)
IFS
(12)
LSI test data
• Normally, set Data = 1. Setting Data = 0 causes the input sensitivity worsening mode and the
sensitivity decreases by about 10 to 30mVrms.
• LSI test data
TEST0
TEST0 to 2
TEST1
All to be set to “0”
TEST2
All set to zero at power ON/reset
(13)
DNC
• Set data = 0.
Continued on next page.
No.8301-11/17
LV23200T
Continued from preceding page.
No.
Control block data
(14)
Forced monaural
Description
Related data
• Data to determine the output of output port STSW, controlling the forced stereo functions.
“Data” = 0 : MONO
control data
1 : STEREO
STSW
(15)
• Data to determine the output of output ports SDC, controlling the SD sensitivity
SD sensitivity
“Data” = SDC0 : 0, SDC1 : 0 → SD sensitivity 1 = 50dBµV (Typ)
control data
SDC0 : 0, SDC1 : 1 → SD sensitivity 2 = 52dBµV (Typ)
SDC0 : 1, SDC1 : 0 → SD sensitivity 3 = 57dBµV (Typ)
SDC
SDC0 : 1, SDC1 : 1 → SD sensitivity 4 = 62dBµV (Typ)
* Above data values indicate the difference of SD sensitivity levels and are reference values.
DO control data (serial data output) composition
(1) OUT mode
C0
C1
C2
C3
C4
C5
C6
C7
C8
(3)IF-CTR
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
UL
(1)IN-PORT
C19
DO
0
0 1 0 1 0 1 0 0
SDIND
DI
STIND
Address
Description of DO output data
No.
Control block data
(1)
Stereo and SD
• Data latching stereo and SD indicator conditions.
indicators
Latching made in the data output (OUT) mode.
control data
Description
SDIND←Stereo indicator condition
0 : ST ON, 1 : ST OFF
STIND←SD indicator condition
0 : SD ON, 1 : SD OFF
Related data
STIND, SDIND
(2)
PLL unlock data
• Data latching the content of unlock detection circuit
UL←0 : At unlock
UL
(3)
IF counter,
binary counter
UL0
UL1
1 : At lock or in the detection stop mode
• Data latching the content of IF counter (20-bit binary counter)
CTE
C19←MSB of binary counter
GT0
C0 ←LSB of binary counter
GT1
C19 to C0
No.8301-12/17
LV23200T
Serial data input (IN1/IN2) tSU, tHD, tEL, tES, tEH≥0.75µs tLC<0.75µs
CL : Normally Hi
tEL
tES
tEH
CE
CL
tSU
DI
tHD
B0
B1
B2
B3
A0
A1
A2
A3
P0
P1
P2
P3
R0
R1
R2
R3
tLC
Internal data
CL : Normally Low
tEL
tES
tEH
CE
CL
tSU
DI
tHD
B0
B1
B2
B3
A0
A1
A2
A3
P0
P1
P2
P3
R0
R1
R2
R3
tLC
Internal data
Serial data output (OUT) tSU, tHD, tEL, tES, tEH≥0.75µs tDC, tDH<0.35µs
CL : Normally Hi
tEL
tES
tEH
CE
CL
tSU
DI
tHD
B0
B1
B2
B3
A0
A1
A2
A3
tDC
tDC
I2
DO
I1
tDH
UL
C3
C2
C1
C0
CL : Normally Hi
tEL
tES
tEH
CE
CL
tSU
DI
tHD
B0
B1
B2
B3
A0
A1
A2
A3
tDC
DO
tDC
I2
I1
tDH
UL
C3
C2
C1
C0
(Note) DO pin is an Nch open drain pin, so that the data varying time (tDC and tDH) differs depending on the pull-up
resistance and substrate capacity.
No.8301-13/17
LV23200T
~
Serial data timing
VIH
tCL
VIH
VIL
VIH
VIH
DI
VIL
tSU
VIH
VIL
tHD
tEL
~ ~ ~ ~ ~ ~
CL
VIL
VIL
DO
Internal data latch
VIH
VIL
~ ~ ~ ~ ~ ~ ~
tCH
~ ~
CE
tES
tDC
tDC
tEH
tDH
tLC
Old
New
VIH
VIL
VIH
VIH
VIH
DI
VIL
tSU
tHD
DO
Internal data latch
~ ~ ~ ~ ~ ~ ~
VIH
VIL
~
tCL
VIH
VIL
tEL
VIL
tES
tDC
tEH
~ ~ ~ ~ ~ ~
tCH
~
CE
CL
~
<< When CL stops at the “L” level >>
tDH
tLC
Old
New
<< When CL stops at the “H” level >>
Parameter
Symbol
Pin
Conditions
Min
Typ
Max
Unit
Data setup time
tSU
DI, CL
0.75
µs
Data hold time
tHD
DI, CL
0.75
µs
Clock “L” level time
tCL
CL
0.75
µs
Clock “H” level time
tCH
CL
0.75
µs
CE wait time
tEL
CE, CL
0.75
µs
CE setup time
tES
CE, CL
0.75
µs
CE hold time
tEH
CE, CL
0.75
Data latch change time
tLC
Data output time
tDC
DO, CL
Differs depending on the pull-up resistance
tDH
DO, CE
and substrate capacity
µs
0.75
µs
0.35
µs
No.8301-14/17
LV23200T
Block Diagram
No.8301-15/17
LV23200T
Test Circuit
No.8301-16/17
LV23200T
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the
performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
products or equipment.
SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any
and all semiconductor products fail with some probability. It is possible that these probabilistic failures
could give rise to accidents or events that could endanger human lives, that could give rise to smoke or
fire, or that could cause damage to other property. When designing equipment, adopt safety measures
so that these kinds of accidents or events cannot occur. Such measures include but are not limited to
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This catalog provides information as of July, 2005. Specifications and information herein are subject
to change without notice.
PS No.8301-17/17