L5987 3 A step-down switching regulator Preliminary Data Features ■ 3 A DC output current ■ 2.9 V to 18 V input voltage ■ Output voltage adjustable from 0.6 V ■ 250 kHz switching frequency, programmable up to 1 MHz ■ Internal soft-start and inhibit ■ Low dropout operation: 100 % duty cycle ■ Voltage feed-forward ■ Zero load current operation ■ Over current and thermal protection ■ VFQFPN3x3-8L and HSOP8 package Applications ■ Consumer: STB, DVD, DVD recorder, car audio, LCD TV and monitors ■ Industrial: PLD, PLA, FPGA, chargers ■ Networking: XDSL, modems, DC-DC modules ■ Computer: Optical storage, hard disk drive, printers, audio/graphic cards ■ LED driving Figure 1. August 2008 VFQFPN8 3x3 mm HSOP8 exposed pad Description The L5987 is a step down switching regulator with 3.5 A (minimum) current limited embedded power MOSFET, so it is able to deliver up to 3 A current to the load depending on the application conditionals Section 5.7 and Section 5.8). The input voltage can range from 2.9 V to 18 V, while the output voltage can be set starting from 0.6 V to VIN. Having a minimum input voltage of 2.9 V, the device is suitable also for 3.3 V bus. Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz. The QFN and the HSOP package with exposed pad allow reducing the RthJA down to 60 °C/W and 40 °C/W respectively. Application circuit Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/42 www.st.com 42 Contents L5987 - L5987A Contents 1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 7 2/42 5.1 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.7 Maximum DC output current L5987A (HSOP8) . . . . . . . . . . . . . . . . . . . . 15 5.8 Maximum DC output current L5987 (VFQFPN) . . . . . . . . . . . . . . . . . . . . 15 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4.1 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.2 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.5 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.7 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 L5987 - L5987A Contents 8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3/42 Pin settings L5987 - L5987A 1 Pin settings 1.1 Pin connection Figure 1. Pin connection (top view) OUT SYNCH GND INH FSW COMP 1.2 FB Pin description Table 1. 4/42 VCC Pin description N. Type 1 OUT Description Regulator output 2 SYNCH Master/slave synchronization. When it is left floating, a signal with a phase shift of half a period respect to the power turn on is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal, with zero phase shift. Connecting together the SYNCH pin of two devices, the one with higher frequency works as master and the other one as slave; so the two powers turn on have a phase shift of half a period. 3 INH A logical signal (active high) disable the device. With INH higher than 1.9 V the device is OFF and with INH lower than 0.6 V the device is ON. 4 COMP 5 FB 6 FSW The switching frequency can be increased connecting an external resistor from FSW pin and ground. If this pin is left floating the device works at its free-running frequency of 250 kHz. 7 GND Ground 8 VCC Unregulated DC input voltage Error amplifier output to be used for loop frequency compensation Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.6 V. To have higher regulated voltages an external resistor divider is required from Vout to FB pin. L5987 - L5987A 2 Maximum ratings Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Vcc Input voltage OUT Output DC voltage Value 20 -0.3 to VCC FSW, COMP, SYNCH Analog pin 3 -0.3 to 4 INH Inhibit pin -0.3 to VCC FB Feedback voltage -0.3 to 1.5 Power dissipation at VFQFPN TA < 60 °C HSOP PTOT Unit 1.5. V W 2 TJ Junction temperature range -40 to 150 °C Tstg Storage temperature range -55 to 150 °C Value Unit Thermal data Table 3. Thermal data Symbol RthJA Parameter Maximum thermal resistance junction-ambient (1) VFQFPN 60 HSOP 40 °C/W 1. Package mounted on demonstration board. 5/42 Electrical characteristics 4 L5987 - L5987A Electrical characteristics TJ = 25 °C, VCC = 12 V, unless otherwise specified. Table 4. Electrical characteristics Values Symbol Parameter Test condition Unit Min VCC Operating input voltage range (1) VCCON Turn on VCC threshold (1) VCCOFF Turn off VCC threshold (1) RDS(on) Mosfet on resistance ILIM 2.9 Max 18 2.9 V 2.4 140 170 140 220 3.5 4.0 4.4 225 250 275 mΩ (1) Maximum limiting current Typ A Oscillator FSW Switching frequency VFSW FSW pin voltage D FADJ (1) 265 1.262 Duty cycle Adjustable switching frequency kHz 220 0 RFSW = 33 kΩ V 100 1000 % kHz Dynamic characteristics VFB Feedback voltage 2.9 V < VCC < 18 V (1) 0.593 0.6 0.607 V 2.4 mA 30 μA DC characteristics IQ IQST-BY Quiescent current Duty Cycle = 0, VFB = 0.8 V Total stand-by quiescent current 20 Inhibit Device ON level 0.6 INH threshold voltage V Device OFF level INH current 1.9 INH = 0 7.5 10 8.2 9.1 μA Soft-start FSW pin floating TSS 6/42 Soft-start duration FSW = 1 MHz, RFSW = 33 kΩ 7.4 ms 2 L5987 - L5987A Electrical characteristics Table 4. Electrical characteristics (continued) Values Symbol Parameter Test condition Unit Min Typ Max Error amplifier VCH High level output voltage VFB < 0.6 V VCL Low level output voltage VFB > 0.6 V IFB Bias source current VFB = 0 V to 0.8 V 1 μA VFB = 0.5 V, VCOMP = 1 V 17 mA Sink COMP pin VFB = 0.7 V, VCOMP = 1 V 25 mA Open loop voltage gain (2) 100 dB IO SOURCE Source COMP pin IO SINK GV 3 V 0.1 Synchronization function High input voltage 2 3.3 V Low input voltage 1 Slave sink current VSYNCH = 2.9 V 0.7 Master output amplitude ISOURCE = 200 μA 3.0 Output pulse width SYNCH floating 110 0.9 mA V ns Input pulse width 70 Protection IFBDISC TSHDN FB disconnection source current 1 Thermal shutdown 150 Hysteresis 30 μA °C 1. Specification referred to TJ from -40 to +125 °C. Specification in the -40 to +125 °C temperature range are assured by design, characterization and statistical correlation. 2. Guaranteed by design. 7/42 Functional description 5 L5987 - L5987A Functional description The L5987 is based on a “voltage mode”, constant frequency control. The output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing an error signal that, compared to a fixed frequency sawtooth, controls the on and off time of the power switch. The main internal blocks are shown in the block diagram in Figure 2. They are: z A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the synchronization signal. Its switching frequency can be adjusted by an external resistor. The voltage and frequency feed forward are implemented. z The soft-start circuitry to limit inrush current during the start up phase. z The voltage mode error amplifier z The pulse width modulator and the relative logic circuitry necessary to drive the internal power switch. z The High-side driver for embedded P-channel power MOSFET switch. z The peak current limit sensing block, to handle over load and short circuit conditions. z A voltage regulator and internal reference. It supplies internal circuitry and provides a fixed internal reference. z A voltage monitor circuitry (UVLO) that checks the input and internal voltages. z A thermal shutdown block, to prevent thermal run away. Figure 2. 8/42 Block diagram L5987 - L5987A 5.1 Functional description Oscillator and synchronization Figure 3 shows the block diagram of the oscillator circuit. The internal oscillator provides a constant frequency clock. Its frequency depends on the resistor externally connect to FSW pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be increased as shown in Figure 5 by external resistor connected to ground. To improve the line transient performance, keeping the PWM gain constant versus the input voltage, the voltage feed forward is implemented by changing the slope of the sawtooth according to the input voltage change (see Figure 4.a). The slope of the sawtooth also changes if the oscillator frequency is increased by the external resistor. In this way a frequency feed forward is implemented (Figure 4.b) in order to keep the PWM gain constant versus the switching frequency (see Section 6.4 for PWM gain expression). On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of 180° with respect to the clock. This delay is useful when two devices are synchronized connecting the SYNCH pin together. When SYNCH pins are connected, the device with higher oscillator frequency works as Master, so the Slave device switches at the frequency of the master but with a delay of half a period. This minimizes the RMS current flowing through the input capacitor [see L5988D data sheet]. Figure 3. Oscillator circuit block diagram Clock FSW Clock Generator Synchronization SYNCH Ramp Generator Sawtooth The device can be synchronized to work at higher frequency feeding an external clock signal. The synchronization changes the sawtooth amplitude, changing the PWM gain (Figure 4.c). This changing has to be taken into account when the loop stability is studied. To minimize the change of the PWM gain, the free running frequency should be set (with a resistor on FSW pin) only slightly lower than the external clock frequency. This pre-adjusting of the frequency will change the sawtooth slope in order to get negligible the truncation of sawtooth, due to the external synchronization. 9/42 Functional description 10/42 L5987 - L5987A Figure 4. Sawtooth: voltage and frequency feed forward; external synchronization Figure 5. Oscillator frequency versus FSW pin resistor L5987 - L5987A 5.2 Functional description Soft-start The soft-start is essential to assure correct and safe start up of the step-down converter. It avoids inrush current surge and makes the output voltage increases monothonically. The soft-start is performed by a staircase ramp on the non-inverting input (VREF) of the error amplifier. So the output voltage slew rate is: Equation 1 SR OUT = SR VREF ⋅ ⎛ 1 + R1 --------⎞ ⎝ R2⎠ where SRVREF is the slew rate of the non-inverting input, while R1and R2 is the resistor divider to regulate the output voltage (see Figure 6). The soft-start stair case consists of 64 steps of 9.5 mV each one, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So the soft-start time and then the output voltage slew rate depend on the switching frequency. Figure 6. Soft-start scheme Soft-start time results: Equation 2 32 ⋅ 64 SS TIME = ----------------Fsw For example with a switching frequency of 250 kHz the SSTIME is 8 ms. 11/42 Functional description 5.3 L5987 - L5987A Error amplifier and compensation The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier so with high DC gain and low output impedance. The uncompensated error amplifier characteristics are the following: Table 5. Uncompensated error amplifier characteristics Parameter Value Low frequency gain 100 dB GBWP 4.5 MHz Slew rate 7 V/μs Output voltage swing 0 to 3.3 V Maximum source/sink current 25 mA/40 mA In continuos conduction mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. In case the zero introduced by the output capacitor helps to compensate the double pole of the LC filter a type II compensation network can be used. Otherwise, a type III compensation network has to be used (see Chapter 6.4 for details about the compensation network selection). Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe phase margin. 12/42 L5987 - L5987A 5.4 Functional description Over-current protection The L5987 implements the over-current protection sensing current flowing through the power MOSFET. Due to the noise created by the switching activity of the power MOSFET, the current sensing is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. The masking time is about 200 ns. When the over-current is detected, two different behaviors are possible depending on the operating condition. 1. Output voltage in regulation. When the over current is sensed, the power MOSFET is switched off and the internal reference (VREF), that biases the non-inverting input of the error amplifier, is set to zero and kept in this condition for a soft-start time (TSS, 2048 clock cycles). After this time, a new soft-start phase takes place and the internal reference begins ramping (see Figure 7.a). 2. Soft-start phase. If the over current limit is reached the power MOSFET is turned off implementing the pulse by pulse over current protection. During the soft-start phase, under over current condition, the device can skip pulses in order to keep the output current constant and equal to the current limit. If at the end of the “masking time” the current is higher than the over current threshold, the power MOSFET is turned off and it will skip one pulse. If, at the next switching on at the end of the “masking time” the current is still higher than the threshold, the device will skip two pulses. This mechanism is repeated and the device can skip up to seven pulses. While, if at the end of the “masking time” the current is lower than the over current threshold, the number of skipped cycles is decreased of one unit. At the end of soft-start phase the output voltage is in regulation and if the over current persists the behavior explained above takes place. (see Figure 7.b) So the over current protection can be summarized as an “hiccup” intervention when the output is in regulation and a constant current during the soft-start phase. If the output is shorted to ground when the output voltage is on regulation, the over current is triggered and the device starts cycling with a period of 2048 clock cycles between “hiccup” (power MOSFET off and no current to the load) and “constant current” with very short on-time and with reduced switching frequency (up to one eighth of normal switching frequency). See for short circuit behavior. 13/42 Functional description Figure 7. 5.5 L5987 - L5987A Over-current protection strategy Inhibit function The inhibit feature allows to put in stand-by mode the device.With INH pin higher than 1.9 V the device is disabled and the power consumption is reduced to less than 30 μA. With INH pin lower than 0.6 V, the device is enabled. If the INH pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible. 5.6 Hysteretic thermal shutdown The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C, the device restarts in normal operation. The sensing element is very close to the PDMOS area, so ensuring an accurate and fast temperature detection. 14/42 L5987 - L5987A 5.7 Functional description Maximum DC output current L5987A (HSOP8) The L5987A can manage DC output currents up to 3 A and the rated RMS current of its internal power switch is 3 A. So the L5987A can deliver 3 A with 100 % of duty cycle. 5.8 Maximum DC output current L5987 (VFQFPN) The L5987 can manage DC output currents up to 3 A. However the rated RMS current of its internal power switch is 2.5 A. Since the current flows through the integrated power element only during the on time, the RMS value is given by: Equation 3 I RMS = I O ⋅ D Where D is the duty cycle (VO/VIN). Considering IO = 3 A, the maximum duty cycle that can be managed is: Equation 4 2 I RMS D = -----------= 69% 2 IO In Figure 8 the maximum DC output current is reported as a function of the duty cycle. For duty cycles lower than 69 %, the RMS current does not limit the maximum DC output current of 3 A. For duty cycles higher than the 69 % the maximum DC output current is limited by the RMS current to: Equation 5 2.5 I O, MAX = -------D [A] if D ≥ 69% In order to have a more accurate calculation of the maximum DC output current, the complete expression for the duty cycle can be adopted, considering the voltage drop across the power MOSFET, the series resistance of the inductor and the forward voltage of the rectification diode. The duty cycle results: Equation 6 V OUT + V F + DCR ⋅ IO D = --------------------------------------------------------V IN + V F – R DSON ⋅ I O where IO is the desired DC output current. For example with VIN = 5 V, VOUT = 3.3 V, IO = 2.6 A, RDS(on) = 220 mΩ, VF = 0.35 V and DCR = 30 mΩ, the duty results D = 78 %, so according to Equation 5 the maximum DC output current is 2.83 A, which is higher than desired current. 15/42 Functional description L5987 - L5987A With VIN = 3.3 V, VOUT = 1.8 V, IO = 2.7 A, RDS(on) = 220 mΩ, VF = 0.35 V and DCR = 30 mΩ, the duty is D = 73 %, so the maximum DC output current results 2.926 A, higher than the desired current. Figure 8. 16/42 Maximum DC output current for VQFN package vs duty cycle. For duty cycles lower than 69 %, the RMS current does not limit the maximum DC output current of 3 A. For duty cycles higher than the 69 % the maximum DC output current is limited by the RMS current (see Equation 5) L5987 - L5987A Application information 6 Application information 6.1 Input capacitor selection The capacitor connected to the input has to be capable to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have a RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 7 2 2 ⋅ D- D -------------I RMS = I O ⋅ D – 2 + ------2 η η Where Io is the maximum DC output current, D is the duty cycle, η is the efficiency. Considering η = 1, this function has a maximum at D = 0.5 and it is equal to Io/2. In a specific application the range of possible duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as: Equation 8 V OUT + V F D MAX = -----------------------------------V INMIN – V SW and Equation 9 V OUT + V F D MIN = ------------------------------------V INMAX – V SW Where VF is the forward voltage on the freewheeling diode and VSW is voltage drop across the internal PDMOS. In Table 6. some multi layer ceramic capacitors suitable for this device are reported: Table 6. Input MLCC capacitors Manufacture Series Cap value (μF) Rated voltage (V) GRM31 10 25 GRM55 10 25 C3225 10 25 MURATA TDK 17/42 Application information 6.2 L5987 - L5987A Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value in order to have the expected current ripple has to be selected. The rule to fix the current ripple value is to have a ripple at 20 %-40 % of the output current. In the continuos current mode (CCM), the inductance value can be calculated by the following equation: Equation 10 V IN – V OUT V OUT + V F ΔI L = ------------------------------ ⋅ T ON = ---------------------------- ⋅ T OFF L L Where TON is the conduction time of the internal high side switch and TOFF is the conduction time of the external diode (in CCM, FSW = 1/(TON + TOFF)). The maximum current ripple, at fixed Vout, is obtained at maximum TOFF that is at minimum duty cycle (see previous section to calculate minimum duty). So fixing ΔIL = 20 % to 30 % of the maximum output current, the minimum inductance value can be calculated: Equation 11 V OUT + V F 1 – D MIN L MIN = ---------------------------- ⋅ ----------------------ΔI MAX F SW where FSW is the switching frequency, 1/(TON + TOFF). For example for VOUT = 3.3 V, VIN = 12 V, IO = 3 A and FSW = 250 kHz the minimum inductance value to have ΔIL = 30 % of IO is about 10 μH. The peak current through the inductor is given by: Equation 12 ΔI I L, PK = I O + -------L2 So if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. The higher is the inductor value, the higher is the average output current that can be delivered, without reaching the current limit. In the table below some inductor part numbers are listed. Table 7. Inductors Manufacturer Series Inductor value (μH) Saturation current (A) MSS1038 3.8 to 10 3.9 to 6.5 MSS1048 12 to 22 3.84 to 5.34 Coilcraft 18/42 L5987 - L5987A Application information Table 7. Inductors (continued) Manufacturer Series Inductor value (μH) Saturation current (A) PD Type L 8.2 to 15 3.75 to 6.25 PD Type M 2.2 to 4.7 4 to 6 CDRH6D226/HP 1.5 to 3.3 3.6 to 5.2 CDR10D48MN 6.6 to 12 4.1 to 5.7 Wurth SUMIDA 6.3 Output capacitor selection The current in the capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. Equation 13 ΔI MAX ΔV OUT = ESR ⋅ ΔI MAX + -----------------------------------8 ⋅ C OUT ⋅ f SW Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi layer ceramic capacitor (MLCC) with very low ESR value. The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. In Chapter 6.4, it will be illustrated how to consider its effect in the system stability. For example with VOUT = 3.3 V, VIN = 12 V, ΔIL = 0.9 A (resulting by the inductor value), in order to have a ΔVOUT = 0.01·VOUT, if the multi layer ceramic capacitor are adopted, 13 μF are needed and the ESR effect on the output voltage ripple can be neglected. In case of not negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value. So in case of 330 μF with ESR = 30 mΩ, the resistive component of the drop dominates and the voltage ripple is 27 mV. The output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. When the load transient slew rate exceeds the system bandwidth the output capacitor provides the current to the load. So if the high slew rate load transient is required by the application the output capacitor and system bandwidth have to be chosen in order to sustain the load transient. In the table below some capacitor series are listed. 19/42 Application information Table 8. L5987 - L5987A Output capacitors Manufacturer Series Cap value (μF) Rated voltage (V) ESR (mΩ) GRM32 22 to 100 6.3 to 25 <5 GRM31 10 to 47 6.3 to 25 <5 ECJ 10 to 22 6.3 <5 EEFCD 10 to 68 6.3 15 to 55 SANYO TPA/B/C 100 to 470 4 to 16 40 to 80 TDK C3225 22 to 100 6.3 <5 MURATA PANASONIC 6.4 Compensation network The compensation network has to assure stability and good dynamic performance. The loop of the L5987 is based on the voltage mode control. The error amplifier is a voltage operational amplifier with high bandwidth. So selecting the compensation network the E/A will be considered as ideal, that is, its bandwidth is much larger than the system one. The transfer functions of PWM modulator and the output LC filter are studied (see Figure 10.). The transfer function of the PWM modulator, from the error amplifier output (COMP pin) to the OUT pin, results: Equation 14 V IN G PW0 = -------Vs where VS is the sawtooth amplitude. As seen in Chapter 5.1, the voltage feed forward generates a sawtooth amplitude directly proportional to the input voltage, that is: Equation 15 V S = K ⋅ V IN In this way the PWM modulator gain results constant and equals to: Equation 16 V IN 1- = 9 - = --G PW0 = -------Vs K The synchronization of the device with an external clock provided trough SYNCH pin can modifies the PWM modulator gain (see Chapter 5.1 to understand how this gain changes and how to keep it constant in spite of the external synchronization). 20/42 L5987 - L5987A Application information Figure 9. The error amplifier, the PWM modulation and the LC output filter VCC VS VREF FB PWM E/A OUT COMP L ESR GPW0 GLC COUT The transfer function on the LC filter is given by: Equation 17 s 1 + ------------------------2π ⋅ f zESR G LC ( s ) = ------------------------------------------------------------------------2 s s 1 + ---------------------------+ ⎛ -------------------⎞ ⎝ ⎠ 2π ⋅ f LC 2π ⋅ Q ⋅ f LC where: Equation 18 1 f LC = ------------------------------------------------------------------------, ESR2π ⋅ L ⋅ C OUT ⋅ 1 + -------------R OUT 1 f zESR = -------------------------------------------2π ⋅ ESR ⋅ C OUT Equation 19 R OUT ⋅ L ⋅ C OUT ⋅ ( R OUT + ESR ) Q = ------------------------------------------------------------------------------------------ , L + C OUT ⋅ R OUT ⋅ E SR V OUT R OUT = -------------I OUT As seen in Chapter 5.3 two different kind of network can compensate the loop. In the two following paragraph the guidelines to select the Type II and Type III compensation network are illustrated. 21/42 Application information 6.4.1 L5987 - L5987A Type III compensation network The methodology to stabilize the loop consists of placing two zeros to compensate the effect of the LC double pole, so increasing phase margin; then to place one pole in the origin to minimize the dc error on regulated output voltage; finally to place other poles far away the zero dB frequency. If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2π∗ESR∗COUT<1/BW), the type III compensation network is needed. Multi layer ceramic capacitors (MLCC) have very low ESR (<1 mΩ), with very high frequency zero, so type III network is adopted to compensate the loop. In Figure 10 the type III compensation network is shown. This network introduces two zeros (fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are: Equation 20 1 f Z1 = ------------------------------------------------, 2π ⋅ C 3 ⋅ ( R 1 + R 3 ) 1 f Z2 = -----------------------------2π ⋅ R 4 ⋅ C 4 Equation 21 f P0 = 0, 1 -, f P1 = ----------------------------2π ⋅ R 3 ⋅ C 3 1 f P2 = ------------------------------------------C4 ⋅ C5 2π ⋅ R 4 ⋅ -------------------C4 + C5 Figure 10. Type III compensation network In Figure 11 the bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f)) and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)) are drawn. 22/42 L5987 - L5987A Application information Figure 11. Open loop gain: module bode diagram The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow: 1. Choose a value for R1, usually between 1 k and 5 k. 2. Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means: Equation 22 BW 1 R 4 = ---------- ⋅ ---- ⋅ R 1 f LC K where K is the feed forward constant and 1/K is equals to 9. 3. Calculate C4 by placing the zero at 50 % of the output filter double pole frequency (fLC): Equation 23 1 C 4 = --------------------------π ⋅ R 4 ⋅ f LC 4. Calculate C5 by placing the second pole at four times the system bandwidth (BW): Equation 24 C4 C 5 = ------------------------------------------------------------2π ⋅ R 4 ⋅ C 4 ⋅ 4 ⋅ BW – 1 5. Set also the first pole at four times the system bandwidth and also the second zero at the output filter double pole: 23/42 Application information L5987 - L5987A Equation 25 R1 -, R 3 = -------------------------4 ⋅ BW – 1 ----------------f LC 1 C 3 = ---------------------------------------2π ⋅ R 3 ⋅ 4 ⋅ BW The suggested maximum system bandwidth is equals to the switching frequency divided by 3.5 (FSW/3.5), anyway lower than 100 kHz if the FSW is set higher than 500 kHz. For example with VOUT = 3.3 V, VIN = 12 V, IO = 3 A, L = 10 μH, COUT = 22 μF, ESR < 1 mΩ, the type III compensation network is: R 1 = 4.99kΩ, R 2 = 1.1kΩ, R 3 = 220Ω, R 4 = 3.3kΩ, C 3 = 3.3nF, C 4 = 10nF, C 5 = 180pF In Figure 12 is shown the module and phase of the open loop gain. The bandwidth is about 71 kHz and the phase margin is 46°. 24/42 L5987 - L5987A Application information Figure 12. Open loop gain bode diagram with ceramic output capacitor 25/42 Application information 6.4.2 L5987 - L5987A Type II compensation network If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2π∗ESR∗COUT>1/BW), this zero helps stabilize the loop. Electrolytic capacitors show not negligible ESR (>30 mΩ), so with this kind of output capacitor the type II network combined with the zero of the ESR allows stabilizing the loop. In Figure 13 the type II network is shown. Figure 13. Type II compensation network The singularities of the network are: 1 -, f Z1 = ----------------------------2π ⋅ R 4 ⋅ C 4 f P0 = 0, 1 f P1 = ------------------------------------------C4 ⋅ C5 2π ⋅ R 4 ⋅ -------------------C4 + C5 In Figure 14 the bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f)) and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)) are drawn. 26/42 L5987 - L5987A Application information Figure 14. Open loop gain: module bode diagram The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow: 1. Choose a value for R1, usually between 1k and 5k, in order to have values of C4 and C5 not comparable with parasitic capacitance of the board. 2. Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means: Equation 26 f ESR 2 BW V S R 4 = ⎛ ------------⎞ ⋅ ------------ ⋅ --------- ⋅ R 1 ⎝ f LC ⎠ f ESR V IN Where fESR is the ESR zero: Equation 27 1 f ESR = -------------------------------------------2π ⋅ ESR ⋅ C OUT and Vs is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant. 3. Calculate C4 by placing the zero one decade below the output filter double pole: Equation 28 10 C 4 = -----------------------------2π ⋅ R 4 ⋅ f LC 4. Then calculate C3 in order to place the second pole at four times the system bandwidth (BW): 27/42 Application information L5987 - L5987A Equation 29 C4 C 5 = ------------------------------------------------------------2π ⋅ R 4 ⋅ C 4 ⋅ 4 ⋅ BW – 1 For example with VOUT = 3.3 V, VIN = 12 V, IO = 3 A, L = 10 μH, COUT = 330 μF, ESR = 35 mΩ, the type II compensation network is: R 1 = 1.5kΩ, R 2 = 330Ω, R 4 = 10kΩ, C 4 = 47nF, C 5 = 82pF In Figure 15 is shown the module and phase of the open loop gain. The bandwidth is about 32 kHz and the phase margin is 45°. 28/42 L5987 - L5987A Application information Figure 15. Open loop gain bode diagram with electrolytic/tantalum output capacitor 29/42 Application information 6.5 L5987 - L5987A Thermal considerations The thermal design is important to prevent the thermal shutdown of device if junction temperature goes above 150 °C. The three different sources of losses within the device are: a) conduction losses due to the not negligible RDS(on) of the power switch; these are equal to: Equation 30 2 P ON = R DSON ⋅ ( I OUT ) ⋅ D Where D is the duty cycle of the application and the maximum RDS(on) over temperature is 220 mΩ. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN, but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increases compared with the ideal case. b) switching losses due to power MOSFET turn ON and OFF; these can be calculated as: Equation 31 ( T RISE + T FALL ) P SW = V IN ⋅ I OUT ⋅ ------------------------------------------- ⋅ Fsw = V IN ⋅ I OUT ⋅ T SW ⋅ F SW 2 Where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS) and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 16. TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 50ns. c) Quiescent current losses, calculated as: Equation 32 P Q = V IN ⋅ I Q where IQ is the quiescent current (IQ = 2.4 mA). The junction temperature TJ can be calculated as: Equation 33 T J = T A + Rth JA ⋅ P TOT Where TA is the ambient temperature and PTOT is the sum of the power losses just seen. RthJA is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount 30/42 L5987 - L5987A Application information of heat. The RthJA measured on the demonstration board described in the following paragraph is about 60 °C/W for the VFQFPN package and about 40 °C/W for the HSOP package. Figure 16. Switching losses 6.6 Layout considerations The PC board layout of switching DC/DC regulator is very important to minimize the noise injected in high impedance nodes and interferences generated by the high switching current loops. In a step down converter the input loop (including the input capacitor, the power MOSFET and the free wheeling diode) is the most critical one. This is due to the fact that the high value pulsed current are flowing through it. In order to minimize the EMI, this loop has to be as short as possible. The feedback pin (FB) connection to external resistor divider is a high impedance node, so the interferences can be minimized placing the routing of feedback node as far as possible from the high current paths. To reduce the pick up noise the resistor divider has to be placed very close to the device. To filter the high frequency noise, a small capacitor (220 nF) can be added as close as possible to the input voltage pin of the device. Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane enhances the thermal performance of the converter allowing high power conversion. In Figure 17 a layout example is shown. 31/42 Application information Figure 17. Layout example 32/42 L5987 - L5987A L5987 - L5987A 6.7 Application information Application circuit In Figure 18 the demonstration board application circuit is shown. Figure 18. Demonstration board application circuit Vin=2.9V - 18V C1 22u 25V VCC C6 220n INH 25V GND 8 1 L5987/A 3 7 6 FSW 4 2 SYNCH 5 FB Vout=1.8V C2 22u 25V D1 STPS2L25 COMP R5 150k R4 2K R1 4.99K C4 10hF C5 330pF Table 9. L1 5.2uH MSS1038 OUT R2 2.49k R3 330 C3 2.2nF Component list Reference Part number Description Manufacturer C1 GRM32ER61E226KE15 22μF, 25V Murata C2 GRM32ER61E226KE15 22μF, 25V Murata C3 2.2nF, 50V C4 10nF, 50V C5 330pF, 50V C6 220nF, 25V R1 4.99 kΩ, 1%, 0.1W 0603 R2 2.49kΩ, 1%, 0.1W 0603 R3 330 Ω, 1%, 0.1W 0603 R4 2 kΩ, 1%, 0.1W 0603 R5 100k. D1 STPS2L25V 2A DC, 25V STMicroelectronics L1 MSS1038-522NL 5.2μH, 30%, 5.28A, DCRMAX=22mΩ Coilcraft 33/42 Application information Figure 19. PCB layout: L5987 and L5987A (component side) Figure 20. PCB layout: L5987 and L5987A (bottom side) Figure 21. PCB layout: L5987 and L5987A (front side) 34/42 L5987 - L5987A L5987 - L5987A Application information Figure 22. Junction temperature vs output current Figure 23. Junction temperature vs output current Figure 24. Junction temperature vs output current Figure 25. Efficiency vs output current 92 FSW=250kHz 90 VO=5V E ffic ie n c y [% ] 88 86 VO=3.3V 84 82 VO=2.5V 80 78 VIN=12V 76 0.3 0.8 1.3 1.8 2.3 2.8 Io [A] Figure 26. Efficiency vs output current Figure 27. Efficiency vs output current 95 FSW=250kHz 95 90 VO=3.3V 85 VO=2.5V 80 75 VO=1.8V E ffic ie n c y [% ] E ffic ie n c y [% ] 90 VO=2.5V 85 VO=1.8V 80 75 VO=1.2V VIN=3.3V 70 VIN=5V 70 65 0.3 0.8 1.3 1.8 Io [A] 2.3 2.8 0.3 0.8 1.3 1.8 2.3 2.8 Io [A] 35/42 L5987 - L5987A Application information Figure 28. Load regulation Figure 29. Line regulation 1.2 1 VCC=12V IO=1A VCC=5V 0.8 0.8 Δ V FB/V FB [%] Δ VFB/VFB [%] 1 0.6 0.4 IO=2A IO=3A 0.6 0.4 0.2 0.2 0 0 0 0.5 1 1.5 2 2.5 3 2 4 6 8 10 12 14 16 18 VCC [V] IO [A] Figure 30. Load transient: from 0.4 A to 3 A Figure 31. Soft-start IL 1A/div VOUT 100mV/div AC coupled VOUT 0.5V/div 1V/div COUT=47uF L=3.8uH FSW=520k IL 1A/div Time base 1ms/div Time base 100us/div Figure 32. Short-circuit behavior OUT 10V/div 1V/div VOUT 0.5V/div SHORTED OUTPUT IL 1A/div Time base 5ms/div 36/42 L5987 - L5987A 7 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of the second level interconnect is marked on the package and on the inner box label, in compliance with the JEDEC Standard JESD97. The maximum ratings related to soldering condition are also marked on the inner box label. ECOPACK® is an ST trademark. ECOPACK specifications are available at: www.st.com 37/42 Package mechanical data Table 10. L5987 - L5987A VFQFPN8 (3x3x1.08 mm) mechanical data mm inch Dim. Min Typ Max Min Typ Max 0.80 0.90 1.00 0.0315 0.0354 0.0394 A1 0.02 0.05 0.0008 0.0020 A2 0.70 0.0276 A3 0.20 0.0079 A b 0.18 0.23 0.30 0.0071 0.0091 0.0118 D 2.95 3.00 3.05 0.1161 0.1181 0.1200 D2 2.23 2.38 2.48 0.0878 0.0937 0.0976 E 2.95 3.00 3.05 0.1161 0.1181 0.1200 E2 1.65 1.70 1.75 0.0649 0.0669 0.0689 e L 0.50 0.35 0.40 ddd Figure 33. Package dimensions 38/42 0.0197 0.45 0.08 0.0137 0.0157 0.0177 0.0031 L5987 - L5987A Package mechanical data Table 11. HSOP8 mechanical data mm inch Dim Min Typ A Max Min Typ 1.70 Max 0.0669 A1 0.00 A2 1.25 b 0.31 0.51 0.0122 0.0201 c 0.17 0.25 0.0067 0.0098 D 4.80 4.90 5.00 0.1890 E 5.80 6.00 6.20 0.2283 0.2441 E1 3.80 3.90 4.00 0.1496 0.1575 e 0.15 0.00 0.0059 0.0492 0.1929 0.1969 1.27 h 0.25 0.50 0.0098 0.0197 L 0.40 1.27 0.0157 0.0500 k 0 8 0.3150 0.10 0.0039 ccc Figure 34. Package dimensions 39/42 Order codes 8 L5987 - L5987A Order codes Table 12. Order codes Order codes Package L5987 VFQFPN8 L5987A HSOP8 L5987TR VFQFPN8 L5987ATR HSOP8 Packaging Tube Tape and reel 40/42 L5987 - L5987A 9 Revision history Revision history Table 13. Document revision history Date Revision 29-Aug-2008 1 Changes Initial release 41/42 L5987 - L5987A Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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