STMICROELECTRONICS LNBH221

LNBH221
Dual LNB supply and control IC with
Step-Up converter and I²C interface
Feature summary
■
All the features are the same for both section
■
Complete and independent interface between
LNBS and relevant I2CTM BUS
■
BUILT-IN DC/DC controller for single 12V
supply operation and high efficiency (Typ. 93%
@ 500mA)
■
LNB output current guaranteed up to 500mA
■
Both compliant with eutelsat and directv output
voltage specification accurate BUILT-IN
22KHz tone oscillator suits widely accepted
standards
■
Fast oscillator start-up facilitates DiSEqCTM
encoding
■
BUILT-IN 22KHz tone detector supports bidirectional DiSEqCTM 2.0
■
Semi-lowdrop post regulator and high
efficiency step-up pwm for low power loss: Typ.
0.56W @ 125mA
■
Two output pins suitable to bypass the output rl filter and avoid any tone distorsion (R-L filter
as per DiSEqC 2.0 SPECs, see application
circuit on pag. 7, 8)
■
Overload and over-temperature internal
protections
■
Overload and over-temperature I2C diagnostic
BITs
■
LNB short circuit soa protection with I2C
diagnostic bit
■
+/- 4KV ESD tolerant on input/output power
pins
POWER SO-36
assembled in POWER SO-36, specifically
designed to provide the power 13/18V, and the
22KHz tone signalling for two independent LNB
down converters or to a multiswitch box that could
be independently powered and set. In this
application field, it offers a complete solution with
extremely low component count, low power
dissipation together with simple design and I2CTM
standard interfacing.
Description
Intended for analog and digital DUAL Satellite
STB receivers/SatTV, sets/PC cards, the
LNBH221 is a voltage regulator and interface IC,
February 2006
Rev. 5
1/27
www.st.com
27
LNBH221
Contents
1
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Typical application circuits for each section : A and B . . . . . . . . . . . . . 7
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6
5.1
I2C Bus Interface (one for each section) . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.4
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.5
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.6
Transmission without acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . .11
LNBH221 software description (same for both section) . . . . . . . . . . . 13
6.1
Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.2
System register (SR, 1 Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.3
Transmitted data (I2C BUS write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4
Received data (I2C bus READ MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5
Power-On I2C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.6
Address Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7
DiSEqCTM Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8
Thermal design notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9
Typical performance characteristics (of each section) . . . . . . . . . . . . 19
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
LD39150
Diagram
1
Diagram
Figure 1.
Block diagram
Gate
LNBH221- section A
Sense
Step-up
Controller
VoTX
Vup
Vcc
Byp
SDA
SCL
VoRX
Preregul.+
U.V.lockout
+P.ON res.
Linear Post-reg
+Modulator
+Protections
V Select
I²C
Diagn.
Enable
ADDR
TEN
DSQIN
22KHz
Oscill.
Tone
Detector
DSQOUT
Step-up
Controller
VoTX
Vup
Byp
SDA
SCL
VoRX
Preregul.+
U.V.lockout
+P.ON res.
Linear Post-reg
+Modulator
+Protections
V Select
I²C
EXTM
Diagn.
Enable
ADDR
TEN
DSQIN
DETIN
LNBH221- section B
Gate
Sense
Vcc
EXTM
22KHz
Oscill.
Tone
Detector
DETIN
DSQOUT
3/27
Maximum ratings
LNBH221
2
Maximum ratings
Table 1.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC Input Voltage
-0.3 to 16
V
VUP
DC Input Voltage
-0.3 to 25
V
DC Output Pin Voltage
-0.3 to 25
V
Internally Limited
mA
VOTX/RX
IO
Output Current
VI
Logic Input Voltage (SDA, SCL, DSQIN)
-0.3 to 7
V
Detector Input Signal Amplitude
-0.3 to 2
VPP
VOH
Logic High Output Voltage (DSQOUT)
-0.3 to 7
V
IGATE
Gate Current
±400
mA
Current Sense Voltage
-0.3 to 1
V
Address Pin Voltage
-0.3 to 7
V
VDETIN
VSENSE
VADDRESS
Tstg
Storage Temperature Range
-40 to 150
°C
TJ
Operating Junction Temperature Range
-40 to 125
°C
Note:
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied.
Table 2.
Thermal Data
Symbol
RthJC
4/27
Parameter
Thermal Resistance Junction-Case
Value
Unit
2
°C/W
LD39150
Pin configuration
3
Pin configuration
Figure 2.
Pin configurations (top view)
Table 3.
Pin description
Symbol
Name
Function
PIN Number
Sect:
A
B
Supply Input
8V to 15V supply. A 220µF bypass capacitor to GND with a
470nF (ceramic) in parallel is recommended.
8
26
GATE
External Switch Gate
External MOS switch Gate connection of the step-up converter.
7
25
SENSE
Current Sense (Input)
Current Sense comparator input. Connected to current sensing
resistor.
6
24
Step-up Voltage
Input of the linear post-regulator. The voltage on this pin is
monitored by the internal step-up controller to keep a minimum
dropout across the linear pass transistor.
9
27
Output Port during
22KHz Tone RX
RX Output to the LNB in DiSEqC 2.0 application. See truth table
for voltage selections and description on page 4.
28
10
SDA
Serial Data
Bidirectional data from/to I2C bus.
2
20
SCL
Serial Clock
Clock from I2C bus.
3
21
DSQIN
DiSEqC Input
When the TEN bit of the System Register is LOW, this pin will
accept the DiSEqC code from the main µcontroller. Each section
of the LNBH221 will use this code to modulate the internally
generated 22kHz carrier. Set to GND this pin if not used.
4
22
DETIN
Detector In
22kHz Tone Detector Input. Must be AC coupled to the DiSEqC
bus.
35
17
VCC
VUP
VORX
5/27
Pin configuration
Table 3.
LNBH221
Pin description
Symbol
Name
Function
PIN Number
Sect:
A
B
Open drain output of the Tone Detector to the main µcontroller for
DiSEqC data decoding. It is LOW when tone is detected on the
DETIN.
5
23
External Modulation
External Modulation Input. Needs DC decoupling to the AC
source. If not used, can be left open.
31
13
GND
Ground
1, 14, 1, 14,
18,
18,
Circuit Ground. It is internally connected to the die frame for heat
19,
19,
dissipation.
32,
32,
36
36
BYP
Bypass Capacitor pin Needed for internal pre regulator filtering.
34
16
VOTX
Output Port during
22KHz Tone TX
Output of the linear post regulator/modulator to the LNB. See
truth table for voltage selections.
30
12
GND
Ground
To be connected to ground.
29
11
33
15
DSQOUT DiSEqC Output
EXTM
ADDR
6/27
Address Setting
2C
Four I bus addresses available by setting the Address Pin
level voltage.
LD39150
Typical application circuits for each section: A and B
4
Typical application circuits for each section: A and B
Figure 3.
Application Circuit For Diseqc 1.x And Output Current Up To 500mA
D1 1N4001
Axial Ferrite Bead Filter
F1 suggested part number:
IC1
MURATA BL01RN1-A62
Panasonic EXCELS A35
F1
Vup
C9
220µF
C2
220µF
IC2
STS4DNFS30L
VoRX
C3
470nF
Ceramic
Set TTX=1
to LNB
Gate
VoTX
LNBH221
Sense
L1=22µH
Rsc
0.1 Ω
C5
10nF
(**) DETIN
Section A and B
C4
470nF
Ceramic
Byp
C5
470nF
Vcc
Vin
12V
C1
220µF
Tone Enable
D2
BAT43
SDA
EXTM
SCL
Address
DSQIN
DSQOUT
GND
0<VADDR<VBYP
7/27
Typical application circuits for each section: A and B
Figure 4.
LNBH221
Application Circuit For Bi-directional Diseqc 2.0 And Output Current Up To 500mA
F1 suggested part number:
MURATA BL01RN1-A62
Panasonic EXCELS A35
D2 1N4001
Axial Ferrite Bead Filter
IC1
F1
Vup
C9
220µF
IC2
C2
220µF
C3(***)
470nF
Ceramic
VoTX
D4(***)
BAT43
C8(***)
100nF
STS4DNFS30L
270µH
to LNB
Gate
VoRX
LNBH221
Sense
L1=22µH
Rsc
0.1 Ω
C7(***)
100nF
D3(***)
BAT43
15 ohm
(*) see note
(**) DETIN
C6
10nF
Section A and B
Byp
C5
470nF
Vcc
Vin
12V
C1
220µF
C4(***)
470nF
Ceramic
SDA
EXTM
SCL
ADDRESS
DSQIN (**)
GND
0<VADDR<VBYP
DSQOUT
22KHz Tone Enable
1. C8, D3 and D4 are needed to protect the output pins from any negative voltage spikes during high speed
voltage transitions.
2. (*): R-L filter to be used according to EUTELSAT recommendation to implement the DiSEqCTM 2.0, (see
DiSEqCTM implementation on page 8). If bidirectional DiSEqCTM 2.0 is not implemented it can be removed
both with C8 and D4.
3. (**) Do not leave these pins floating if not used.
4. (***) To be soldered as close as possible to relative pins
8/27
LD39150
5
Application information
Application information
Basically, the LNBH221 includes two circuits that are completely independent. Each circuit
can be separately controlled and must have its independent external components. All the
below specification must be considered equal for each section.
This IC has a built in DC/DC step-up controller that, from a single supply source ranging
from 8 to 15V, generates the voltages (VUP) that let the linear post-regulator to work at a
minimum dissipated power of 1W typ. @ 500mA load (the linear regulator drop voltage is
internally kept at: VUP-VOUT=2V typ.). An UnderVoltage Lockout circuit will disable the
whole circuit when the supplied VCC drops below a fixed threshold (6.7V typically). The
internal 22KHz tone generator is factory trimmed in accordance to the standards, and can
be controlled either by the I2CTM interface or by a dedicated pin (DSQIN) that allows
immediate DiSEqCTM data encoding (*). When the TEN (Tone ENable) I2C bit it is set to
HIGH, a continuous 22KHz tone is generated on the output regardless of the DSQIN pin
logic status.
The TEN bit must be set LOW when the DSQIN pin is used for DiSEqCTM encoding. The
fully bi-directional DiSEqCTM 2.0 interfacing is completed by the built-in 22KHz tone
detector. Its input pin (DETIN) must be AC coupled to the DiSEqCTM bus, and the extracted
PWK data are available on the DSQOUT pin (*). To comply to the bi-directional DiSEqCTM
2.0 bus hardware requirements an output R-L filter is needed. The LNBH221 is provided
with two output pins: the VOTX to be used during the tone transmission and the VORX to be
used when the tone is received. This allows the 22KHz Tone to pass without any losses due
to the R-L filter impedance (see DiSeqC 2.0 application circuit on page 4). In DiSeqC 2.0
applications during the 22KHz transmission activated by DSQIN pin (or TEN I2C bit), the
VOTX pin must be preventively set ON by the TTX I2C bit and, both the 13/18V power
supply and the 22KHz tone, are provided by mean of VOTX output. As soon as the tone
transmission is expired, the VOTX must be set to OFF by setting the TTX I2C bit to zero and
the 13/18V power supply is provided to the LNB by the VORX pin through the R-L filter.
When the LNBH221 is used in DiSeqC 1.x applications the R-L filter is not required (see
DiSeqC 1.x application circuit on pag. 4), the TTX I2C bit must be kept always to HIGH so
that, the VOTX output pin can provide both the 13/18V power supply and the 22KHz tone,
enabled by DSQIN pin or by TEN I2C bit. All the functions of this IC are controlled via I2CTM
bus by writing 6 bits on the System Register (SR, 8 bits). The same register can be read
back, and two bits will report the diagnostic status. When the IC is put in Stand-by (EN bit
LOW), the power blocks are disabled.
When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be
13 or 18V by mean of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC
LNBs. Additionally, the LNBH221 is provided with the LLC I2C bit that increase the selected
voltage value (+1V when VSEL=0 and +1.5V when VSEL=1) to compensate for the excess
voltage drop along the coaxial cable (LLC bit HIGH). By mean of the LLC bit, the LNBH221
is also compliant to the American LNB power supply standards that require the higher
output voltage level to 19.5V (typ.) (instead of 18V), by simply setting the LLC=1 when
VSEL=1. In order to improve design flexibility and to allow implementation of newcoming
LNB remote control standards, an analogic modulation input pin is available (EXTM).
An appropriate DC blocking capacitor must be used to couple the modulating signal source
to the EXTM pin. Also in this case, the VOTX output must be set ON during the tone
transmission by setting the TTX bit high. When external modulation is not used, the relevant
pin can be left open. The current limitation block is SOA type: if the output port is shorted to
ground, the SOA current limitation block limits the short circuit current (ISC) at typically
300mA or 200mA respectively for VOUT 13V or 18V, to reduce the power dissipation.
9/27
Application information
LNBH221
Moreover, it is possible to set the Short Circuit Current protection either statically (simple
current clamp) or dynamically by the PCL bit of the I2C SR; when the PCL (Pulsed Current
Limiting) bit is set to LOW, the overcurrent protection circuit works dynamically, as soon as
an overload is detected, the output is shut-down for a time TOFF, typically 900ms.
Simultaneously the OLF bit of the System Register is set to HIGH. After this time has
elapsed, the output is resumed for a time TON=1/10TOFF (typ.). At the end of TON, if the
overload is still detected, the protection circuit will cycle again through TOFF and TON. At the
end of a full TON in which no overload is detected, normal operation is resumed and the OLF
bit is reset to LOW. Typical TON+TOFF time is 990ms and it is determined by an internal
timer. This dynamic operation can greatly reduce the power dissipation in short circuit
condition, still ensuring excellent power-on start up in most conditions. However, there could
be some cases in which an highly capacitive load on the output may cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL=HIGH) and then switching to the dynamic mode (PCL=LOW) after a
chosen amount of time. When in static mode, the OLF bit goes HIGH when the current
clamp limit is reached and returns LOW when the overload condition is cleared. This IC is
also protected against overheating: when the junction temperature exceeds 150°C (typ.),
the step-up converter and the linear regulator are shut off, and the OTF SR bit is set to
HIGH. Normal operation is resumed and the OTF bit is reset to LOW when the junction is
cooled down to 140°C (typ.).
Note:
(*): External components are needed to comply to bi-directional DiSEqCTM bus hardware
requirements. Full compliance of the whole application to DiSEqCTM specifications is not
implied by the use of this IC.
Note:
NOTICE: DiSEqC is a trademark of EUTELSAT. I2C is a trademark of Philips
Semiconductors.
5.1
I2C Bus Interface (one for each section)
Data transmission from main µP to the LNBH221 and viceversa takes place through the 2
wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to
positive supply voltage must be externally connected).
5.2
Data validity
As shown in Figure 5., the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
5.3
Start and stop conditions
As shown in Figure 6. a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH.
The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP
conditions must be sent before each START condition.
10/27
LD39150
5.4
Application information
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
5.5
Acknowledge
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 7.). The peripheral (LNBH221) that acknowledges has to pull-down
(LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW
during this clock pulse. The peripheral which has been addressed has to generate an
acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH
level during the ninth clock pulse time. In this case the master transmitter can generate the
STOP information in order to abort the transfer. The LNBH221 won't generate the
acknowledge if the VCC supply is below the Undervoltage Lockout threshold (6.7V typ.).
5.6
Transmission without acknowledgement
Avoiding to detect the acknowledge of the LNBH221, the µP can use a simpler
transmission: simply it waits one clock without checking the slave acknowledging, and
sends the new data.
This approach of course is less protected from misworking and decreases the noise
immunity..
Figure 5.
Data Validity On The I2C Bus
11/27
Application information
.
Figure 6.
Timing Diagram On I2C Bus
Figure 7.
Acknowledge On I2C Bus
12/27
LNBH221
LD39150
LNBH221 software description (same for both section)
6
LNBH221 software description (same for both
section)
6.1
Interface Protocol
The interface protocol comprises:
- A start condition (S)
- A chip address byte = hex 10 / 11 (the LSB bit determines read(=1)/write(=0) transmission)
- A sequence of data (1 byte + acknowledge)
- A stop condition (P)
CHIP ADDRESS
MSB
0
0
S
0
1
0
0
DATA
0
LSB
R/W ACK
MSB
LSB
ACK
P
ACK= Acknowledge
S= Start
P= Stop
R/W= Read/Write
6.2
MSB
R, W
PCL
System register (SR, 1 Byte)
R, W
TTX
R, W
TEN
R, W
LLC
R, W
VSEL
R, W
EN
R
OTF
LSB
R
OLF
R,W= read and write bit
R= Read-only bit
All bits reset to 0 at Power-On
13/27
LNBH221 software description (same for both section)
LNBH221
Transmitted data (I2C BUS write mode)
6.3
When the R/W bit in the chip address is set to 0, the main µP can write on the System
Register (SR) of the LNBH221 via I2C bus. Only 6 bits out of the 8 available can be written
by the µP, since the remaining 2 are left to the diagnostic flags, and are read-only.
PCL
TTX
TEN
LLC VSEL
EN
OTF
OLF
Function
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
1
X
X
X
1
1
0
X
X
X
X
X
X
VOUT=13.25V, VUP=15.25V
VOUT=18V, VUP=20V
VOUT=14.25V, VUP=16.25V
VOUT=19.5V, VUP=21.5V
22KHz tone is controlled by DSQIN pin
22KHz tone is ON, DSQIN pin disabled
VORX output is ON, output voltage controlled by VSEL
and LLC
VOTX output is ON, 22KHz controlled by DSQIN or TEN,
output voltage level controlled by VSEL and LLC
Pulsed (dynamic) current limiting is selected
Static current limiting is selected
Power blocks disabled
0
0
1
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X= don't care.
Values are typical unless otherwise specified.
Received data (I2C bus READ MODE)
6.4
The LNBH221 can provide to the Master a copy of the SYSTEM REGISTER information via
I2C bus in read mode. The read mode is Master activated by sending the chip address with
R/W bit set to 1.
At the following master generated clocks bits, the LNBH221 issues a byte on the SDA data
bus line (MSB transmitted first).
At the ninth clock bit the MCU master can:
- acknowledge the reception, starting in this way the transmission of another byte from the
LNBH221;
- no acknowledge, stopping the read mode communication.
While the whole register is read back by the µP, only the two read-only bits OLF and OTF
convey diagnostic informations about the LNBH221.
PCL
ISEL
TEN
LLC VSEL
EN
These bits are read exactly the same as
they were left after last write operation
OTF
OLF
0
1
0
1
Function
TJ<140°C, normal operation
TJ>150°C, power block disabled
IOUT<IOMAX, normal operation
IOUT>IOMAX, overload protection triggered
Values are typical unless otherwise specified.
14/27
LD39150
6.5
LNBH221 software description (same for both section)
Power-On I2C interface reset
The I2C interface built in the LNBH221 is automatically reset at power-on. As long as the
VCC stays below the UnderVoltage Lockout threshold (6.7V typ.), the interface will not
respond to any I2C command and the System Register (SR) is initialized to all zeroes, thus
keeping the power blocks disabled. Once the VCC rises above 7.3V typ, the I2C interface
becomes operative and the SR can be configured by the main µP. This is due to 500mV of
hysteresis provided in the UVL threshold to avoid false retriggering of the Power-On reset
circuit.
6.6
Address Pin
Connecting this pin to GND the Chip I2C interface address is 0001000, but, it is possible to
choice among 4 different addresses simply setting this pin at 4 fixed voltage levels (see
Table 7. on page 17).
6.7
DiSEqCTM Implementation
The LNBH221 helps the system designer to implement the bi-directional DiSEqC 2.0
protocol by allowing an easy PWK modulation/demodulation of the 22KHz carrier. The PWK
data are exchanged between the LNBH221 and the main µP using logic levels that are
compatible with both 3.3 and 5V microcontrollers. This data exchange is made through two
dedicated pins, DSQIN and DSQOUT, in order to maintain the timing relationships between
the PWK data and the PWK modulation as accurate as possible. These two pins should be
directly connected to two I/O pins of the µP, thus leaving to the resident firmware the task of
encoding and decoding the PWK data in accordance to the DiSEqC protocol. Full
compliance of the system to the specification is thus not implied by the bare use of the
LNBH221. The system designer should also take in consideration the bus hardware
requirements; that can be simply accomplished by the R-L termination connected on the
VOUT pins of the LNBH221, as shown in the Typical Application Circuit on page 7, 8. To
avoid any losses due to the R-L impedance during the tone transmission, the LNBH221 has
dedicated output (VOTX) that, in a DiSEqC 2.0 application, is connected after the filter and
must be enabled by setting the TTX SR bit HIGH only during the tone transmission (see
DiSEqC 2.O operation description on page 9).
Unidirectional (1.x) DiSEqC and non-DiSEqC systems normally don't need this termination,
and the VOTX pin can be directly connected to the LNB supply port of the Tuner (see
DiSeqC 1.x application circuit on pag. 7, 8). There is also no need of Tone Decoding, thus
DETIN and DSQOUT pins can be left unconnected and the Tone is provided by the VOTX.
15/27
Electrical characteristics
LNBH221
7
Electrical characteristics
Table 4.
Electrical characteristics of each section (A and B)
(TJ = 0 to 85°C, EN=1, TTX=0/1, LLC=VSEL=TEN=PCL=0, DSQIN=LOW, VIN=12V,
IOUT=50mA, unless otherwise specified. See software description section for I2C access to
the system register)
Symbol
VIN
IIN
Parameter
Supply Voltage
Supply Current
VOUT
Output Voltage
VOUT
Output Voltage
∆VOUT
Line Regulation
∆VOUT
Load Regulation
IMAX
Parameter
IOUT = 500 mA
TEN=VSEL=LLC=1
Min.
Typ.
8
Max.
Unit
15
V
EN=TEN=VSEL=LLC=1, No
Load
20
40
EN=0
3.5
7
IOUT = 500 mA
VSEL=1
IO = 500 mA
VSEL=0
VIN =8 to 15V
mA
LLC=0
17.3
18
18.7
LLC=1
18.7
19.5
20.3
LLC=0
12.75 13.25 13.75
LLC=1
13.75 14.25 14.75
V
V
VSEL=0
5
40
VSEL=1
5
60
mV
VSEL = 0 or 1 IOUT = 50 to
500mA
Output Current Limiting
500
200
mV
750
mA
VSEL = 0
300
VSEL = 1
200
Dynamic Overload protection
OFF Time
PCL=0Output Shorted
900
ms
Dynamic Overload protection
ON Time
PCL=0Output Shorted
tOFF/1
0
ms
fTONE
Tone Frequency
TEN=1
20
22
24
KHz
ATONE
Tone Amplitude
TEN=1
0.55
0.72
0.9
VPP
DTONE
Tone Duty Cycle
TEN=1
40
50
60
%
tr, tf
Tone Rise and Fall Time
TEN=1
5
8
15
µs
GEXTM
External Modulation Gain
∆VOUT/∆VEXTM, f = 10Hz to
50KHz, TTX=1
VEXTM
External Modulation Input
Voltage
AC Coupling, TTX=1
400
mVPP
ZEXTM
External Modulation Impedance f = 10Hz to 50KHz
260
W
fSW
DC/DC Converter Switch
Frequency
220
kHz
fDETIN
Tone Detector Frequency
Capture Range
ISC
Output Short Circuit Current
tOFF
tON
16/27
mA
0.4Vpp sinewave
6
18
24
kHz
LD39150
Table 4.
Electrical characteristics
Electrical characteristics of each section (A and B)
(TJ = 0 to 85°C, EN=1, TTX=0/1, LLC=VSEL=TEN=PCL=0, DSQIN=LOW, VIN=12V,
IOUT=50mA, unless otherwise specified. See software description section for I2C access to
the system register)
Symbol
Parameter
VDETIN
Tone Detector Input Amplitude
ZDETIN
Tone Detector Input Impedance
Parameter
fIN=22kHz sinewave
Min.
Typ.
0.2
Max.
Unit
1.5
VPP
150
VOL
DSQOUT Pin Logic LOW
Tone presentIOL=2mA
IOZ
DSQOUT Pin Leakage Current
Tone absentVOH = 6V
VIL
DSQIN Input Pin Logic LOW
VIH
DSQIN Input Pin Logic HIGH
IIH
DSQIN Pin Input Current
VIH = 5V
15
IOBK
Output Backward Current
EN=0 VOBK = 18V
-6
0.3
kΩ
0.5
V
10
µA
0.8
V
2
V
µA
-15
mA
TSHDN
Thermal Shutdown Threshold
150
°C
∆TSHDN
Thermal Shutdown Hysteresis
15
°C
Table 5.
Symbol
Gate And Sense Electrical Characteristics (TJ = 0 to 85°C, VIN=12V)
Parameter
Parameter
Min.
Typ.
Max.
Unit
RDSON-L
Gate LOW RDSON
IGATE=-100mA
4.5
Ω
RDSON-H
Gate LOW RDSON
IGATE=100mA
4.5
Ω
VSENSE
Current Limit Sense Voltage
200
mV
Table 6.
Symbol
I2C Electrical Characteristics (TJ = 0 to 85°C, VIN=12V)
Parameter
Parameter
VIL
LOW Level Input Voltage
SDA, SCL
VIH
HIGH Level Input Voltage
SDA, SCL
IIN
Input Current
SDA, SCL, VIN= 0.4 to 4.5V
VOL
Low Level Output Voltage
SDA (open drain), IOL = 6mA
fMAX
Maximum Clock Frequency
SCL
Table 7.
Symbol
Min.
Typ.
Max.
Unit
0.8
V
2
V
-10
10
µA
0.6
V
500
KHz
Address Pin Characteristics (TJ = 0 to 85°C, VIN=12V)
Parameter
Parameter
Min.
Typ.
Max.
Unit
VADDR-1
"0001000" Addr Pin Voltage
0
0.7
V
VADDR-2
"0001001" Addr Pin Voltage
1.3
1.7
V
VADDR-3
"0001010" Addr Pin Voltage
2.3
2.7
V
VADDR-4
"0001011" Addr Pin Voltage
3.3
5
V
VADDR-1
"0001000" Addr Pin Voltage
0
0.7
V
17/27
Thermal design notes
8
LNBH221
Thermal design notes
During normal operation, the LNBH221 device dissipates some power. At rated output
current of 500mA on each section output, the voltage drop on both linear regulators lead to
a total dissipated power that is typically 2W. The heat generated requires a suitable heatsink
to keep the junction temperature below the over-temperature protection threshold.
Assuming a 45°C temperature inside the Set-Top-Box case, the total RthJC has to be less
than 40°C/W.
While this can be easily achieved using a through-hole power package that can be attached
to a small heatsink or to the metallic frame of the receiver, a surface mount power package
must rely on PCB solutions whose thermal efficiency is often limited. The simplest solution
is to use a large, continuous copper area of the GND layer to dissipate the heat coming from
the IC body.
Given for the PSO-36 package an RthJC equal to 2°C/W, a maximum of 38°C/W are left to
the PCB heatsink. This area can be the inner GND layer of a multi-layer PCB, or, in a dual
layer PCB, an unbroken GND area even on the opposite side where the IC is placed. In
Figure 8., it is shown a suggested layout for the PSO-36 package with a dual layer PCB,
where the IC exposed pad connected to GND and the square dissipating area are thermally
connected through 32 vias holes, filled by solder. This arrangement, when L=40mm,
achieves an RthJA of about 28°C/W.
Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its
ground exposed pad approximately in the middle of the dissipating area; to provide as many
vias as possible; to design a dissipating area having a shape as square as possible and not
interrupted by other copper traces.
Figure 8.
18/27
PowerSO-36 Suggested Pcb Heatsink Layout
LD39150
9
Typical performance characteristics (of each section)
Typical performance characteristics (of each section)
(TJ = 25°C, unless otherwise specification)
Figure 9.
Output Voltage vs Temperature
Figure 10. Output Voltage vs Temperature
Figure 11. Output Voltage vs Temperature
Figure 12. Load Regulation vs Temperature
Figure 13. Load Regulation vs Temperature
Figure 14. Supply Current vs Temperature
19/27
Typical performance characteristics (of each section)
LNBH221
Figure 15. Supply Current vs Temperature
Figure 16. Supply Current vs Temperature
Figure 17. Dynamic Overload Protection ON
Time vs Temperature
Figure 18. Dynamic Overload Protection OFF
Time vs Temperature
Figure 19. Output Current Limiting vs
Temperature
Figure 20. Tone Frequency vs Temperature
20/27
LD39150
Typical performance characteristics (of each section)
Figure 21. Tone Amplitude vs Temperature
Figure 22. Tone Duty Cycle vs Temperature
Figure 23. Tone Rise Time vs Temperature
Figure 24. Tone Fall Time vs Temperature
Figure 25. Undervoltage Lockout Threshold vs Figure 26. Output Backward Current vs
Temperature
Temperature
21/27
Typical performance characteristics (of each section)
LNBH221
Figure 27. DC/DC Converter Efficiency vs
Temperature
Figure 28. Current Limit Sense Voltage vs
Temperature
Figure 29. 22kHz Tone Waveform
Figure 30. DSQIN Tone Enable Transient
Response
VCC=12V, IO=50mA, EN=TEN=1
VCC=12V, IO=50mA, EN=1, Tone enabled by DSQIN Pin
Figure 31. DSQIN Tone Enable Transient
Response
Figure 32. DSQIN Tone Disable Transient
Response
VCC=12V, IO=50mA, EN=1, Tone enabled by DSQIN Pin
VCC=12V, IO=50mA, EN=1, Tone enabled by DSQIN Pin
22/27
LD39150
10
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
23/27
Package mechanical data
LNBH221
PowerSO-36 MECHANICAL DATA
DIM.
A
a1
a2
a3
b
c
D (1)
D1
E
E1 (1)
E2
E3
e
e3
G
H
h
L
N
S
mm.
MIN.
TYP
inch
MAX.
3.60
0.30
3.30
0.10
0.38
0.32
16.00
9.80
14.50
11.10
2.90
6.2
0.10
0
0.22
0.23
15.80
9.40
13.90
10.90
5.8
MIN.
TYP.
0.0039
0
0.0087
0.0091
0.6220
0.3701
0.5472
0.4291
0.2283
0.65
11.05
0
15.50
0.80
0°
MAX.
0.1417
0.0118
0.1299
0.0039
0.0150
0.0126
0.6299
0.3858
0.5709
0.4370
0.1142
0.2441
0.0256
0.4350
0.10
15.90
1.10
1.10
10°
8°
0.0000
0.6102
0.0039
0.6260
0.0433
0.0433
10°
8°
0.0315
0°
6
(1) “D and E1” do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.00 ”)
0096119/B
24/27
LD39150
Package mechanical data
Tape & Reel PowerSO-36 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
TYP
MAX.
MIN.
330
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
TYP.
0.504
30.4
0.519
1.197
Ao
15.1
15.3
0.594
0.602
Bo
16.5
16.7
0.650
0.658
Ko
3.8
4.0
0.149
0.157
Po
3.9
4.1
0.153
0.161
P
23.9
24.1
0.941
0.949
W
23.7
24.3
0.933
0.957
25/27
Revision history
LNBH221
11
Revision history
Table 8.
Document revision history
Date
Revision
08-Apr-2005
4
Maturity Changed.
23-Feb-2006
5
The Figure 3. and Figure 4. has been updated.
26/27
Changes
LD39150
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27/27