M74HC595 8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE) ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 59MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN.) FOR QA to QH |IOH| = IOL = 4mA (MIN.) FOR QH’ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 595 DESCRIPTION The M74HC595 is an high speed CMOS 8-BIT SHIFT REGISTERS/OUTPUT LATCHES (3-STATE) fabricated with silicon gate C2MOS technology. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP M74HC595B1R M74HC595M1R T&R M74HC595RM13TR M74HC595TTR The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS March 2004 1/16 M74HC595 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN N° SYMBOL 1, 2, 3, 4, 5, 6, 7, 15 9 10 11 13 14 12 QA to QH 8 16 GND VCC QH’ SCLR SCK G SI RCK NAME AND FUNCTION Data Outputs Serial Data Outputs Shift Register Clear Input Shift Register Clock Input Output Enable Input Serial Data Input Storage Register Clock Input Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS SI SCK SCLR RCK G X X X X X X X X L X X X H L X L H X X H H X X X H X X STATE OF S.R. IS NOT CHANGED X X X X S.R. DATA IS STORED INTO STORAGE REGISTER X X X X STORAGE REGISTER STATE IS NOT CHANGED X: Don’t Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/16 QA THRU QH OUTPUTS DISABLE QA THRU QH OUTPUTS ENABLE SHIFT REGISTER IS CLEARED FIRST STAGE OF S.R. BECOMES "L" OTHER STAGES STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY FIRST STAGE OF S.R. BECOMES "H" OTHER STAGES STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY M74HC595 LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays TIMING CHART 3/16 M74HC595 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 35 mA VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current Power Dissipation DIP SOP TSSOP PD Tstg Storage Temperature TL Lead Temperature (10 sec) V ± 70 mA 750(*) 500(*) 450(*) mW mW mW -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) Power dissipation at 65°C. Derating from 65°C to 125°C: DIP Package -10mW/°C; SO Package -7mW/°C; TSSOP Package -6.1mW/°C. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage Top Operating Temperature Input Rise and Fall Time tr, tf 4/16 Value Unit 2 to 6 V 0 to VCC V 0 to VCC V -55 to 125 °C VCC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns M74HC595 DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOH VOL VOL II IOZ ICC Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage (for QH’ outputs) High Level Output Voltage (for QA to QH outputs) Low Level Output Voltage (for QH’ outputs) Low Level Output Voltage (for QA to QH outputs) Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 4.5 6.0 2.0 4.5 6.0 Typ. Max. 1.5 3.15 4.2 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 Max. 1.5 3.15 4.2 0.5 1.35 1.8 V 0.5 1.35 1.8 2.0 IO=-20 µA 1.9 2.0 1.9 1.9 4.5 IO=-20 µA 4.4 4.5 4.4 4.4 6.0 IO=-20 µA 5.9 6.0 5.9 5.9 4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10 Unit V V 6.0 IO=-7.8 mA 5.68 5.8 5.63 5.60 2.0 IO=-20 µA 1.9 2.0 1.9 1.9 4.5 IO=-20 µA 4.4 4.5 4.4 4.4 6.0 IO=-20 µA 5.9 6.0 5.9 5.9 4.5 IO=-6.0 mA 4.18 4.31 4.13 4.10 6.0 IO=-7.8 mA 5.68 5.8 5.63 5.60 2.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=20 µA 0.0 0.1 0.1 0.1 6.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=4.0 mA 0.17 0.26 0.33 0.40 6.0 IO=7.8 mA 0.18 0.26 0.33 0.40 2.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=20 µA 0.0 0.1 0.1 0.1 V V 6.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=6.0 mA 0.17 0.26 0.33 0.40 6.0 IO=7.8 mA 0.18 0.26 0.33 0.40 6.0 VI = VCC or GND ± 0.1 ±1 ±1 µA 6.0 VI = VIH or VIL VO = VCC or GND ± 0.5 ±5 ± 10 µA 6.0 VI = VCC or GND 4 40 80 µA V 5/16 M74HC595 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time (Qn) tTLH tTHL Output Transition Time (QH’) tPLH tPHL Propagation Delay Time (SCK - QH’) tPLH tPHL Propagation Delay Time (SCLR - QH’) tPLH tPHL Propagation Delay Time (RCK - Qn) tPZL tPZH High Impedance Output Enable Time tPLZ tPHZ High Impedance Output Disable Time fMAX tW(H) tW(L) ts ts 6/16 Maximum Clock Frequency Minimum Pulse Width (SCK, RCK) Minimum Pulse Width (SCLR) Minimum Set-up Time (SI - CCK) Minimum Set-up Time (SCK - RCK) VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Value TA = 25°C CL (pF) Min. 50 50 50 50 50 150 50 RL = 1 KΩ 150 RL = 1 KΩ 50 RL = 1 KΩ 50 150 50 50 50 50 6.0 30 35 5.2 26 31 Typ. Max. 25 7 6 30 8 7 45 15 13 60 18 15 60 20 17 75 25 22 45 15 13 60 20 17 30 15 14 17 50 59 14 40 45 17 6 6 20 6 6 25 5 4 35 8 6 60 12 10 75 15 13 125 25 21 175 35 30 150 30 26 190 38 32 135 27 23 175 35 30 150 30 26 -40 to 85°C -55 to 125°C Min. Min. Max. 75 15 13 95 19 16 155 31 26 220 44 37 190 38 32 240 48 41 170 34 29 220 44 37 190 38 32 4.8 24 28 4.2 21 25 75 15 13 75 15 13 50 10 9 75 15 13 Max. 90 18 15 115 23 20 190 38 32 265 53 45 225 45 38 285 57 48 205 41 35 265 53 45 225 45 38 4 20 24 3.4 17 20 95 19 16 95 19 16 65 13 11 95 19 16 Unit ns ns ns ns ns ns ns ns ns MHz MHz 110 22 19 110 22 19 75 15 13 110 22 19 ns ns ns ns M74HC595 Test Condition Symbol ts th tREM Parameter Minimum Set-up Time (SCRL - RCK) Minimum Hold Time Minimum Clear Removal Time VCC (V) CL (pF) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Value TA = 25°C Min. 50 Typ. Max. 40 10 7 100 20 17 0 0 0 50 10 9 50 15 3 3 50 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 125 25 21 0 0 0 65 13 11 145 29 25 0 0 0 75 15 13 ns ns ns CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter Value TA = 25°C VCC (V) Min. Typ. Max. 10 CIN Input Capacitance 5 CPD Power Dissipation Capacitance (note 1) 184 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 10 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC TEST CIRCUIT TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VCC tPZH, tPHZ GND CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) 7/16 M74HC595 WAVEFORM 1: SCK TO QH’ PROPAGATION DELAY TIMES, SCK MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle) WAVEFORM 2: RCK TO Qn PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: SI TO SCK SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 8/16 M74HC595 WAVEFORM 4: SCK TO RCK SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 5: SCLR MINIMUM PULSE WIDTH, MINIMUM REMOVAL TIME (f=1MHz; 50% duty cycle) 9/16 M74HC595 WAVEFORM 6: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 7: INPUT WAVEFORM (f=1MHz; 50% duty cycle) 10/16 M74HC595 Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 11/16 M74HC595 SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.004 0.008 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45˚ (typ.) D 9.8 E 5.8 10 0.385 6.2 0.228 0.393 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 8 0.024 ˚ (max.) PO13H 12/16 M74HC595 TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0˚ L 0.45 A 0.60 0.0256 BSC 8˚ 0˚ 0.75 0.018 8˚ 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 13/16 M74HC595 Tape & Reel SO-16 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 14/16 TYP 0.504 22.4 0.519 0.882 Ao 6.45 6.65 0.254 0.262 Bo 10.3 10.5 0.406 0.414 Ko 2.1 2.3 0.082 0.090 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 M74HC595 Tape & Reel TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 22.4 0.519 0.882 Ao 6.7 6.9 0.264 0.272 Bo 5.3 5.5 0.209 0.217 Ko 1.6 1.8 0.063 0.071 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 15/16 M74HC595 Information furnished is believed to be accurate and reliable. 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