STB70NH03L N-channel 60V - 0.0075Ω - 70A - D2PAK STripFET™ III Power MOSFET for DC-DC conversion General features Type VDSS RDS(on) ID STB70NH03L 30V < 0.009Ω 60A (1) ■ RDS(on) x Qg industry benchmark ■ Conduction losses reduced ■ Switching losses reduced ■ Low threshold device 3 1 D²PAK Description The device utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. It is ideal in high performance DC-DC converter applications where efficiency is to be achieved at very high output currents. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STB70NH03LT4 B70NH03L D²PAK Tape & reel July 2006 Rev 6 1/15 www.st.com 15 Contents STB70NH03L Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 ................................................ 8 STB70NH03L 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol VDS VDGR Parameter Value Unit Drain-source Voltage (VGS = 0) 30 V Drain-gate Voltage (RGS = 20 kΩ) 30 V ± 20 V VGS Gate- source Voltage ID (1) Drain Current (continuous) at TC = 25°C 60 A Drain Current (continuous) at TC = 100°C 43 A Drain Current (pulsed) 240 A Total Dissipation at TC = 25°C 858 W ID (1) IDM (2) PTOT Derating Factor EAS (3) Tstg TJ W/°C Single Pulse Avalanche Energy 300 mJ -55 to 175 °C Value Unit Storage Temperature Operating Junction Temperature 1. Value limited by wire bonding 2. Pulse width limited by safe oper`ting area 3. Starting TJ = 25 oC, ID = 30A, VDD = 20V Table 2. Symbol Thermal data Parameter RthJC Thermal resistance junction-case max 1.87 °C/W RthJA Thermal resistance junction-ambient max 62.5 °C/W Tl Maximum lead temperature for soldering purpose 300 °C 3/15 Electrical characteristics 2 STB70NH03L Electrical characteristics (TCASE = 25°C unless otherwise specified) Table 3. On/off states Symbol Parameter Test conditions Drain-source breakdown voltage ID = 250 µA, VGS = 0 IDSS Zero gate voltage Drain current (VGS = 0) VDS = max rating VDS = max rating TC = 125°C IGSS Gate-body leakage Current (VDS = 0) VGS = ± 20 V VGS(th) Gate threshold voltage VDS = VGS ID = 250 µA RDS(on) Static drain-source on resistance VGS = 10 V VGS = 5 V ID = 30 A ID = 30 A V(BR)DSS Table 4. Symbol Typ Max 30 Unit V 1 10 µA µA ±100 nA 1 V 0.0075 0.0095 0.0135 0.009 Ω Ω Dynamic Parameter Test conditions gfs (1) Forward transconductance VDS = 10 V Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS = 10V f = 1 MHz VGS = 0 Gate Input Resistance td(on) tr td(off) tf ID = 18 A Min Typ Max Unit 25 S 2200 380 49 pF pF pF f = 1 MHz gate DC bias = 0 test signal level = 20 mV open drain 1.5 Ω Turn-on delay time Rise time Turn-off delay Time Fall time VDD = 15 V RG = 4.7 Ω 21 95 19 15 ns ns Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD= 15V ID= 70A VGS= 5V Qgls(2) Third-quadrant gate charge VDS< 0 V VGS= 10 V RG ID = 30 A VGS = 5 V 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 2. Gate charge for synchronous operation . See Chapter 6: Appendix A 4/15 Min 15.7 8.3 3.4 15 21 nC nC nC nC STB70NH03L Electrical characteristics Table 5. Symbol ISD ISDM (1) VSD(2) trr Qrr IRRM Source drain diode Parameter Test conditions Min Typ Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 30 A VGS = 0 Reverse recovery time I = 60 A di/dt = 100A/µs Reverse recovery charge SD TJ = 150°C VDD = 20 V Reverse recovery current 32 51 3.2 Max Unit 60 240 A A 1.3 V ns nC A 1. Pulse width limited by safe operating area 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 5/15 Electrical characteristics STB70NH03L 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/15 STB70NH03L Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 12. Normalized Breakdown vs temperature 7/15 Test circuit 3 STB70NH03L Test circuit Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform 8/15 STB70NH03L 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/15 Package mechanical data STB70NH03L D2PAK MECHANICAL DATA TO-247 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 A2 0.03 0.23 0.001 0.009 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 0.368 D1 E 8 10 E1 0.315 10.4 0.393 8.5 0.334 G 4.88 5.28 0.192 0.208 L 15 15.85 0.590 0.625 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.068 M 2.4 3.2 0.094 0.126 R 0.4 0º 0.015 4º 3 V2 1 10/15 STB70NH03L 5 Packaging mechanical data Packaging mechanical data D2PAK FOOTPRINT TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. mm MIN. A B DIM. mm inch MIN. MAX. MIN. A0 10.5 10.7 0.413 0.421 B0 15.7 15.9 0.618 0.626 D 1.5 1.6 0.059 0.063 D1 1.59 1.61 0.062 0.063 E 1.65 1.85 0.065 0.073 F 11.4 11.6 0.449 0.456 K0 4.8 5.0 0.189 0.197 0.153 0.161 MAX. MIN. 330 1.5 C 12.8 D 20.2 G 24.4 N 100 T TAPE MECHANICAL DATA inch MAX. 12.992 0.059 13.2 0.504 0.520 26.4 0.960 1.039 0795 3.937 30.4 1.197 BASE QTY BULK QTY 1000 1000 MAX. P0 3.9 4.1 P1 11.9 12.1 0.468 0.476 P2 1.9 2.1 0.075 0.082 R 50 T 0.25 0.35 0.0098 0.0137 W 23.7 24.3 1.574 0.933 0.956 * on sales type 11/15 Appendix A 6 STB70NH03L Appendix A Figure 18. Buck converter: power losses estimation The power losses associated with the FETs in a synchronous buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. 12/15 ● The low side (SW2) device requires: ● Very low RDS(on) to reduce conduction losses ● Small Qgls to reduce the gate charge losses ● Small Coss to reduce losses due to output capacitance ● Small Qrr to reduce losses on SW1 during its turn-on ● The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source ● voltage to avoid the cross conduction phenomenon; ● The high side (SW1) device requires: ● Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate ● Small Qg to have a faster commutation and to reduce gate charge losses ● Low RDS(on) to reduce the conduction losses. STB70NH03L Appendix A Table 6. Power losses calculation High side switching (SW1) Low side switch (SW2) R DS(on)SW1 * I 2L * δ R DS(on)SW2 * I 2L * (1 − δ ) Pconduction Vin * (Q gsth(SW1) + Q gd(SW1) ) * f * Pswitching Recovery IL Ig Zero Voltage Switching (1) Not applicable Vin * Q rr(SW2) * f Conductio n Not applicable Vf(SW2) * I L * t deadtime * f Pgate(QG) Q g(SW1) * Vgg * f Q gls(SW2) * Vgg * f PQoss Vin * Q oss(SW1) * f Vin * Q oss(SW2) * f 2 2 Pdiode 1. Dissipated by SW1 during turn-on Table 7. Paramiters meaning Parameter d Meaning Duty-cycle Qgsth Post threshold gate charge Qgls Third quadrant gate charge Pconduction Pswitching On state losses On-off transition losses Pdiode Conduction and reverse recovery diode losses Pgate Gate drive losses PQoss Output capacitance losses 13/15 Revision history 7 STB70NH03L Revision history Table 8. 14/15 Revision history Date Revision Changes 21-Jun-2004 5 Complete document 20-Jul-2006 6 New template, no content change STB70NH03L Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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