STLC3085 Integrated Pots Interface for Home Access Gateway and WLL Preliminary Data Features ■ Monochip SLIC optimised for WLL & VoIP applications ■ Implement all key features of the borsht function ■ Single supply (4.5 to 12V) ■ Built in DC/DC Converter controller ■ Soft battery reversal with programmable transition time ■ On-hook transmission ■ Programmable off-hook detector threshold ■ Integrated ringing ■ Integrated ring trip ■ Parallel control interface (3.3V logic level) ■ Programmable constant current feed ■ Surface mount package ■ Integrated thermal protection ■ Dual gain value option ■ Automatic recognition flyback and buckboost configuration ■ BCDIIIS 90V technology ■ -40 to +85°C operating range TQFP44 is the ability to operate with a single supply voltage (from +4.5V to +12V) and self generate the negative battery by means of an on chip DC/ DC converter controller that drives an external MOS switch. The battery level is properly adjusted depending on the operating mode. A useful characteristic for these applications is the integrated ringing generator. The control interface is a parallel type with open drain output and 3.3V logic levels. Constant current feed can be set from 20mA to 25mA. Off-hook detection threshold is programmable from 5mA to 9mA. Description The STLC3085 is a SLIC device specifically designed for WLL (Wireless Local Loop), and ISDN Terminal Adaptors and VoIP applications. One of the distinctive characteristic of this device The device, developed in BCDIIIS technology (90V process), operates in the extended temperature range and integrates a thermal protection that sets the device in power down when Tj exceeds 140°C.. Order codes Part number Temp range, °C Package Packing E-STLC3085 (*) -40 to 85 TQFP44 Tube (*) ECOPACK® (see Section 5) February 2006 Rev 1 1/28 www.st.com 28 STLC3085 Contents Contents 1 2 3 4 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 DC/DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.1 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.2 High impedance feeding (HI-Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.3 Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.4 Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.5 Layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.6 External components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Applications diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Appendix A STLC3085 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Appendix B STLC3085 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Appendix C Typical state diagram for STLC3085 operation . . . . . . . . . . . . . . . . 25 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/28 STLC3085 Block diagram and pin description 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram D0 D1 D2 DET INPUT LOGIC AND DECODER OUTPUT LOGIC BGND Status and functions TIP TX RX SUPERVISION LINE OUTPUT DRIVER STAGE ZAC1 RING AC PROC ZAC RS CREV ZB DC PROC CSVR CLK RSENSE GATE VF DC/DC CONV. REFERENCE Vcc CVCC VPOS Vss VBAT VOLT. REG. Agnd Vbat CAC AGND Pin connection N.C. N.C. N.C. 41 40 39 38 CSVR TIP 42 BGND N.C. 43 RING CREV 44 VBAT VBAT1 Pin connection 37 36 35 34 4 30 IREF GAIN SET 5 29 RLIM N.C. 6 28 AGND DET 7 27 CVCC RES 8 26 VPOS RES 9 25 RSENSE RES 10 24 GATE RES 11 23 CLK 12 13 14 15 16 17 18 19 20 21 22 VF RTH PD N.C. 31 CZ RD 3 TX 32 D2 ZB D1 CAC ILTF RS 33 2 ZAC 1 ZAC1 D0 RX Figure 2. RES 1.2 ILTF RD IREF RLIM RTH D00TL488 3/28 STLC3085 Block diagram and pin description 1.3 Table 1. Pin description Pin description N° Pin Function 1 D0 Control Interface: input bit 0. 2 D1 Control Interface: input bit 1. 3 D2 Control interface: input bit 2. 4 PD Power Down input. Normally connected to CVCC (or to logic level high). 5 Gain SET 6,22,38, 39,40,42 NC Not connected. 7 DET Logic interface output of the supervision detector (active low). Control gain interface: 0 Level Rxgain = 0dB Txgain = -6dB 1 Level Rxgain = +6dB Txgain = -12dB 8 RESERVED Connected to GND 9 RESERVED Connected to GND 10 RESERVED Connected to GND 11 RESERVED Left open. 12 RESERVED Connected to GND 4 wire input port (RX input); 300KΩ input impedance. This signal is referred to AGND. If connected to single supply CODEC output it must be DC decoupled with proper capacitor. 13 RX 14 ZAC1 RX buffer output (the AC impedance is connected from this node to ZAC). 15 ZAC AC impedance synthesis. 16 RS Protection resistors image (the image resistor is connected from this node to ZAC). 17 ZB Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from this node to AGND. ZA impedance is connected from this node to ZAC1). 18 CAC 19 TX 4 wire output port (TX output). The signal is referred to AGND. If connected to single supply CODEC input it must be DC decoupled with proper capacitor. 20 CZ Fly-Back compensation 21 VF Feedback input for DC/DC converter controller. 23 CLK 24 GATE 25 RSENSE 4/28 AC feedback input, AC/DC split capacitor (CAC). Power Switch Controller Clock (typ. 125KHz). This pin can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an internal auto-oscillation is internally generated and it is used instead of the external clock. When the CLK pin is connected to AGND, the GATE output is disabled. Driver for external Power MOS transistor (P-chanell in Buck-boost configuration, Nchannel in Fly-back configuration). Voltage input for current sensing. RSENSE resistor should be connected close to this pin and VPOS pin (Buck-boost) or GND (Fly-back). The PCB layout should minimize the extra resistance introduced by the copper tracks. STLC3085 Table 1. Block diagram and pin description Pin description (continued) N° Pin 26 VPOS Positive supply input. 27 CVCC Internal positive voltage supply filter. 28 AGND Analog Ground, must be shorted with BGND. 29 RLIM Constant current feed programming pin (via RLIM). RLIM should be connected close to this pin and AGND pin to avoid noise injection. 30 IREF Internal bias current setting pin. RREF should be connected close to this pin and AGND pin to avoid noise injection. 31 RTH Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin and AGND pin to avoid noise injection. 32 RD DC feedback and ring trip input. RD should be connected close to this pin and AGND pin to avoid noise injection. 33 ILTF Transversal line current image output. 34 CSVR Battery supply filter capacitor. 35 BGND Battery Ground, must be shorted with AGND. 36 VBAT Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted to VBAT1. 37 RING 2 wire port; RING wire (Ib is the current sunk into this pin). 41 TIP 43 CREV Reverse polarity transition time control. A proper capacitor connected between this pin and AGND is setting the reverse polarity transition time. This is the same transition time used to shape the "trapezoidal ringing" during ringing injection. 44 VBAT1 Frame connection. Must be shorted to VBAT. 1.4 Function 2 wire port; TIP wire (Ia is the current sourced from this pin). Thermal data Table 2. Symbol Rth j-amb Thermal data Parameter Thermal Resistance Junction to Ambient Typ. Value Unit 60 °C/W 5/28 STLC3085 Electrical specification 2 Electrical specification 2.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Value Unit -0.4 to +13 V -1 to +1 V -0.4 to 5.5 V Max. junction Temperature 150 °C Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device supply pins). 85 V Human Body Model ±1750 V Charged Device Model ±500 V Value Unit 4.5 to +12 V AGND to BGND -100 to +100 mV Vdig Pin D0, D1, D2, DET, PD -0.25 to 5.25 V Top Ambient Operating Temperature Range -40 to +85 °C -64 max. V Vpos A/BGND Vdig Tj Vbtot ESD RATING 2.2 Parameter Positive Supply Voltage AGND to BGND Pin D0, D1, D2, DET Operating range Table 4. Operating range Symbol Vpos A/BGND Vbat (1) Parameter Positive Supply Voltage Self Generated Battery Voltage (1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 shall be selected in order to fulfil the a.m limits (see Table 10 ) 6/28 STLC3085 2.3 Electrical specification Electrical characteristics Table 5. Electrical characteristics Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25°C. External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25°C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85°C. Symbol Parameter Test Condition Min. Typ. Max. Unit DC CHARACTERISTICS Vlohi Line voltage Il = 0, HI-Z (High impedance feeding) Tamb = 0 to 85°C 40 46 V Vlohi Line voltage Il = 0, HI-Z (High impedance feeding) Tamb = -40 to 85°C 38 44 V Vloa Line voltage Il = 0, ACTIVE Tamb = 0 to 85°C 31 38 V Vloa Line voltage Il = 0, ACTIVE Tamb = -40 to 85°C 29 35 V Ilim Lim. current programming range ACTIVE mode 20 25 mA Ilima Lim. current accuracy ACTIVE mode. Rel. to programmed value 20mA to 25mA -10 10 % Feeding resistance HI-Z (High Impedance feeding) 2.4 3.6 kΩ Rfeed HI AC CHARACTERISTICS Rp = 50Ω, 1% tol., L/T Long. to transv. (see Appendix for test circuit) ACTIVE N. P., RL = 600Ω (1) 50 58 dB 40 45 dB 48 53 dB 22 26 dB f = 300 to 3400Hz Rp = 50Ω, 1% tol., T/L Transv. to long. (see Appendix for test circuit) ACTIVE N. P., RL = 600Ω (1) f = 300 to 3400Hz Rp = 50Ω, 1% tol., T/L Transv. to long. (see Appendix for test circuit) ACTIVE N. P., RL = 600Ω (1) f = 1kHz 300 to 3400Hz, 2WRL THL 2W return loss Trans-hybrid loss ACTIVE N. P., RL = 600Ω (1) 300 to 3400Hz, 20Log|VRX/VTX|, ACTIVE N. P., RL = 600Ω 30 dB (1) 7/28 STLC3085 Electrical specification Table 5. Electrical characteristics (continued) Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25°C. External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25°C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85°C. Symbol Parameter Test Condition Min. Typ. Max. Unit at line terminals on ref. imped. Ovl 2W overload level TXoff TX output offset G24 Transmit gain abs. G42 Receive gain abs. ACTIVE N. P., RL = 600Ω (1) ACTIVE N. P., RL = 600Ω (1) 3.2 dBm -250 250 mV -6.4 -5.6 dB -0.4 0.4 dB -0.12 0.12 dB -0.12 0.12 dB -68 dBmp 0dBm @ 1020Hz, ACTIVE N. P., RL = 600Ω (1) 0dBm @ 1020Hz, G24f TX gain variation vs. freq. ACTIVE N. P., RL = 600Ω (1) rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., RL = 600Ω (1) G24f RX gain variation vs. freq. rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., RL = 600Ω (1) psophometric filtered V2Wp Idle channel noise at line 0dB gainset ACTIVE N. P., RL = 600Ω (1) -73 Tamb = 0 to +85°C psophometric filtered V2Wp Idle channel noise at line 0dB gainset ACTIVE N. P., RL = 600Ω (1) -68 dBmp Tamb = -40 to +85°C psophometric filtered V4Wp Idle channel noise at line 0dB gainset ACTIVE N. P., RL = 600Ω (1) -75 -70 dBmp Tamb = 0 to +85°C psophometric filtered V4Wp Thd CLKfreq Idle channel noise at line 0dB gainset ACTIVE N. P., RL = 600Ω (1) Total Harmonic Distortion ACTIVE N. P., RL = 600Ω (1) -75 dBmp Tamb = -40 to +85°C CLK operating range -10% 125 41 45 -44 dB 10% kHz RING Vring 8/28 Line voltage RING D2 toggling @ fr = 25Hz Load = 2REN; Crest Factor = 1.25 1REN = 1800Ω + 1.0µF Tamb = 0 to +85°C Vrms STLC3085 Table 5. Electrical specification Electrical characteristics (continued) Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25°C. External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25°C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85°C. Symbol Vring Parameter Line voltage Test Condition Min. Typ. RING D2 toggling @ fr = 25Hz Load = 2REN; Crest Factor = 1.25 1REN = 1800Ω + 1.0µF Tamb = -40 to +85°C 40 44 10.5 Max. Unit Vrms DETECTORS IOFFTHA Off/hook current threshold ACT. mode, RTH = 32.4kΩ 1% (Prog. ITH = 9mA) ROFTHA Off/hook loop resistance threshold ACT. mode, RTH = 32.4kΩ 1% (Prog. ITH = 9mA) 3.4 kΩ IONTHA On/hook current threshold ACT. mode, RTH = 32.4kΩ 1% (Prog. ITH = 9mA) 6 mA RONTHA On/hook loop resistance threshold ACT. mode, RTH = 32.4kΩ 1% (Prog. ITH = 9mA) 8 kΩ IOFFTHI Off/hook current threshold Hi Z mode, RTH = 32.4kΩ 1% (Prog. ITH = 9mA) 10.5 mA ROFFTHI Off/hook loop resistance threshold Hi Z mode, RTH = 32.4kΩ 1% (Prog. ITH = 9mA) 800 W IONTHI On/hook current threshold Hi Z mode, RTH = 32.4kΩ 1% (Prog. ITH = 9mA) 6 mA RONTHI On/hook loop resistance threshold Hi Z mode, RTH = 32.4kΩ 1% (Prog. ITH = 9mA) 8 Irt Ring Trip detector threshold range RING 20 50 mA Irta Ring Trip detector threshold accuracy RING -15 15 % Trtd Ring trip detection time RING Td Dialling distortion ACTIVE Rlrt (2) ThAl mA kΩ TBD -1 Loop resistance Tj for th. alarm activation ms 1 ms 500 W 160 °C DIGITAL INTERFACE INPUTS: D0, D1, D2, PD, CLK OUTPUTS: DET Vih In put high voltage Vil Input low voltage 2 V 0.8 V 9/28 STLC3085 Electrical specification Table 5. Electrical characteristics (continued) Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25°C. External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25°C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85°C. Symbol Parameter Test Condition Min. Typ. Max. Unit Iih Input high current -10 10 µA Iil Input low current -10 10 µA 0.45 V Vol Output low voltage Iol = 1mA PSRR AND POWER CONSUMPTION PSERRC Power supply rejection Vpos to Vripple = 100mVrms 2W port 50 to 4000Hz Ivpos Vpos supply current @ ii = 0 HI-Z On-Hook ACTIVE On-Hook, RING (line open) Ipk (3) Peak current limiting accuracy RING Off-Hook RSENSE = 130mΩ (1) RL: Line Resistance (2) Rlrt = Maximum loop resistance (incl. telephone) for correct ring trip detection. (3) Buck Boost configuration. 10/28 26 -20% 36 dB 13 50 55 25 80 90 mA mA mA 770 +20% mApk STLC3085 3 Functional description Functional description The STLC3085 is a device specifically developed for WLL VoIP and ISDN-TA applications. It is based on a SLIC core, on purpose optimised for these applications, with the addition of a DC/DC converter controller to fulfil the WLL and ISDN-TA design requirements. The SLIC performs the standard feeding, signalling and transmission functions. It can be set in three different operating modes via the D0, D1, D2 pins of the control logic interface (0 to 3.3V logic levels). The loop status is carried out on the DET pin (active low). The DET pin is an open drain output to allow easy interfacing with both 3.3V and 5V logic levels. The four possible SLIC’s operating modes are: ● Power Down ● High Impedance Feeding (HI-Z) ● Active ● Ringing Table 6 shows how to set the different SLIC operating modes. Table 6. SLIC operating modes. PD D0 D1 D2 Operating Mode 0 0 0 X Power Down 1 0 0 X H.I. Feeding (HI-Z) 1 0 1 0 Active Normal Polarity 1 0 1 1 Active Reverse Polarity Not used Not used 1 3.1 1 0 0/1 Ring (D2 bit toggles @ fring) DC/DC converter The DC/DC converter controller is driving an external power MOS transistor N-Ch plus transformer (Flyback configuration) or P-Ch plus inductor (BuckBoost configuration), in order to generate the negative battery voltage needed for device operation. The DC/DC converter controller is synchronised with an external CLK (125KHz typ.) or with an internal clock generated when the pin CLK is connected to CVCC. One Rsense in series to PGND supply (FlyBack) or to VPOS supply (BuckBoost) allows to fix the maximum allowed input peak current. This feature is implemented in order to avoid overload on Vpos supply in case of line transient (ex. ring trip detection). Typ. value of 130mΩ guarantees an average current consumption from Vpos < 600mA for BuckBoost configuration and < 1.25A for Fly- Back configuration. 11/28 STLC3085 Functional description Typ. value of 220mΩ guarantees an average current consumption from Vpos < 800mA for FlyBack configuration The self generated battery voltage is set to a predefined value in on-hook state. This value can be adjusted via one external resistor (RF1) and it is typical -46V. When RING mode is selected this value is increased to -64V typ. Once the line goes in off-hook condition, the DC/DC converter automatically adjusts the generated battery voltage in order to feed the line with a fixed DC current (programmable via RLIM) optimising the power dissipation. 3.2 Operating modes 3.2.1 Power down When this mode is selected the SLIC is switched off and the TIP and RING pins are in high impedance. Also the line detectors are disabled therefore the off-hook condition cannot be detected. This mode can be selected in emergency condition when it is necessary to cut any current delivered to the line. This mode is also forced by STLC3085 in case of thermal overload (Tj > 140°C). In this case the device goes back to the previous status as soon as the junction temperature decrease under the hysteresis threshold. No AC transmission is possible 3.2.2 High impedance feeding (HI-Z) This operating mode is normally selected when the telephone is in on-hook in order to monitor the line status keeping the power consumption at the minimum. The output voltage in on-hook condition is equal to the self generated battery voltage (-46V typ). When off-hook occurs the DET becomes active (low logic level). The off-hook threshold in HI-Z mode is the same value as programmed in ACTIVE mode. The DC characteristic in HI-Z mode is just equal to the self generated battery with 2x(1600Ω+Rp) in series (see Figure 3), where Rp is the external protection resistance. No AC transmission is possibile. Figure 3. DC Characteristic in HI-Z Mode. IL Vbat 2x(R1+Rp) Slope: 2x(R1+Rp) (R1=1500ohm) VL Vbat (-46V) 12/28 STLC3085 3.2.3 Functional description Active 3.2.3.1 DC characteristics & supervision When this mode is selected the STLC3085 provides both DC feeding and AC transmission. The STLC3085 feeds the line with a constant current fixed by RLIM (20mA to 25mA range). The on-hook voltage is typically 38V allowing on-hook transmission; the self generated Vbat is 46V typ. If the loop resistance is very high and the line current cannot reach the programmed constant current feed value, the STLC3085 behaves like a 38V voltage source with a series impedance equal to the protection resistors 2xRp (typ. 2x50Ω). Figure 4 shows the typical DC characteristic in ACTIVE mode. The line status (on/off hook) is monitored by the SLIC’S supervision circuit. The off-hook threshold can be programmed via the external resistor RTH in the range from 5mA to 9mA. Independently on the programmed constant current value, the TIP and RING buffers have a current source capability limited to 65mA typ. Figure 4. DC characteristic in ACTIVE mode IL Ilim (20 to 25mA) 2Rp VL 10V Vbat (-46V) Moreover the power available at Vbat is controlled by the DC/DC converter that limits the peak current drawn from the Vpos supply. The maximum allowed current peak is set by RSENSE resistor. 3.2.3.2 AC characteristics The SLIC provides the standard SLIC transmission functions: Once in active mode the SLIC can operate with two different Tx, Rx Gain. Setting properly by the Gain set control bit (see Table 7). Table 7. ● Gain Set in Active Mode Gain set 4 to 2 wire Gain 2 to 4 wire Gain Impedance Synthesis Scale Factor 0 0dB -6dB x 50 1 +6dB -12dB x 25 Input impedance synthesis: can be real or complex and is set by a scaled (x50 or x25) external ZAC impedance. 13/28 STLC3085 Functional description ● Transmit and receive: The AC signal present on the 2W port (TIP/RING) is transferred to the TX output with a -6dB or -12dB gain and from the RX input to the 2W port with a 0dB or +6dB gain. ● 2 to 4 wire conversion: The balance impedance can be real or complex, the proper cancellation is obtained by means of two external impedance ZA and ZB Once in Active mode (D1=1) the SLIC can operate in different states setting properly D0 and D2 control bits (see also Table 8). Table 8. SLIC states in ACTIVE mode D0 D1 D2 Operating Mode 0 1 0 Active Normal Polarity 0 1 1 Active Reverse Polarity 3.2.3.3 Polarity reversal The D2 bit controls the line polarity, the transition between the two polarities is performed in a "soft" way. This means that the TIP and RING wire exchange their polarities following a ramp transition (see Figure 5). The transition time is controlled by an external capacitor CREV. This capacitor is also setting the shape of the ringing trapezoidal waveform. When the control pins set battery reversal the line polarity is reversed with a proper transition time set via an external capacitor (CREV). Figure 5. TIP/RING typical transition from Direct to Reverse Polarity GND TIP 4V typ. 38 V typ ON-HOOK dV/dT set by CREV RING 3.2.4 Ringing When this mode is selected STLC3085 self generate an higher negative battery (-64V typ.) in order to allow a balanced ringing signal of typically 59Vpeak. In this condition both the DC and AC feedback loop are disabled and the SLIC line drivers operate as voltage buffers. The ring waveform is obtained toggling the D2 control bit at the desired ring frequency. This bit in fact controls the line polarity (0=direct; 1= reverse). As in the ACTIVE mode the line voltage transition is performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see Figure 6). The shaping is defined by the CREV external capacitor. 14/28 STLC3085 Figure 6. Functional description TIP/RING typical ringing waveform GND TIP 2.5V typ. 59V typ. dV/dT set by CREV RING VBAT 2.5V typ. Selecting the proper capacitor value it is possible to get different crest factor values. The following table shows the crest factor values obtained with a 20Hz and 25Hz ring frequency and with 1REN. These value are valid either with European or USA specification: Table 9. CREV CREST FACTOR @20Hz CREST FACTOR @25Hz 22nF 1.2 1.26 27nF 1.25 1.32 33nF 1.33 Not significant (1) (1) Distorsion already less than 10%. The ring trip detection is performed sensing the variation of the AC line impedance from on hook (relatively high) to off-hook (low). This particular ring trip method allows to operate without DC offset superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. It should be noted that such a method is optimised for operation on short loop applications and may not operate properly in presence of long loop applications (> 500Ω). Once ring trip is detected, the DET output is activated (logic level low), at this point the card controller or a simple logic circuit should stop the D2 toggling in order to effectively disconnect the ring signal and then set the STLC3085 in the proper operating mode (normally ACTIVE). 3.2.4.1 Ring level in presence of more telephone in parallel As already mentioned above the maximum current that can be drawn from the Vpos supply is controlled and limited via the external RSENSE. This will limit also the power available at the self generated negative battery. If for any reason the ringer load is too low the self generated battery will drop in order to keep the power consumption to the fixed limit and therefore also the ring voltage level will be reduced. In the typical Buck Boost configuration with RSENSE = 130mΩ the peak current from Vpos is limited to about 770mA, which correspond to an average current of 600mA max. In this condition the STLC3085 can drive up to 2REN with a ring frequency fr=25Hz (1REN = 1800Ω + 1.0µF, European standard). In Fly-Back configuration the value of RSENSE = 220mΩ guarantees match both European and USA standards. 15/28 STLC3085 Functional description 3.2.5 Layout recommendation A properly designed PCB layout is a basic issue to guarantee a correct behaviour and good noise performances. Particular care must be taken on the ground connection and in this case the star configuration allows surely to avoid possible problems (see Application Diagram Figure 7 and Figure 8). The ground of the power supply (VPOS) has to be connected to the center of the star, let’s call this point SYSTEM-GND. This point should show a resistance as low as possible, that means it should be a ground plane. In particular to avoid noise problems the layout should prevent any coupling between the DC/ DC converter components and analog pins that are referred to AGND (ex: RD, IREF, RTH, RLIM, VF). As a first reccomendation the components CV, L, T1, D1, CVPOS, RSENSE should be kept as close as possible to each other and isolated from the other components. Additional improvements can be obtained: 3.2.6 ● decoupling the center of the star from the analog ground of STLC3085 using small chokes. ● adding a capacitor in the range of 100nF between VPOS and AGND in order to filter the switch frequency on VPOS. External components list In order to properly define the external components value the following system parameters have to be defined: Table 10. Name ● The AC input impedance shown by the SLIC at the line terminals "Zs" to which the return loss measurement is referred. It can be real (typ. 600Ω) or complex. ● The AC balance impedance, it is the equivalent impedance of the line "Zl" used for evaluation of the trans-hybrid loss performances (2/4 wire conversion). It is usually a complex impedance. ● The value of the two protection resistors Rp in series with the line termination. ● The slope of the ringing waveform "∆VTR/∆T ". ● The value of the constant current limit current "Ilim". ● The value of the off-hook current threshold "ITH". ● The value of the ring trip rectified average threshold current "IRTH". ● The value of the required self generated negative battery "VBATR" in ring mode (max value is 64V). This value can be obtained from the desired ring peak level + 5V. ● The value of the maximum current peak drawn from Vpos "IPK". External Components Function Formula Typ. Value BUCKBOOST CONFIGURATION RREF Bias setting current RREF = 1.3/Ibias Ibias = 50µA CSVR Negative Battery Filter CSVR = 1/(2π ⋅ fp ⋅ 1.8MΩ) fp = 50Hz 16/28 26kΩ 1% 1.5nF 10% 100V STLC3085 Table 10. Name RD CAC RP Functional description External Components (continued) Function Ring Trip threshold setting resistor Formula RD = 100/IRTH 2KΩ < RD < 5KΩ Line protection resistor Rp > 30Ω RLIM Current limiting programming RLIM = 1300/Ilim 32.5kΩ < RLIM < 65kΩ RTH Off-hook threshold programming RTH = 290/ITH (ACTIVE mode) 27kΩ < RTH < 52kΩ Reverse polarity transition time programming RDD Pull up resistors CVCC 4.12kΩ 1% @ IRTH = 24mA 22µF 20% 15V @ RD = 4.12kΩ AC/DC split capacitance CREV Typ. Value CREV = ((1/3750) · ∆T/∆VTR) 50Ω 1% 52.3kΩ 1% @ Ilim = 25mA 32.4kΩ 1% @ITH = 9mA 22nF 10% 10V @ 12V/ms 100kΩ Internally supply filter capacitor 100nF 20% 10V Positive supply filter capacitor CVpos(1) with low impedance for switch mode power supply 100µF CV(2) Battery supply filter capacitor with low impedance for switch mode power supply 100µF 20% 100V CVB High frequency noise filter 470nF 20% 100V CRD(3) High frequency noise filter 100nF 10% 15V Q1 DC/DC converter switch P ch. MOS transistor RDS(ON)≤1.2Ω,VDS = -100V Total gate charge=20nC max. with VGS=4.5V and VDS=1V ID>500mA D1 DC/DC converter series diode Vr > 100V, tRR ≤ 50ns SMBYW01-200 or equivalent RSENSE DC/DC converter peak current limiting RSENSE = 100mV/IPK 130mΩ @IPK = 770mA RF1 Negative battery programming level 250KΩ<RF1<270KΩ 270kΩ 1% @ VBATR = -64V RF2 Negative battery programming level L(4) DC/DC converter inductor Possible choiches: IRF9510 or IRF9520 or IRF9120 or equivalent 9.1kΩ 1% DC resistance ≤ 0.1Ω L=100µH SUMIDA CDRH125 or equivalent FLY-BACK CONFIGURATION RREF Bias setting current RREF = 1.3/Ibias; Ibias = 50µA 26kΩ 1% 17/28 STLC3085 Functional description Table 10. Name CSVR RD CAC RP External Components (continued) Function Negative Battery Filter Ring Trip threshold setting resistor Formula CSVR = 1/(2π ⋅ fp ⋅ 1.8MΩ) fp = 50Hz RD = 100/IRTH 2KΩ < RD < 5KΩ Line protection resistor Rp > 30Ω RLIM Current limiting programming RLIM = 1300/Ilim 52.3kΩ < RLIM < 65kΩ RTH Off-hook threshold programming RTH = 290/ITH (ACTIVE mode) 27kΩ < RTH < 52kΩ Reverse polarity transition time programming RDD Pull up resistors CVCC 1.5nF 10% 100V 4.12kΩ 1% @ IRTH = 24mA 22µF 20% 15V @ RD = 4.12kΩ AC/DC split capacitance CREV Typ. Value 50Ω 1% CREV = ((1/3750) · ∆T/∆VTR) 52.3kΩ 1% @ Ilim = 25mA 32.4kΩ 1% @ITH = 9mA 22nF 10% 10V @ 12V/ms 100kΩ Internally supply filter capacitor 100nF 20% 10V Positive supply filter capacitor CVpos(1) with low impedance for switch mode power supply 100µF CV(2) Battery supply filter capacitor with low impedance for switch mode power supply 100µF 20% 100V CVB High frequency noise filter 470nF 20% 100V CRD(3) High frequency noise filter 100nF 10% 15V Fly-Back compensation capacitor 2.2nF, 20% CSF Sense Filter capacitor 120pF, 20% RSF Sense Filter resistor CZ 1kΩ RSENSE DC/DC converter peak current limiting RSENSE = 375mV/IPK Q1 DC/DC converter switch Nchan MOS transistor RDS(ON)≤0.05Ω,VDSS = 30V VDG=30V, ID = 6.5A Low threshold drive D1 DC/DC converter series diode Vr > 350V, tRR ≤ 80ns T1 DC/DC Converter transformer Fly-Back transformer 4W, Turns Ratio 1:16 fro VPOS range from 4.5V to 8.5V Tyco COEV MAGNETICS MGPWG-00007 Formula Typ. Value Name 18/28 Function 220mΩ @IPK = 1.7A STN4NF03L or equivalent SMBYTW01-400 or equivalent STLC3085 Table 10. Functional description External Components (continued) T1 DC/DC Converter transformer Fly-Back transformer 4W, Turns Ratio 1:8 fro VPOS range from 8.5V to 12V RF1 Negative battery programming level 250KΩ<RF1<270KΩ RF2 Negative battery programming level Tyco COEV MAGNETICS MGPWG-00008 270kΩ 1% @ VBATR = -64V 9.1kΩ 1% @Gain Set = 0 RS Protection resistance image RS = 50 ⋅ (2Rp) ZAC Two wire AC impedance ZAC = 50 ⋅ (Zs - 2Rp) 25kΩ 1% @ Zs = 600Ω ZA(5) SLIC impedance balancing network ZA = 50 ⋅ Zs 30kΩ 1% @ Zs = 600Ω ZB(5) Line impedance balancing network ZB = 50 ⋅ Zl 30kΩ 1% @ Zl = 600Ω CCOMP AC feedback loop compensation CH Trans-Hybrid Loss frequency compensation fo = 250kHz CCOMP = 1/(2π⋅fo⋅100⋅(RP)) 5kΩ @ Rp = 50Ω 120pF 10% 10V @ Rp = 50Ω CH = CCOMP 120pF 10% 10V @Gain Set = 1 RS Protection resistance image RS = 25 ⋅ (2Rp) ZAC Two wire AC impedance ZAC = 25 ⋅ (Zs - 2Rp) ZA(5) SLIC impedance balancing network ZA = 25 ⋅ Zs 15kΩ 1% @ Zs = 600Ω ZB(5) Line impedance balancing network ZB = 25 ⋅ Zl 15kΩ 1% @ ZI = 600Ω CCOMP AC feedback loop compensation CH Trans-Hybrid Loss frequency compensation fo = 250kHz CCOMP = 2/(2π⋅fo⋅100⋅(RP)) 2.55kΩ @ Rp = 50Ω 12.5kΩ 1% @ Zs = 600Ω 220pF 10% 10VL @ Rp = 50Ω CH = CCOMP 220pF 10% 10V (1) CVpos should be defined depending on the power supply current capability and maximum allowable ripple. (2) For low ripple application use 2x47 µF in parallel. (3) Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input). (4) For high efficiency in HI-Z mode coil resistance @125kHz must be < 3Ω. (5) In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|. 19/28 STLC3085 Applications diagram 4 Applications diagram Figure 7. Application Diagram with N-Channel RX TX RX TX VPOS CVPOS CVCC T1 RS AGND BGND CVCC VPOS RS GATE ZAC CCOMP N-ch RSF RSENSE ZAC1 ZAC RSENSE CSF ZA D1 VBAT ZB CH Q1 ZB VDD CVB RF1 CZ RF2 VF GAIN SET RDD CV CZ STLC3085 CLK CLK RP CONTROL INTERFACE TIP DET DET D1 D1 D2 D2 PD PD TIP RP D0 D0 RING RING CSVR CREV CREV 8RES CSVR RTH 9RES RLIM IREF 10RES RREF 12RES 11RES ILTF CAC RLIM RTH RD RD CRD D04TL626 AGND CAC BGND SYSTEM GND SUGGESTED GROUND LAY-OUT Figure 8. PGND Application Diagram with P-Channel VPOS CVPOS CVCC RS RX TX RX TX AGND BGND CVCC VPOS RS P-ch GATE D1 ZAC1 VBAT ZAC ZA RF1 CVB ZB CH Q1 RSENSE ZAC CCOMP RSENSE CV VF ZB RF2 VDD CLK RDD RP RP RING DET DET D0 D0 D1 D1 D2 D2 PD PD CREV 9RES RLIM IREF RREF 11RES ILTF CAC SUGGESTED GROUND LAY-OUT 20/28 PGND CAC RLIM RTH RD RD AGND BGND CSVR CREV RTH 10RES SYSTEM GND RING CSVR 8RES 12RES TIP TIP STLC3085 CONTROL INTERFACE CLK GAIN SET CRD D01TL494A L STLC3085 STLC3085 test circuits Appendix A STLC3085 test circuits Referring to the application diagram shown in Figure 11 and using as external components the Typ. Values specified in the "External Components" Table 10 find below the proper configuration for each measurement. All measurements requiring DC current termination should be performed using "Wandel & Goltermann DC Loop Holding Circuit GH-1" or equivalent. Figure 9. 2W Return Loss 2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs) W&G GH1 Zref TX TIP 600ohm 100 F Vs STLC3085 application circuit 100mA DC max 1Kohm E Zin = 100K 200 to 6kHz 100 F 1Kohm RX RING Figure 10. THL Trans Hybrid Loss THL = 20Log|Vrx/Vtx| W&G GH1 TIP TX 100 F 600ohm Vtx STLC3085 application circuit 100mA DC max Zin = 100K 200 to 6kHz 100 F RING RX Vrx 21/28 STLC3085 STLC3085 test circuits Figure 11. G24 Transmit Gain G24 = 20Log|2Vtx/E| W&G GH1 TIP TX 100 F Vtx STLC3085 application circuit 100mA DC max 600ohm Zin = 100K 200 to 6kHz E 100 F RX RING Figure 12. G42 Receive Gain G42 = 20Log|VI/Vrx| W&G GH1 TIP TX 100 F Vl 600ohm STLC3085 application circuit 100mA DC max Zin = 100K 200 to 6kHz 100 F RX RING Vrx Figure 13. PSRRC Power supply rejection Vpos to 2W port PSSRC = 20Log|Vn/Vl| W&G GH1 TIP TX 100 F Vl 600ohm STLC3085 application circuit 100mA DC max Zin = 100K 200 to 6kHz 100 F RING ~ 22/28 RX VPOS Vn STLC3085 STLC3085 test circuits Figure 14. L/T Longitudinal to Transversal Conversion L/T = 20Log|Vcm/Vl| 300ohm W&G GH1 100 F TIP TX 100 F Impedance matching better than 0.1% Vcm 100mA DC max STLC3085 application circuit Vl Zin = 100K 200 to 6kHz 100 F RX RING 300ohm 100 F Figure 15. T/L Transversal to Longitudinal Conversion T/L = 20Log|Vrx/Vcm| 300ohm 100 F W&G GH1 TIP TX 100 F STLC3085 application circuit 100mA DC max Impedance matching better than 0.1% 600ohm Vcm Zin = 100K 200 to 6kHz 100 F RX RING 300ohm Vrx 100 F Figure 16. V2Wp and W4Wp: Idle channel psophometric noise at line and TX. V2Wp = 20Log|Vl/0.774l|; V4Wp = 20Log|Vtx/0.774l| W&G GH1 TIP TX 100 F 600ohm Vl psophometric filtered Vtx psophometric filtered STLC3085 application circuit 100mA DC max Zin = 100K 200 to 6kHz 100 F RING RX 23/28 STLC3085 STLC3085 overvoltage protection Appendix B STLC3085 overvoltage protection Figure 17. Simplified configuration for indoor overvoltage protection STPR120A BGND STLC3085N 2x SM6T39A TIP RING RP1 RP2 TIP RP1 RP2 RING VBAT STPR120A RP1 = 30ohm: RP2 =Fuse or PTC > 20ohm Figure 18. Standard overvoltage protection configuration for K20 compliance BGND STLC3085N RP1 2x SM6T39A TIP RP2 TIP RP2 RING LCP1521S RING RP1 VBAT RP1 = 30ohm: RP2 =Fuse or PTC > 20ohm 24/28 STLC3085 Typical state diagram for STLC3085 operation Appendix C Typical state diagram for STLC3085 operation Figure 19. Typical state diagram for STLC3085 operation Normally used for On Hook Transmission Tj>Tth PD=0, D0=D1=0 Active On Hook Power Down Ring Pause D0=0, D1=1, D2=0 Ring Burst Ring Burst D0=1, D1=0, D2=0/1 Ringing PD=1, D0=D1=0 On Hook Detection for T>Tref HI-Z Feeding Ring Trip Detection Active Off Hook On Hook Condition Off Hook Detection D0=0, D1=1, D2=0 Off Hook Detection Note: all state transitions are under the microprocessor control. 25/28 STLC3085 Package information 5 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 20. TQFP44 (10x10x1.4mm) Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 1.60 A1 0.05 A2 1.35 1.40 0.37 B 0.30 C 0.09 D 11.80 D1 9.80 D3 0.063 0.15 0.002 1.45 0.053 0.055 0.015 0.45 0.012 0.20 0.004 12.00 12.20 0.464 10.00 10.20 0.386 8.00 0.006 0.057 0.018 0.008 0.472 0.480 0.394 0.401 0.315 E 11.80 12.00 12.20 0.464 0.472 0.480 E1 9.80 10.00 10.20 0.386 0.394 0.401 E3 8.00 e 0.80 L 0.45 0.60 L1 0.315 0.031 0.75 0.018 1.00 k OUTLINE AND MECHANICAL DATA MAX. 0.024 0.030 TQFP44 (10 x 10 x 1.4mm) 0.039 0˚(min.), 3.5˚(typ.), 7˚(max.) D D1 A A2 A1 23 33 34 22 0.10mm .004 B E B E1 Seating Plane 12 44 11 1 C L e K TQFP4410 0076922 D 26/28 STLC3085 6 Revision history Revision history Table 11.Document revision history Date Revision 15-Feb-2006 1 Changes Initial release. 27/28 STLC3085 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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