TI CDC351

CDC351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995
D
D
D
D
D
D
D
D
D
DB OR DW PACKAGE
(TOP VIEW)
Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
Operates at 3.3-V VCC
LVTTL-Compatible Inputs and Outputs
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With 3.3-V
VCC)
Distributes One Clock Input to Ten Outputs
Distributed VCC and Ground Pins Reduce
Switching Noise
High-Drive Outputs (– 32-mA IOH,
32-mA IOL )
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages
GND
Y10
VCC
Y9
OE
A
P0
P1
Y8
VCC
Y7
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
GND
Y1
VCC
Y2
GND
Y3
Y4
GND
Y5
VCC
Y6
GND
description
The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with
minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance
state. The CDC351 operates at nominal 3.3-V VCC.
The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure
that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended
for customer use and should be connected to GND.
The CDC351 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
A
OE
OUTPUTS
Yn
L
H
Z
H
H
Z
L
L
L
H
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙΒ is a trademark of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CDC351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995
logic symbol†
5
EN
OE
23
21
19
18
16
6
A
14
11
9
4
2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
5
23
21
19
18
A
Y2
Y3
Y4
6
16
7 8
P0 P1
14
11
9
4
2
2
Y1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Y5
Y6
Y7
Y8
Y9
Y10
CDC351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state,
VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 3.6 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . 0.65 W
DW package . . . . . . . . . . . . . . . . . 1.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65 to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
MIN
MAX
3.6
UNIT
VCC
VIH
Supply voltage
3
High-level input voltage
2
VIL
VI
Low-level input voltage
5.5
V
IOH
IOL
High-level output current
– 32
mA
Low-level output current
32
mA
fclock
TA
Input clock frequency
100
MHz
70
°C
V
0.8
Input voltage
0
Operating free-air temperature
0
V
V
NOTE 3: Unused pins (input or I/O) must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 3 V,
VCC = 3 V,
II = –18 mA
IOH = – 32 mA
VOL
II
IO‡
VCC = 3 V,
VCC = 3.6 V,
IOL = 32 mA
VI = VCC or GND
VCC = 3.6 V,
VCC = 3.6 V,
VO = 2.5 V
VO = 3 V or 0
VCC = 3.6
3 6 V,
V
VI = VCC or GND
IO = 0
0,
VI = VCC or GND,
VCC = 3.3 V,
IOZ
MIN
TYP
Ci
V
V
0.5
–15
±1
µA
mA
± 10
µA
0.3
25
Outputs disabled
0.3
f = 10 MHz
• DALLAS, TEXAS 75265
V
–150
Outputs low
Co
VO = VCC or GND,
VCC = 3.3 V,
f = 10 MHz
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
POST OFFICE BOX 655303
UNIT
–1.2
2
Outputs high
ICC
MAX
mA
4
pF
6
pF
3
CDC351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995
switching characteristics, CL = 50 pF (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
tsk(o)
A
tsk(p)
VCC = 3.3 V,
TA = 25°C
MIN
TYP
MAX
VCC = 3 V to 3.6 V,
TA = 0°C to 70°C
MIN
MAX
UNIT
3.2
3.7
4.2
3
3.5
4
1.8
3.8
5.5
1.3
5.9
1.8
3.8
5.5
1.3
5.9
1.8
3.9
5.9
1.7
6.3
1.8
4.2
5.9
1.7
6.4
Y
0.3
0.5
0.5
ns
A
Y
0.2
0.8
0.8
ns
tsk(pr)
A
Y
1
ns
tr
tf
A
Y
1.5
ns
A
Y
1.5
ns
ns
1
ns
ns
switching characteristics temperature and VCC coefficients over recommended operating free-air
temperature and VCC range (see Note 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
∝tPLH(T)
Average temperature coefficient of low to high
propagation delay
A
Y
65†
ps/10°C
∝tPHL(T)
Average temperature coefficient of high to low
propagation delay
A
Y
45†
ps/10°C
∝tPLH(VCC)
Average VCC coefficient of low to high propagation
delay
A
Y
–140‡
ps/
100 mV
∝tPHL(VCC)
Average VCC coefficient of high to low propagation
delay
A
Y
–120‡
ps/
100 mV
† ∝tPLH(T) and ∝tPHL(T) are virtually independent of VCC.
‡ ∝tPLH(VCC) and ∝tPHL(VCC) are virtually independent of temperature.
NOTE 4: These data were extracted from characterization material and are not tested at the factory.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
6V
S1
500 Ω
From Output
Under Test
TEST
tPLH /tPHL
tPLZ /tPZL
tPHZ /tPZH
Open
GND
CL = 50 pF
(see Note A)
S1
Open
6V
GND
500 Ω
tw
LOAD CIRCUIT
3V
Input
3V
1.5 V
1.5 V
0V
1.5 V
Timing Input
0V
tsu
VOLTAGE WAVEFORMS
th
3V
1.5 V
Data Input
1.5 V
0V
VOLTAGE WAVEFORMS
1.5 V
0V
tPHL
2V
0.8 V
tr
1.5 V
0V
tPLZ
1.5 V
tPLH
Output
1.5 V
tPZL
3V
Input
3V
Output
Control
(low-level
enabling)
1.5 V
VOH
2V
0.8 V
VOL
tf
3V
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
tPZH
VOLTAGE WAVEFORMS
VOL + 0.3 V
VOL
tPHZ
VOH
1.5 V
VOH – 0.3 V
≈0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
CDC351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
A
Y1
tPHL1
tPLH1
tPHL2
tPLH2
tPHL3
tPLH3
tPHL4
tPLH4
tPHL5
tPLH5
tPHL6
tPLH6
tPHL7
tPLH7
tPHL8
tPLH8
tPHL9
tPLH9
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
tPHL10
tPLH10
NOTES: A. Output skew, tsk(o), is calculated as the greater of:
– The difference between the fastest and slowest of tPLHn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
– The difference between the fastest and slowest of tPHLn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
B. Pulse skew, tsk(p), is calculated as the greater of | tPLHn – tPHLn | (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10).
C. Process skew, tsk(pr), is calculated as the greater of:
– The difference between the fastest and slowest of tPLHn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under identical
operating conditions
– The difference between the fastest and slowest of tPHLn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under identical
operating conditions
Figure 2. Waveforms for Calculation of tsk(o), tsk(p), tsk(pr)
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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