m m The mA733M is obsolete and no longer supplied. SLFS027B − NOVEMBER 1970 − REVISED MAY 2004 D 200-MHz Bandwidth D 250-kΩ Input Resistance D Selectable Nominal Amplification of 10, D mA733C . . . D, N, OR NS PACKAGE mA733M . . . J PACKAGE (TOP VIEW) IN+ NC GAIN ADJ 2A GAIN ADJ 1A VCC− NC OUT+ 1 14 2 13 3 4 12 11 5 10 6 9 7 8 100, or 400 No Frequency Compensation Required mA733M . . . U PACKAGE (TOP VIEW) IN+ GAIN ADJ 2A GAIN ADJ 1A VCC − OUT+ IN− NC GAIN ADJ 2B GAIN ADJ 1B VCC+ NC OUT− 1 10 2 9 3 8 4 7 5 6 IN − GAIN ADJ 2B GAIN ADJ 1B VCC+ OUT− NC No internal connection description/ordering information The µA733 is a monolithic two-stage video amplifier with differential inputs and differential outputs. Internal series-shunt feedback provides wide bandwidth, low phase distortion, and excellent gain stability. Emitter-follower outputs enable the device to drive capacitive loads, and all stages are current-source biased to obtain high common-mode and supply-voltage rejection ratios. Fixed differential amplification of 10 V/ V, 100 V/ V, or 400 V/ V may be selected without external components, or amplification may be adjusted from 10 V/ V to 400 V/ V by the use of a single external resistor connected between 1A and 1B. No external frequency-compensating components are required for any gain option. The device is particularly useful in magnetic-tape or disc-file systems using phase or NRZ encoding and in high-speed thin-film or plated-wire memories. Other applications include general-purpose video and pulse amplifiers where wide bandwidth, low phase shift, and excellent gain stability are required. The µA733C is characterized for operation from 0°C to 70°C; the µA733M is characterized for operation over the full military temperature range of −55°C to 125°C. ORDERING INFORMATION P-DIP (N) 0°C to 70°C ORDERABLE PART NUMBER PACKAGE† TA SOIC (D) Tube of 25 UA733CN Tube of 50 UA733CD Reel of 2500 UA733CDR TOP-SIDE MARKING UA733CN UA733C SOP (NS) Reel of 2000 UA733CNSR UA733 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !"# $% $ ! ! & ' $$ ()% $ !* $ #) #$ * ## !% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 m m The mA733M is obsolete and no longer supplied. SLFS027B − NOVEMBER 1970 − REVISED MAY 2004 symbol GAIN ADJ 1A GAIN ADJ 2A IN + OUT+ + _ IN − OUT− GAIN ADJ 1B GAIN ADJ 2B schematic VCC+ 2.4 kΩ 2.4 kΩ 10 kΩ 1.1 kΩ 1.1 kΩ OUT+ IN + 7 kΩ IN − 1A GAIN ADJ 50 Ω 7 kΩ 1B OUT − GAIN ADJ 50 Ω 2B 2A 590 Ω 590 Ω 300 Ω 1.4 kΩ 300 Ω 400 Ω 400 Ω VCC − Component values shown are nominal. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 m m The mA733M is obsolete and no longer supplied. SLFS027B − NOVEMBER 1970 − REVISED MAY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† mA733C mA733M UNIT Supply voltage VCC+ (see Note 1) 8 8 V Supply voltage VCC− (see Note 1) −8 −8 V Differential input voltage ±5 ±5 V Common-mode input voltage ±6 ±6 V Output current 10 10 mA Continuous total power dissipation See Dissipation Rating Table Package thermal impedance, qJA (see Notes 2 and 3) D package 86 N package 80 NS package °C/W C/W 76 Maximum junction temperature, TJ °C 150 Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds J or U package 300 °C Storage temperature range, Tstg − 65 to 150 − 65 to 150 °C † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential input voltages, are with respect to the midpoint between VCC+ and VCC–. 2. Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR DERATE ABOVE TA TA = 70°C POWER RATING TA = 125°C POWER RATING J (µA733M) 500 mW 11.0 mW/°C 104°C 500 mW 269 mW POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 m m The mA733M is obsolete and no longer supplied. SLFS027B − NOVEMBER 1970 − REVISED MAY 2004 electrical characteristics, VCC± = ±6 V, TA = 25°C PARAMETER AVD BW Large-signal differential voltage amplification Bandwidth FIGURE 1 2 TEST CONDITIONS VOD = 1 V RS = 50 Ω mA733C mA733M GAIN OPTION† MIN TYP MAX MIN TYP MAX 1 250 400 600 300 400 500 2 80 100 120 90 100 110 3 8 10 12 9 10 11 1 50 50 2 90 90 3 200 200 UNIT V/ V MHz IIO Input offset current Any 0.4 5 0.4 3 µA IIB Input bias current Any 9 30 9 20 µA VICR Common-mode input voltage range 1 Any ±1 VOC Common-mode output voltage 1 Any 2.4 VOO Output offset voltage 1 VOPP Maximum peakto-peak output voltage swing 1 2.9 3.4 1 0.6 2&3 0.35 Any 3 4.7 10 24 1 ri Input resistance 3 VOD ≤ 1 V 2 Output resistance Ci Input capacitance 3 CMRR Common-mode rejection ration 4 kSVR Supply voltage rejection ratio (∆VCC/(∆VIO) Vn tpd VOD ≤ 1 V VIC = ±1 V, f ≤ 100 kHz 2 2 2 1 ∆VCC± = ±0.5 V 2 Broadband equivalent input noise voltage 5 BW = 1 kHz to 10 MHz Propagation delay time 2 Rise time Isink(max) Maximum output sink current ICC Supply current 2 60 1.5 0.6 1.5 1.5 0.35 1 3 4.7 20 24 V V V 4 kΩ 250 20 20 Ω 2 2 pF 86 50 60 86 RS = 50 Ω, Output voltage step = 1 V 1 7.5 2 6.0 3 3.6 RS = 50 Ω, Output voltage step = 1 V 1 10.5 2 4.5 3 2.5 Any 2.5 Any • DALLAS, TEXAS 75265 70 70 12 POST OFFICE BOX 655303 3.4 70 † The gain option is selected as follows: Gain Option 1: Gain-adjust pin 1A is connected to pin 1B, and pins 2A and 2B are open. Gain Option 2: Gain-adjust pin 1A and pin 1B are open, pin 2A is connected to pin 2B. Gain Option 3: All four gain-adjust pins are open. 4 2.9 250 Any No load, No signal V dB VIC = ±1 V, f = 5 MHz tr 2.4 4 3 ro ±1 50 dB 12 µV 7.5 10 6.0 10 ns 10 ns 3.6 10.5 12 4.5 2.5 3.6 16 70 2.5 24 3.6 16 mA 24 mA m m The mA733M is obsolete and no longer supplied. SLFS027B − NOVEMBER 1970 − REVISED MAY 2004 electrical characteristics, VCC± = ±6 V, TA = 0°C to 70°C for mA733C, − 55°C to 125°C for mA733M PARAMETER AVD IIO IIB Large-signal differential voltage amplification FIGURE 1 TEST CONDITIONS mA733C mA733M GAIN OPTION† MIN MAX MIN MAX 1 250 600 200 600 2 80 120 80 120 3 8 12 8 12 VOD = 1 V UNIT V/ V Input offset current Any 6 5 µA Input bias current Any 40 40 µA VICR Common-mode input voltage range 1 VOO Output offset voltage 1 VOPP Maximum peak-to-peak output voltage swing 1 ri Input resistance 3 CMRR Common-mode rejection ratio 4 kSVR Supply voltage rejection ratio (∆VCC /(∆VIO) 1 Isink(max) Maximum output sink current ICC Supply current Any ±1 ±1 V 1 1.5 1.5 2&3 1.5 1.2 Any V 2.8 2.5 V VOD ≤ 1 V VIC = +1 V, f ≤ 100 kHz 2 8 8 kΩ 2 50 50 dB ∆VCC± = ± 0.5 V 2 50 50 dB Any 2.5 2.2 mA No load, No signal Any 27 27 mA † The gain option is selected as follows: Gain Option 1: Gain-adjust pin 1A is connected to pin 1B, and pins 2A and 2B are open. Gain Option 2: Gain-adjust pin 1A and pin 1B are open, pin 2A is connected to pin 2B. Gain Option 3: All four gain-adjust pins are open. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 m m The mA733M is obsolete and no longer supplied. SLFS027B − NOVEMBER 1970 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION test circuits 0.2 µF + + VOD VID VID 2 kΩ 0.2 µF − − 50 Ω 50 Ω 50 Ω 50 Ω 1 kΩ 1 kΩ Figure 2 Figure 1 0.2 µF 50 Ω + + VOD 0.2 µF 50 Ω 2 kΩ − − VIC 1 kΩ Figure 3 1 kΩ Figure 4 2B 1B 0.2 µF + 0.2 µF + − VOD 2 kΩ − 50 Ω 50 Ω 1 kΩ Radj 2A 1A VOLTAGE AMPLIFICATION ADJUSTMENT Figure 5 6 Figure 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 kΩ m m The mA733M is obsolete and no longer supplied. SLFS027B − NOVEMBER 1970 − REVISED MAY 2004 TYPICAL CHARACTERISTICS PHASE SHIFT vs FREQUENCY PHASE SHIFT vs FREQUENCY 5 50 VCC ± = ± 6 V TA = 25°C 0 − 50 Phase Shift − Degrees Phase Shift − Degrees VCC ± = ± 6 V TA = 25°C 0 −5 GAIN 2 −10 −15 GAIN 2 −100 −150 −200 −250 −300 −350 −400 −20 0 1 2 3 4 5 6 7 8 9 −450 10 1 4 f − Frequency − MHz 1.2 VCC ± = ± 6 V GAIN 1 1.1 mA733C GAIN 2 GAIN 3 1.0 GAIN 2 GAIN 3 0.9 GAIN 1 − 50 − 25 0 25 50 75 TA − Free-Air Temperature − °C 100 125 Voltage Amplification Relative to Value at VCC +_ = +_ 6 V VOLTAGE AMPLIFICATION (SINGLE-ENDED OR DIFFERENTIAL) vs TEMPERATURE Voltage Amplification Relative to Value at TA = 25o C 40 100 400 Figure 8 Figure 7 0.8 −75 10 f − Frequency − MHz VOLTAGE AMPLIFICATION (SINGLE-ENDED OR DIFFERENTIAL) vs SUPPLY VOLTAGE 1.4 TA = 25°C 1.2 GAIN 3 1.0 0.8 GAIN 2 0.6 GAIN 1 0.4 3 Figure 9 4 5 6 7 |VCC±| − Supply Voltage − V 8 Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 m m The mA733M is obsolete and no longer supplied. SLFS027B − NOVEMBER 1970 − REVISED MAY 2004 TYPICAL CHARACTERISTICS SINGLE-ENDED VOLTAGE AMPLIFICATION vs FREQUENCY DIFFERENTIAL VOLTAGE AMPLIFICATION vs RESISTANCE BETWEEN G1A AND G1B VCC ± = ± 6 V VOD = 1 V TA = 25°C See Figure 6 700 AVD − Differential Voltage Amplification AVS − Single-ended Voltage Amplification − dB 1000 400 200 100 70 40 20 10 50 GAIN 1 40 GAIN 2 30 20 GAIN 3 10 VCC ± = ± 6 V TA = 25°C 0 10 40 100 400 1k 4k 1 10 k 4 Figure 11 24 No Load No Signal TA = 25°C 20 16 I CC − Supply Current − mA I CC − Supply Current − mA 18 14 mA733C 12 10 8 6 VCC ± = ± 6 V No Load No Signal − 50 − 25 16 12 8 4 0 25 50 75 100 125 TA − Free-Air Temperature − °C 0 3 4 5 Figure 14 POST OFFICE BOX 655303 6 7 |VCC±| − Supply Voltage − V Figure 13 8 400 SUPPLY CURRENT vs SUPPLY VOLTAGE 20 0 −75 100 Figure 12 SUPPLY CURRENT vs FREE-AIR TEMPERATURE 2 40 f − Frequency − MHz Radj − Resistance Between G1A and G1B − Ω 4 10 • DALLAS, TEXAS 75265 8 m m The mA733M is obsolete and no longer supplied. SLFS027B − NOVEMBER 1970 − REVISED MAY 2004 TYPICAL CHARACTERISTICS 5 VCC ± = ± 6 V TA = 25°C 4 3 2 1 0 10 40 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE VOPP − Maximum Peak-to-Peak Output Voltage − V VOPP − Maximum Peak-to-Peak Output Voltage − V MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs LOAD RESISTANCE 100 400 1k RL − Load Resistance − Ω 4k 8 TA = 25°C 7 6 5 4 3 2 1 0 10 k 3 4 5 6 7 |VCC±| − Supply Voltage − V Figure 15 Figure 16 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY INPUT RESISTANCE vs FREE-AIR TEMPERATURE 6 40 VCC ± = ± 6 V TA = 25°C 35 5 r i − Input Resistance − kΩ VOPP − Maximum Peak-to-Peak Output Voltage − V 8 4 3 2 VCC ± = ± 6 V 30 25 GAIN 2 20 mA733C 15 10 1 5 0 1 2 4 7 10 20 40 70 100 200 400 0 − 60 − 40 −20 f − Frequency − MHz 0 20 40 60 80 100 120 140 TA − Free-Air Temperature − °C Figure 18 Figure 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 MECHANICAL DATA MCFP001A – JANUARY 1995 – REVISED DECEMBER 1995 U (S-GDFP-F10) CERAMIC DUAL FLATPACK Base and Seating Plane 0.250 (6,35) 0.246 (6,10) 0.045 (1,14) 0.026 (0,66) 0.008 (0,20) 0.004 (0,10) 0.080 (2,03) 0.050 (1,27) 0.300 (7,62) MAX 1 0.019 (0,48) 0.015 (0,38) 10 0.050 (1,27) 0.280 (7,11) 0.230 (5,84) 5 6 4 Places 0.005 (0,13) MIN 0.350 (8,89) 0.250 (6,35) 0.350 (8,89) 0.250 (6,35) 4040179 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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