LD39100XX LD39100XX12, LD39100XX25 1 A, low quiescent current, low noise voltage regulator Features ■ Input voltage from 1.5 to 5.5 V ■ Ultra low dropout voltage (200 mV typ. at 1 A load) ■ Very low quiescent current (20 µA typ. at no load, 200 µA typ. at 1 A load, 1 µA max in off mode) ■ Very low noise with no bypass capacitor (30 µVRMS at VOUT = 0.8 V) ■ Output voltage tolerance: ± 2.0 % @ 25 °C ■ 1 A guaranteed output current ■ Wide range of output voltages available on request: 0.8 V to 4.5 V with 100 mV step and adjustable from 0.8 V ■ Logic-controlled electronic shutdown ■ Stabilized with ceramic capacitors COUT = 1 µF ■ Internal current and thermal limit ■ DFN6 (3 x 3 mm) package ■ Temperature range: - 40 °C to 125 °C Applications ■ Printers ■ Personal digital assistants (PDAs) ■ Cordless phones ■ Consumer applications DFN6 (3 x 3 mm) with a typical dropout voltage of 200 mV. The device is stable due to the use of ceramic capacitors on the input and output. The ultra low drop-voltage, low quiescent current and low noise features make it suitable for low power battery powered applications. Power supply rejection is 65 dB at low frequencies and starts to roll off at 10 kHz. An enable logic control function puts the LD39100xx in shutdown mode, allowing a total current consumption lower than 1 µA. The device also includes short-circuit constant current limiting and thermal protection. Description The LD39100xx provides 1 A maximum current from an input voltage ranging from 1.5 V to 5.5 V Table 1. October 2011 Device summary Part numbers Order codes Output voltages LD39100XX LD39100PUR Adj. from 0.8 V LD39100XX12 LD39100PU12R 1.2 V LD39100XX25 LD39100PU25R 2.5 V Doc ID 15676 Rev 3 1/23 www.st.com 23 Contents LD39100XX, LD39100XX12, LD39100XX25 Contents 1 Circuit schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 Power Good function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/23 Doc ID 15676 Rev 3 LD39100XX, LD39100XX12, LD39100XX25 Circuit schematics 1 Circuit schematics Figure 1. Schematic diagram for the LD39100PU IN PG Power-good signal IN BandGap reference Current limit OpAmp OUT Thermal protection ADJ EN Internal enable GND Figure 2. Schematic diagram for the LD39100PUxx IN PG Power-good signal IN BandGap reference Current limit OpAmp OUT Thermal protection R1 NC EN R2 Internal enable GND Doc ID 15676 Rev 3 3/23 Pin configuration LD39100XX, LD39100XX12, LD39100XX25 2 Pin configuration Figure 3. Pin connection (top view) EN VIN EN GND NC GND ADJ PG VOUT VOUT PG LD39100PUxx Table 2. VIN LD39100PU Pin description Pin n° Symbol LD39100PUxx EN 1 1 Enable pin logic input: Low = shutdown, High = active GND 2 2 Common ground PG 3 3 Power Good VOUT 4 4 Output voltage ADJ 5 - Adjust pin VIN 6 6 Input voltage of the LDO NC - 5 Not connected GND 4/23 Function LD39100PU EXP pad Exposed pad must be connected to GND Doc ID 15676 Rev 3 LD39100XX, LD39100XX12, LD39100XX25 3 Maximum ratings Table 3. Absolute maximum ratings Symbol Maximum ratings Value Unit -0.3 to 7 V DC output voltage -0.3 to VIN + 0.3 (7 V max) V EN Enable pin -0.3 to VIN + 0.3 (7 V max) V PG Power Good pin -0.3 to 7 V ADJ Adjust pin 4 V IOUT Output current Internally limited Power dissipation Internally limited VIN VOUT PD Parameter DC input voltage TSTG Storage temperature range - 65 to 150 °C TOP Operating junction temperature range - 40 to 125 °C Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND. Table 4. Thermal data Symbol Parameter Value Unit RthJA Thermal resistance junction-ambient 55 °C/W RthJC Thermal resistance junction-case 10 °C/W Table 5. Symbol ESD ESD performance Parameter Test conditions Value Unit HBM 4 kV MM 0.4 kV ESD protection voltage Doc ID 15676 Rev 3 5/23 Electrical characteristics 4 LD39100XX, LD39100XX12, LD39100XX25 Electrical characteristics TJ = 25 °C, VIN = 1.8 V, CIN = COUT = 1 µF, IOUT = 100 mA, VEN = VIN, unless otherwise specified. Table 6. Symbol VIN Electrical characteristics for the LD39100PU Parameter Operating input voltage VADJ VADJ accuracy IADJ Adjust pin current ΔVOUT Static line regulation ΔVOUT Transient line regulation (1) ΔVOUT Static load regulation ΔVOUT Transient load regulation (1) VDROP Dropout voltage (2) eN SVR Test conditions Output noise voltage Supply voltage rejection VO = 0.8 V Min. Typ. 1.5 Quiescent current 816 IOUT=10mA, -40°C<TJ<125°C 776 800 824 mV 1 VOUT+1 V ≤ VIN ≤ 5.5 V, IOUT=100mA 0.01 ΔVIN=500mV, IOUT=100mA, tR=5µs 10 ΔVIN=500mV, IOUT=100mA, tF=5µs 10 IOUT=10mA to 1A 40 IOUT=1A to 10mA, tF=5µs 40 IOUT=1A, VO fixed to 1.5V -40°C<TJ<125°C 200 10Hz to 100kHz, IOUT=100mA, VOUT=0.8V 30 VIN=1.8V+/-VRIPPLE VRIPPLE=0.25V, freq. = 1kHz IOUT=10mA 65 VIN=1.8V+/-VRIPPLE VRIPPLE=0.25V, freq.=10kHz IOUT=100mA 62 IOUT=0mA 20 6/23 400 mV µVRMS dB 50 200 µA 300 0.001 Rising edge 0.92* VOUT Falling edge 0.8* VOUT Doc ID 15676 Rev 3 %/mA mVpp VIN input current in off mode: VEN=GND(3) RL=0 %/V 0.002 IOUT=10mA to 1A, tR=5µs IOUT=0 to 1A µA mVpp Power good output voltage low Isink=6mA open drain output Short-circuit current V 800 Power good output threshold ISC 5.5 784 IOUT=0 to 1A, -40°C<TJ<125°C PG Unit IOUT=10mA, TJ = 25°C IOUT=0mA, -40°C<TJ<125°C IQ Max. 1 V 0.4 1.5 V A LD39100XX, LD39100XX12, LD39100XX25 Table 6. Electrical characteristics Electrical characteristics for the LD39100PU (continued) Symbol Parameter Test conditions Min. Typ. Enable input logic low VEN IEN tON TSHDN COUT Enable input logic high Enable pin input current Turn-on time VIN=1.5V to 5.5V, -40°C<TJ<125°C Max. Unit 0.4 V 0.9 VEN= VIN V 0.1 (4) 100 30 Thermal shutdown 160 Hysteresis 20 nA µs °C Output capacitor Capacitance (see typical performance characteristics for stability) 1 22 µF 1. All transient values are guaranteed by design, not production tested 2. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply for output voltages below 1.5 V 3. PG pin floating 4. Turn-on time is time measured between the enable input just exceeding VEN high value and the output voltage just reaching 95% of its nominal value Doc ID 15676 Rev 3 7/23 Electrical characteristics LD39100XX, LD39100XX12, LD39100XX25 TJ = 25 °C, VIN = VOUT(NOM) + 1 V, CIN = COUT = 1 µF, IOUT = 100 mA, VEN = VIN, unless otherwise specified. Table 7. Symbol VI VOUT Electrical characteristics for LD39100PUxx Parameter VOUT accuracy Static line regulation ΔVOUT Transient line regulation (1) ΔVOUT Static load regulation ΔVOUT Transient load regulation (1) VDROP SVR Max. Unit 1.5 5.5 V VOUT>1.5V, IOUT=10mA, TJ = 25°C -2.0 2.0 VOUT>1.5V, IOUT=10mA, -40°C<TJ<125°C -3.0 3.0 Operating input voltage ΔVOUT eN Test conditions Min. Typ. % VOUT ≤ 1.5V, IOUT=10mA ±20 VOUT ≤ 1.5V, IOUT=10mA, -40°C<TJ<125°C ±30 VOUT+1V ≤ VIN ≤ 5.5V, IOUT=100mA 0.01 ΔVIN=500mV, IOUT=100mA, tR=5µs 10 ΔVIN=500 mV, IOUT=100mA, tF=5µs 10 mV mVpp IOUT=10 mA to 1A 0.002 IOUT=10 mA to 1A, tR=5µs 40 IOUT=1A to 10mA, tF=5µs 40 Dropout voltage (2) IOUT=1A, VOUT > 1.5V, -40°C<TJ<125°C 200 Output noise voltage 10Hz to 100kHz, IOUT=100mA, VOUT=2.5V 85 VIN=VOUT(NOM)+0.5V+/-VRIPPLE VRIPPLE=0.1V, freq. = 1kHz IOUT=10mA 65 VIN=VOUT(NOM)+0.5V+/-VRIPPLE VRIPPLE=0.1V, freq.=10 kHz IOUT=100mA 62 IOUT = 0 mA 20 Supply voltage rejection VOUT=1.5V Quiescent current IOUT = 0 to 1A 8/23 Enable input logic high µA 300 VIN input current in OFF mode: VEN = GND(3) 0.001 Rising edge 0.92* VOUT Falling edge 0.8* VOUT 1 V 0.4 RL=0 1.5 VIN=1.5 V to 5.5 V, -40°C<TJ<125°C Doc ID 15676 Rev 3 0.9 V A 0.4 Enable input logic low VEN µVRMS 200 Power good output voltage low Isink=6mA open drain output Short-circuit current mV 50 Power good output threshold ISC 400 dB IOUT = 0 to 1A -40°C<TJ<125°C PG %/mA mVpp IOUT = 0 mA, -40°C<TJ<125°C IQ %/V V V LD39100XX, LD39100XX12, LD39100XX25 Table 7. Electrical characteristics Electrical characteristics for LD39100PUxx (continued) Symbol Parameter Test conditions Min. Max. Unit 0.1 100 nA IEN Enable pin input current TON Turn-on time (4) 30 Thermal shutdown 160 Hysteresis 20 TSHDN COUT VEN = VIN Typ. µs °C Output capacitor Capacitance (see typical performance characteristics for stability) 1 22 µF 1. All transient values are guaranteed by design, not production tested 2. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply for output voltages below 1.5 V 3. PG pin floating 4. Turn-on time is time measured between the enable input just exceeding VEN high Value and the output voltage just reaching 95% of its nominal value Doc ID 15676 Rev 3 9/23 Typical performance characteristics 5 LD39100XX, LD39100XX12, LD39100XX25 Typical performance characteristics CIN = COUT = 1 µF. Figure 4. VADJ accuracy Figure 5. 2.56 0.86 VIN = 3.5 V, VEN = VIN, IOUT = 10 mA VIN = 1.8 V, VEN = VIN, IOUT = 10 mA 0.84 2.54 0.82 2.52 VOUT [V] VADJ [V] VOUT accuracy 0.8 0.78 2.5 2.48 2.46 0.76 2.44 0.74 -50 -25 0 25 50 75 100 125 -50 150 -25 0 25 50 Figure 6. Dropout voltage vs. temperature (VOUT = 2.5 V) Figure 7. 400 350 VEN to VIN, VOUT = 2.5 V, IOUT = 1 A 100 125 150 250 200 150 100 50 Dropout voltage vs. temperature (VOUT = 1.5 V) VEN to VIN, VOUT @ 1.5 V, IOUT = 1 A 350 Dropout [mV] Dropout [mV] 300 75 T [°C] T [°C] 300 250 200 150 100 50 0 0 -50 -25 0 25 50 75 100 125 -50 150 -25 0 25 50 Figure 8. 75 100 125 150 T [°C] T [°C] Dropout voltage vs. output current Figure 9. Short-circuit current vs. drop voltage 0.25 VOUT @ 1.5 V VEN to VIN 3.5 VIN from 0 to 5.5 V, VEN to VIN, VOUT = 0.8 V 3 VOUT = 2.5 V 2.5 0.15 ISC [A] Dropout [V] 0.2 0.1 125 °C 85 °C 55 °C 25 °C 0 °C -25 °C -40 °C 2 1.5 1 0.05 0.5 0 0 0 0 200 400 600 800 1000 0.5 1200 IOUT [mA] 10/23 Doc ID 15676 Rev 3 1 1.5 2 2.5 3 3.5 Vdrop [V] 4 4.5 5 5.5 6 LD39100XX, LD39100XX12, LD39100XX25 Typical performance characteristics Figure 10. Output voltage vs. input voltage (VOUT = 0.8 V) Figure 11. Output voltage vs. input voltage (VOUT = 2.5 V) 1.2 3 VIN from 0 to 5.5 V, VEN to VIN, VOUT = 0.8 V, IOUT = 1 A VIN from 0 to 5 V, VEN to VIN, VOUT = 2.5 V, IOUT = 1A 2.5 0.8 VOUT [V] VOUT [V] 1 125°C 0.6 85°C 55°C 0.4 85°C 1.5 0.2 25°C -25°C -25°C -40°C 0 0 0 0 0.5 1 1.5 2 2.5 3 3.5 VIN [V] 4 4.5 5 5.5 0.5 1 1.5 2 2.5 6 Figure 12. Quiescent current vs. temperature 3 3.5 4 4.5 5 5.5 6 VIN [V] Figure 13. VIN input current in off mode vs. temperature 0.6 140 VIN = 3.5 V, VEN to GND, VOUT = 2.5 V 0.5 120 80 Iq [µA] 100 Iq [µA] 0°C 0.5 -40°C No Load IOUT = 1 A 60 VIN = 1.8 V, VEN to VIN, VOUT = 2.5 V 40 0.4 0.3 0.2 20 0.1 0 -50 -25 0 25 50 75 100 125 0 -50 150 T [°C] 0 25 50 75 100 125 150 Figure 15. Line regulation 0.04 0.015 0.03 VIN = 3.5 V, IOUT = from 10 mA to 1 A, VEN=VIN, VOUT = 2.5 V 0.01 VIN = from 1.8 V to 5.5 V, IOUT = 100 mA, VEN = VIN, VOUT = 0.8 V Line [%/V] 0.02 0.005 0 -0.005 0.01 0 -0.01 -0.02 -0.01 -0.015 -50 -25 T [°C] Figure 14. Load regulation Load [%/mA] 55°C 1 25°C 0°C 125°C 2 -0.03 -25 0 25 50 75 100 125 150 -0.04 -50 T [°C] -25 0 25 50 75 100 125 150 T [°C] Doc ID 15676 Rev 3 11/23 Typical performance characteristics LD39100XX, LD39100XX12, LD39100XX25 Figure 16. Line regulation 0.04 Figure 17. Supply voltage rejection vs. temperature (VOUT = 0.8 V) VIN = from 3.5 V to 5.5 V, IOUT = 100 mA, VEN = VIN, VOUT = 2.5 V 0.03 100 VIN from 1.7 V to 1.9 V, VEN to VIN, VOUT = 0.8 V 80 SVR [dB] Line [%/V] 0.02 0.01 0 -0.01 -0.02 60 40 Freq.10 kHz, IOUT = 100 mA 20 -0.03 Freq.1 kHz, IOUT = 10 mA 0 -50 -0.04 -50 -25 0 25 50 75 100 125 -25 0 25 150 50 75 100 125 150 T [°C] T [°C] Figure 18. Supply voltage rejection vs. temperature (VOUT = 2.5 V) Figure 19. Supply voltage rejection vs. frequency (VOUT = 0.8 V) 100 100 VIN from 2.9 V to 3.1 V, VEN to VIN, VOUT = 2.5 V SVR [dB] SVR [dB] IOUT = 10 mA VIN from 1.55 V to 2.05 V, VEN to VIN, VOUT = 0.8 V 80 80 60 40 Freq. = 10 kHz, IOUT = 100 mA 20 IOUT = 100 mA 60 40 20 Freq. = 1 kHz, IOUT = 10 mA 0 -50 0 -25 0 25 50 75 100 125 0 150 10 20 30 40 50 60 70 80 90 100 110 Freq [kHz] T [°C] Figure 20. Supply voltage rejection vs. frequency (VOUT = 2.5 V) Figure 21. Output noise voltage vs. frequency 100 90 80 70 60 50 40 30 20 10 0 VIN from 2.9 V to 3.1 V, VEN to VIN, VOUT = 2.5 V AP - IOUT = 10mA IOUT = 100 mA 0 10 20 30 40 50 60 Freq [kHz] AP - IOUT = 1mA IOUT = 10 mA 70 80 90 eN [µV/SQRT(Hz)] SVR [dB] AP - IOUT = 100mA 2.5 AP - IOUT = 0A 2.0 1.5 1.0 0.5 100 110 0.0 1.E+01 1.E+02 1.E+03 f [Hz] VIN = 1.8 V, VOUT = 0.8 V, VEN = VIN 12/23 Doc ID 15676 Rev 3 1.E+04 1.E+05 LD39100XX, LD39100XX12, LD39100XX25 Typical performance characteristics VEN [V] Figure 22. Enable voltage vs. temperature 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 VIN = 5.5 V IOUT = 100 mA, VOUT = 0.8 V Figure 23. Load transient (IOUT = from 10 mA to 1 A) High VOUT Low IOUT -25 0 25 50 75 100 125 150 T [°C] VEN= VIN=3.5V, VOUT=0.8V, IOUT= from10mA to 1A, tR= tF =5 µs Figure 24. Load transient (VOUT = 0.8 V) VOUT Figure 25. Load transient (VOUT = 2.5 V) VOUT IOUT IOUT VEN= VIN=3.5V, VOUT=0.8V, IOUT= from100 mA to 1A, tR= tF =5 µs VEN= VIN=3.5V, VOUT=2.5V, IOUT= from10 mA to 1A, tR= tF =5 µs Figure 26. Load transient (IOUT = from 100 mA Figure 27. Line regulation transient to 1 A) VIN VOUT VOUT IOUT VEN= VIN=3.5V, VOUT=2.5V, IOUT= from100 mA to 1A, tR= tF =5 µs VEN= VIN =1.8 V to 2.3 V, VOUT = 0.8V, IOUT=100 mA, tR = tF = 5 µs Doc ID 15676 Rev 3 13/23 Typical performance characteristics LD39100XX, LD39100XX12, LD39100XX25 Figure 28. Startup transient Figure 29. Enable transient VIN VEN VOUT VOUT VEN= VIN= from 0.8 V, VOUT=0.8 V, IOUT = 100 mA VEN= 0 to 2 V, VOUT=0.8 V, VIN = 3.5 V, IOUT = 100 mA, tR = 5 µs Figure 30. ESR required for stability with ceramic capacitors (VOUT = 0.8 V) Figure 31. ESR required for stability with ceramic capacitors (VOUT = 2.5 V) 0.25 UNSTABLE ZONE 0.2 ESR @ 100kHz [Ω] ESR @ 100 kHz [ohm] 0.25 0.15 0.1 STABLE ZONE 0.05 0.15 0.1 STABLE ZONE 0.05 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 COUT [µF] (nominal value) VIN = VEN = from 1.5 V to 5.5 V, VOUT = 0.8 V, IOUT = from 1 mA to 1 A 14/23 UNSTABLE ZONE 0.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 COUT [µF] (nominal value) VIN = VEN = from 3.5 V to 5.5 V, VOUT = 2.5 V, IOUT = from1 mA to 1 A Doc ID 15676 Rev 3 LD39100XX, LD39100XX12, LD39100XX25 6 Application information Application information The LD39100xx is an ultra low dropout linear regulator. It provides up to 1 A with a low 200 mV dropout. The input voltage range is from 1.5 V to 5.5 V. The device is available in fixed and adjustable output versions. The regulator is equipped with internal protection circuitry, such as short-circuit current limiting and thermal protection. The regulator is stable due to ceramic capacitors on the input and the output. The expected values of the input and output ceramic capacitors are from 1 µF to 22 µF with 1 µF typical. The input capacitor must be connected within 0.5 inches of the VIN terminal. The output capacitor must also be connected within 0.5 inches of output pin. There is no upper limit to the value of the input capacitor. Figure 32 and Figure 33 illustrate the typical application schematics: Figure 32. Typical application circuit for the fixed output version VIN 6 1 CIN PG VIN EN LD39100PUxx VOUT 3 VOUT 4 OFF ON NC GND 5 COUT 2 Figure 33. Typical application circuit for the adjustable version VIN 6 1 PG VIN EN LD39100PU VOUT 3 OFF ON CIN GND ADJ 2 Doc ID 15676 Rev 3 VOUT 4 5 R1 COUT R2 15/23 Application information LD39100XX, LD39100XX12, LD39100XX25 For the adjustable version, the output voltage can be adjusted from 0.8 V up to the input voltage, minus the voltage drop across the PMOS (dropout voltage), by connecting a resistor divider between the ADJ pin and the output, thus allowing remote voltage sensing. The resistor divider should be selected using the following equation: VOUT = VADJ (1 + R1 / R2) with VADJ = 0.8 V (typ.) It is recommended to use resistors with values in the range of 10 kΩ to 50 kΩ. Lower values can also be suitable, but will increase current consumption. 6.1 Power dissipation An internal thermal feedback loop disables the output voltage if the die temperature rises to approximately 160 °C. This feature protects the device from excessive temperature and allows the user to push the limits of the power handling capability of a given circuit board without the risk of damaging the device. It is very important to use a good PC board layout to maximize power dissipation. The thermal path for the heat generated by the device is from the die to the copper lead frame through the package leads and exposed pad to the PC board copper. The PC board copper acts as a heat sink. The footprint copper pads should be as wide as possible to spread and dissipate the heat to the surrounding ambient. Feed-through vias to the inner or backside copper layers are also useful in improving the overall thermal performance of the device. The power dissipation of the device depends on the input voltage, output voltage and output current, and is given by: PD = (VIN -VOUT) IOUT The junction temperature of the device is: TJ_MAX = TA + RthJA x PD where: TJ_MAX is the maximum junction of the die,125 °C; TA is the ambient temperature; RthJA is the thermal resistance junction-to-ambient. Figure 34. Power dissipation vs. ambient temperature 3.5 3 PD [W] 2.5 2 1.5 1 0.5 0 -50 -30 -10 10 30 50 TA [°C] 16/23 Doc ID 15676 Rev 3 70 90 110 130 LD39100XX, LD39100XX12, LD39100XX25 6.2 Application information Enable function The LD39100xx features an enable function. When the EN voltage is higher than 2 V, the device is ON, and if it is lower than 0.8 V, the device is OFF. In shutdown mode, consumption is lower than 1 µA. The EN pin does not have an internal pull-up, which means that it cannot be left floating if it is not used. 6.3 Power Good function Most applications require a flag showing that the output voltage is in the correct range. The Power Good threshold depends on the adjust voltage. When the adjust is higher than 0.92*VADJ, the Power Good (PG) pin goes to high impedance. If the adjust is below 0.80*VADJ the PG pin goes to low impedance. If the device is functioning well, the Power Good pin is at high impedance. If the output voltage is fixed using an external or internal resistor divider, the Power Good threshold is 0.92*VOUT. The use of the Power Good function requires an external pull-up resistor, which must be connected between the PG pin and VIN or VOUT. The typical current capability of the PG pin is up to 6 mA. The use of a pull-up resistor for PG in the range of 100 kΩ to 1 MΩ is recommended. If the Power Good function is not used, the PG pin must remain floating. Doc ID 15676 Rev 3 17/23 Package mechanical data 7 LD39100XX, LD39100XX12, LD39100XX25 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 18/23 Doc ID 15676 Rev 3 LD39100XX, LD39100XX12, LD39100XX25 Package mechanical data DFN6 (3x3 mm) mechanical data mm. inch. Dim. Min. Typ. Max. Min. Typ. Max. A 0.80 0.90 1.00 0.031 0.035 0.039 A1 0 0.02 0.05 0 0.001 0.002 A3 0.20 0.008 b 0.23 0.30 0.38 0.009 0.012 0.015 D 2.90 3.00 3.10 0.114 0.118 0.122 D2 2.23 2.38 2.48 0.088 0.094 0.098 E 2.90 3.00 3.10 0.114 0.118 0.122 E2 1.50 1.65 1.75 0.059 0.065 0.069 e L 0.95 0.30 0.40 0.037 0.50 0.012 0.016 0.020 7946637A Doc ID 15676 Rev 3 19/23 Package mechanical data LD39100XX, LD39100XX12, LD39100XX25 Tape & reel QFNxx/DFNxx (3x3) mechanical data mm. inch. Dim. Min. Typ. A Min. Typ. 330 13.2 12.8 D 20.2 0.795 N 60 2.362 0.504 0.519 18.4 0.724 Ao 3.3 0.130 Bo 3.3 0.130 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 Doc ID 15676 Rev 3 Max. 12.992 C T 20/23 Max. LD39100XX, LD39100XX12, LD39100XX25 Package mechanical data Figure 35. DFN6 (3 x 3) footprint recommended data Doc ID 15676 Rev 3 21/23 Revision history LD39100XX, LD39100XX12, LD39100XX25 8 Revision history Table 8. Document revision history Date Revision 29-Jul-2009 1 Initial release. 16-Apr-2010 2 Modified Figure 8 on page 10. 11-Oct-2011 3 Document status promoted from preliminary data to datasheet. 22/23 Changes Doc ID 15676 Rev 3 LD39100XX, LD39100XX12, LD39100XX25 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 15676 Rev 3 23/23