STMICROELECTRONICS STM32F050K4

STM32F050x4 STM32F050x6
Low- and medium-density advanced ARM™-based 32-bit MCU with
up to 32 Kbytes Flash, timers, ADC and comm. interfaces
Datasheet − production data
Features
■
Core: ARM 32-bit Cortex™-M0 CPU,
frequency up to 48 MHz
■
Memories
– 16 to 32 Kbytes of Flash memory
– 4 Kbytes of SRAM with HW parity checking
■
CRC calculation unit
■
Reset and supply management
– Voltage range: 2.0 V to 3.6 V
– Power-on/Power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop and
Standby
– VBAT supply for RTC and backup registers
LQFP48 7x7
UFQFPN32 5x5
UFQFPN28 4x4
TSSOP20
– 1 x 16-bit timer with 1 IC/OC
– Independent and system watchdog timers
– SysTick timer: 24-bit downcounter
■
Calendar RTC with alarm and periodic wakeup
from Stop/Standby
■
Communication interfaces
– 1 x I2C interface; supporting Fast Mode
Plus (1 Mbit/s) with 20 mA current sink,
SMBus/PMBus, and wakeup from STOP
– 1 x USART supporting master synchronous
SPI and modem control; one with ISO7816
interface, LIN, IrDA capability auto baud
rate detection and wakeup feature
– 1 x SPI (18 Mbit/s) with 4 to 16
programmable bit frames, with I2S interface
multiplexed
■
Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
■
Up to 39 fast I/Os
– All mappable on external interrupt vectors
– Up to 25 I/Os with 5 V tolerant capability
■
Serial wire debug (SWD)
■
96-bit unique ID
■
5-channel DMA controller
■
Extended temperature range: -40 to +105°C
■
1 × 12-bit, 1.0 µs ADC (up to 10 channels)
– Conversion range: 0 to 3.6V
– Separate analog supply from 2.4 up to
3.6 V
■
Up to 9 timers
– 1 x 16-bit 7-channel advanced-control timer
for 6 channels PWM output, with deadtime
generation and emergency stop
– 1 x 32-bit and 1 x 16-bit timer, with up to 4
IC/OC, usable for IR control decoding
– 1 x 16-bit timer, with 2 IC/OC, 1 OCN,
deadtime generation and emergency stop
– 1 x 16-bit timer, with IC/OC and OCN,
deadtime generation, emergency stop and
modulator gate for IR control
November 2012
This is information on a product in full production.
Table 1.
Reference
Device summary
Part number
STM32F050x4
STM32F050F4, STM32F050G4, STM32F050K4,
STM32F050C4
STM32F050x6
STM32F050F6, STM32F050G6, STM32F050K6,
STM32F050C6
Doc ID 023683 Rev 1
1/97
www.st.com
1
Contents
STM32F050xx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
ARM® CortexTM-M0 core with embedded Flash and SRAM . . . . . . . . . 12
3.2
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13
3.5
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.2
Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.10
3.11
2/97
3.5.1
3.9.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
3.9.2
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.1
Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.2
General-purpose timers (TIM2..3, TIM14..17) . . . . . . . . . . . . . . . . . . . . 18
3.11.3
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.4
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.5
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 20
3.13
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14
Universal synchronous/asynchronous receiver transmitter (USART) . . . 21
3.15
Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 22
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STM32F050xx
3.16
Contents
Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 40
6.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 40
6.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.11
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.12
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.13
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.14
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.15
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.16
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.17
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.18
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.19
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Doc ID 023683 Rev 1
3/97
Contents
7
STM32F050xx
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 93
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4/97
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F050xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 10
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 30
Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 31
STM32F050x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Typical and maximum current consumption from VDD supply at VDD = 3.6 . . . . . . . . . . . 43
Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 44
Typical and maximum VDD consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 45
Typical and maximum VDDA consumption in Stop and Standby modes. . . . . . . . . . . . . . . 45
Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 46
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 48
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Doc ID 023683 Rev 1
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List of tables
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
6/97
STM32F050xx
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
WWDG min-max timeout value @48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 85
UFQFPN32 – 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
UFQFPN28 – 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TSSOP20 – 20-pin thin shrink small outline package mechanical data . . . . . . . . . . . . . . . 91
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Doc ID 023683 Rev 1
STM32F050xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LQFP48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
UFQFPN32 32-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
UFQFPN28 28-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TSSOP20 20-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32F050xx memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
HSI oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . 68
Five volt tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . 68
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
I2S slave timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 85
LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
UFQFPN32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline . . . 87
UFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
UFQFPN28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline . . . 89
UFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
TSSOP20 - 20-pin thin shrink small outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Doc ID 023683 Rev 1
7/97
Introduction
1
STM32F050xx
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F050x4 and STM32F050x6 microcontrollers, hereafter referred to as
STM32F050xx.
This datasheet should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM Cortex™-M0 core, please refer to the Cortex™-M0 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/index.html.
8/97
Doc ID 023683 Rev 1
STM32F050xx
2
Description
Description
The STM32F050xx family incorporates the high-performance ARM Cortex™-M0 32-bit
RISC core operating at a 48 MHz maximum frequency, high-speed embedded memories
(Flash memory up to 32 Kbytes and SRAM up to 4 Kbytes), and an extensive range of
enhanced peripherals and I/Os. All devices offer standard communication interfaces (one
I2C, one SPI, one I2S, and one USART), one 12-bit ADC, up to five general-purpose 16-bit
timers, a 32-bit timer and an advanced-control PWM timer.
The STM32F050xx family operates in the -40 to +85 °C and -40 to +105 °C temperature
ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes
allows the design of low-power applications.
The STM32F050xx family includes devices in five different packages ranging from 20 pins to
48 pins. Depending on the device chosen, different sets of peripherals are included. An
overview of the complete range of peripherals proposed in this family is provided.
These features make the STM32F050xx microcontroller family suitable for a wide range of
applications such as control application and user interfaces, handheld equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
Doc ID 023683 Rev 1
9/97
Description
Table 2.
STM32F050xx
STM32F050xx family device features and peripheral counts
Peripheral
Flash (Kbytes)
SRAM (Kbytes)
STM32F050Fx
16
32
4
STM32F050Gx
16
32
16
4
Advanced
control
1 (16-bit)
General
purpose
4 (16-bit)
1 (32-bit)
SPI (I2S)(1)
I C
1
USART
1
GPIOs
1
(9 ext. + 3 int.)
15
23
27
39
2.0 to 3.6 V
Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: -40°C to 105°C / -40 °C to 125 °C
TSSOP20
UFQFPN28
1. The SPI interface can be used either in SPI mode or in I2S audio mode.
10/97
4
48 MHz
Operating voltage
Packages
32
1
(10 ext. + 3 int.)
Max. CPU frequency
Operating temperature
16
1
2
12-bit synchronized
ADC
(number of channels)
32
STM32F050Cx
4
Timers
Comm.
interfaces
STM32F050Kx
Doc ID 023683 Rev 1
UFQFPN32
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Doc ID 023683 Rev 1
11/97
Functional overview
STM32F050xx
3
Functional overview
3.1
ARM® CortexTM-M0 core with embedded Flash and SRAM
The ARM Cortex™-M0 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F050xx family has an embedded ARM core and is therefore compatible with all
ARM tools and software.
Figure 1 shows the general block diagram of the device family.
3.2
Memories
The device has the following features:
●
4 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
●
The non-volatile memory is divided into two arrays:
–
16 to 32 Kbytes of embedded Flash memory for programs and data
–
Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
3.3
–
Level 0: no readout protection
–
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot
in RAM selection disabled
Boot modes
At startup, the boot pin and boot selector option bit are used to select one of three boot
options:
●
Boot from User Flash
●
Boot from System Memory
●
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1.
12/97
Doc ID 023683 Rev 1
STM32F050xx
3.4
Functional overview
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
3.5
Power management
3.5.1
Power supply schemes
3.5.2
●
VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
●
VDDA = 2.0 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and PLL
(minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). The VDDA
voltage level must be always greater or equal to the VDD voltage level and must be
provided first.
●
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
●
The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
●
The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
Doc ID 023683 Rev 1
13/97
Functional overview
3.5.3
STM32F050xx
Voltage regulator
The regulator has three operating modes: main (MR), low power (LPR) and power down.
●
MR is used in normal operating mode (Run)
●
LPR can be used in Stop mode where the power demand is reduced
●
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
3.5.4
Low-power modes
The STM32F050xx family supports three low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●
Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC alarm, I2C1 or
USART1.
The I2C1 and the USART1 can be configured to enable the HSI RC oscillator for
processing incoming data. If this is used, the voltage regulator should not be put in the
low-power mode but kept in normal mode.
●
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pins, or an RTC alarm occurs.
Note:
14/97
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
Doc ID 023683 Rev 1
STM32F050xx
3.6
Functional overview
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Figure 2.
Clock tree
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Doc ID 023683 Rev 1
15/97
Functional overview
3.7
STM32F050xx
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to avoid
spurious writing to the I/Os registers.
3.8
Direct memory access controller (DMA)
The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except
TIM14) and ADC.
3.9
Interrupts and events
3.9.1
Nested vectored interrupt controller (NVIC)
The STM32F050xx family embeds a nested vectored interrupt controller able to handle up
to 32 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M0) and 4
priority levels.
●
Closely coupled NVIC gives low latency interrupt processing
●
Interrupt entry vector table address passed directly to the core
●
Closely coupled NVIC core interface
●
Allows early processing of interrupts
●
Processing of late arriving higher priority interrupts
●
Support for tail-chaining
●
Processor state automatically saved
●
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.9.2
Extended interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 39
GPIOs can be connected to the 16 external interrupt lines.
16/97
Doc ID 023683 Rev 1
STM32F050xx
3.10
Functional overview
Analog to digital converter (ADC)
The 12-bit analog to digital converter has up to 16 external and 3 internal (temperature
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy
of the temperature measurement. As the offset of the temperature sensor varies from chip
to chip due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 3.
Temperature sensor calibration values
Calibration value name
3.10.2
Description
Memory address
TS_CAL1
TS ADC raw data acquired at
temperature of 30 °C,
VDDA= 3.3 V
0x1FFF F7B8 - 0x1FFF F7B9
TS_CAL2
TS ADC raw data acquired at
temperature of 110 °C
VDDA= 3.3 V
0x1FFF F7C2 - 0x1FFF F7C3
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage
of VREFINT is individually measured for each part by ST during production test and stored in
the system memory area. It is accessible in read-only mode.
Table 4.
Temperature sensor calibration values
Calibration value name
VREFINT_CAL
Description
Raw data acquired at
temperature of 30 °C
VDDA= 3.3 V
Doc ID 023683 Rev 1
Memory address
0x1FFF F7BA - 0x1FFF F7BB
17/97
Functional overview
3.11
STM32F050xx
Timers and watchdogs
The STM32F050xx family devices include up to six general-purpose timers, one basic timer
and an advanced control timer.
Table 5 compares the features of the advanced-control, general-purpose and basic timers.
Table 5.
Timer feature comparison
Timer
type
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA request
generation
Advanced
control
TIM1
16-bit
Up, down,
up/down
Any integer
between 1
and 65536
Yes
4
Yes
TIM2
32-bit
Up, down,
up/down
Any integer
between 1
and 65536
Yes
4
No
TIM3
16-bit
Up, down,
up/down
Any integer
between 1
and 65536
Yes
4
No
TIM14
16-bit
Up
Any integer
between 1
and 65536
No
1
No
TIM16,
TIM17
16-bit
Up
Any integer
between 1
and 65536
Yes
1
Yes
General
purpose
3.11.1
Capture/compare Complementary
channels
outputs
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:
●
Input capture
●
Output compare
●
PWM generation (edge or center-aligned modes)
●
One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.11.2
General-purpose timers (TIM2..3, TIM14..17)
There are six synchronizable general-purpose timers embedded in the STM32F050xx
devices (see Table 5 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
18/97
Doc ID 023683 Rev 1
STM32F050xx
Functional overview
TIM2, TIM3
STM32F050xx devices feature two synchronizable 4-channel general-purpose timers. TIM2
is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a
16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advancedcontrol timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or
one-pulse mode output.
TIM16, and TIM17 have a complementary output with dead-time generation and
independent DMA request generation
Their counters can be frozen in debug mode.
3.11.3
Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with userdefined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.11.4
System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
Doc ID 023683 Rev 1
19/97
Functional overview
3.11.5
STM32F050xx
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
3.12
●
A 24-bit down counter
●
Autoreload capability
●
Maskable system interrupt generation when the counter reaches 0.
●
Programmable clock source (HCLK or HCLK/8)
Real-time clock (RTC) and backup registers
The RTC and the 5 backup registers are supplied through a switch that takes power either
on VDD supply when present or through the VBAT pin. The backup registers are five 32-bit
registers used to store 20 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
●
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
●
Automatically correction for 28, 29 (leap year), 30, and 31 day of the month.
●
Programmable alarm with wake up from Stop and Standby mode capability.
●
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
●
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
●
2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
●
Timestamp feature which can be used to save the calendar content. This function can
triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
The RTC clock sources can be:
20/97
●
A 32.768 kHz external crystal
●
A resonator or oscillator
●
The internal low-power RC oscillator (typical frequency of 40 kHz)
●
The high-speed external clock divided by 32.
Doc ID 023683 Rev 1
STM32F050xx
3.13
Functional overview
Inter-integrated circuit interface (I2C)
The I2C interface (I2C1) can operate in multimaster or slave mode. It can support Standard
mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s)
with 20 mA output drive.
It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses,
1 with configurable mask). It also includes programmable analog and digital noise filters.
Table 6.
Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
≥ 50 ns
Programmable length from 1 to 15
I2C peripheral clocks
Benefits
Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C interface can be served by the DMA controller.
3.14
Universal synchronous/asynchronous receiver transmitter
(USART)
The device embeds an universal synchronous/asynchronous receiver transmitters
(USART1), which communicates at speeds of up to 6 Mbit/s.
It provides hardware management of the CTS, RTS and RS485 DE signals, multiprocessor
communication mode, master synchronous communication and single-wire half-duplex
communication mode. It also supports SmartCard communication (ISO 7816), IrDA SIR
ENDEC, LIN Master/Slave capability, auto baud rate feature and has a clock domain
independent from the CPU clock, allowing it to wake up the MCU from Stop mode.
The USART interface can be served by the DMA controller.
Doc ID 023683 Rev 1
21/97
Functional overview
3.15
STM32F050xx
Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I2S)
The SPI (SPI1) is able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
One standard I2S interface (multiplexed with SPI1) supporting four different audio standards
can operate as master or slave at half-duplex communication mode. It can be configured to
transfer 16 and 24 or 32 bits with16-bit or 32-bit data resolution and synchronized by a
specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit
programmable linear prescaler. When operating in master mode it can output a clock for an
external audio component at 256 times the sampling frequency.
3.16
Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
22/97
Doc ID 023683 Rev 1
STM32F050xx
Pinouts and pin description
6"!4
0#
0#/3#?).
0#/3#?/54
0&/3#?).
0&/3#?/54
.234
633!
6$$!
0!
0!
0!
0"
0!
0"
0"
0"
0"
0"
"//4
,1&0
0&
0&
0!
0!
0!
0!
0!
0!
0"
0"
0"
0"
6$$
0"
633
0"
0"
0"
0"
0!
0!
0!
0!
0!
0!
0"
LQFP48 48-pin package pinout
6$$
633
Figure 3.
-36
UFQFPN32 32-pin package pinout
0"
"//4
0"
0"
0"
0"
0"
0!
Figure 4.
6$$
0&/3#?).
0&/3#?/54
.234
6$$!
0!
0!
0!
633
633!
0!
0!
0!
0!
0!
0!
0!
6$$
0!
0!
0!
0!
0!
0"
0"
0"
4
Pinouts and pin description
-36
Doc ID 023683 Rev 1
23/97
Pinouts and pin description
UFQFPN28 28-pin package pinout
0"
0"
0"
0"
0"
0!
0!
Figure 5.
STM32F050xx
0!
0!
0!
0!
6$$
633
0"
0!
0"
0!
0!
0!
0!
0!
"//4
0&/3#?).
0&/3#?/54
.234
6$$!
0!
0!
-36
Figure 6.
TSSOP20 20-pin package pinout
"//4
0&/3#?).
0&/3#?/54
0!
0!
0!
0! 6$$
633
0"
0!
0!
0!
.234
6$$!
0!
0!
0!
0!
0!
-36
24/97
Doc ID 023683 Rev 1
STM32F050xx
Pinouts and pin description
Table 7.
Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
FTf
5 V tolerant I/O, FM+ capable
TTa
3.3 V tolerant I/O directly connected to ADC
TC
Standard 3.3V I/O
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
I/O structure
Notes
Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions
Additional
Functions directly selected/enabled through peripheral registers
functions
Doc ID 023683 Rev 1
25/97
Pinouts and pin description
Pin definitions
UFQFPN32
UFQFPN28
TSSOP20
1
-
-
-
Pin name
(function after
reset)
Pin type
LQFP48
Pin number
VBAT
S
I/O structure
Table 8.
STM32F050xx
Pin functions
Notes
Alternate functions
Additional
functions
Backup power supply
2
-
-
-
PC13
I/O
TC
(1)(2)
RTC_TAMP1,
RTC_TS,
RTC_OUT,
WKUP2
3
-
-
-
PC14/OSC32_IN
(PC14)
I/O
TC
(1)(2)
OSC32_IN
4
-
-
-
PC15/OSC32_OUT
(PC15)
I/O
TC
(1)(2)
OSC32_OUT
5
2
2
2
PF0/OSC_IN
(PF0)
I/O
FT
OSC_IN
6
3
3
3
PF1/OSC_OUT
(PF1)
I/O
FT
OSC_OUT
7
4
4
4
NRST
I/O
RST
8
0
-
-
VSSA
S
Analog ground
9
5
5
5
VDDA
S
Analog power supply
10
6
6
6
PA0
I/O
TTa
TIM2_CH1_ETR,
USART1_CTS(3)
ADC_IN0,
RTC_TAMP2,
WKUP1
11
7
7
7
PA1
I/O
TTa
TIM2_CH2,
EVENTOUT,
USART1_RTS(3)
ADC_IN1
12
8
8
8
PA2
I/O
TTa
TIM2_CH3,
USART1_TX(3)
ADC_IN2
13
9
9
9
PA3
I/O
TTa
TIM2_CH4,
USART1_RX(3)
ADC_IN3
TTa
SPI1_NSS,
I2S1_WS,
TIM14_CH1,
USART1_CK(3)
ADC_IN4
TTa
SPI1_SCK,
I2S1_CK,
TIM2_CH1_ETR
ADC_IN5
14
15
26/97
10
11
10
11
10
11
PA4
PA5
I/O
I/O
Doc ID 023683 Rev 1
Device reset input / internal reset output
(active low)
STM32F050xx
Pin definitions (continued)
16
12
12
12
Pin name
(function after
reset)
PA6
Pin type
TSSOP20
UFQFPN28
UFQFPN32
LQFP48
Pin number
I/O
I/O structure
Table 8.
Pinouts and pin description
Pin functions
Notes
Alternate functions
Additional
functions
TTa
SPI1_MISO,
I2S1_MCK,
TIM3_CH1,
TIM1_BKIN,
TIM16_CH1,
EVENTOUT
ADC_IN6
ADC_IN7
17
13
13
13
PA7
I/O
TTa
SPI1_MOSI,
I2S1_SD,
TIM3_CH2,
TIM14_CH1,
TIM1_CH1N,
TIM17_CH1,
EVENTOUT
18
14
14
-
PB0
I/O
TTa
TIM3_CH3,
TIM1_CH2N,
EVENTOUT
ADC_IN8
19
15
15
14
PB1
I/O
TTa
TIM3_CH4,
TIM14_CH1,
TIM1_CH3N
ADC_IN9
20
16
-
-
PB2
I/O
FT
21
-
-
-
PB10
I/O
FTf
TIM2_CH3,
I2C1_SCL(3)
22
-
-
-
PB11
I/O
FTf
TIM2_CH4,
EVENTOUT,
I2C1_SDA(3)
23
0
16
15
VSS
S
Ground
24
17
17
16
VDD
S
Digital power supply
25
-
-
-
PB12
I/O
FT
TIM1_BKIN,
EVENTOUT,
SPI1_NSS(3)
26
-
-
-
PB13
I/O
FT
TIM1_CH1N,
SPI1_SCK(3)
27
-
-
-
PB14
I/O
FT
TIM1_CH2N,
SPI1_MISO(3)
28
-
-
-
PB15
I/O
FT
TIM1_CH3N,
SPI1_MOSI(3)
Doc ID 023683 Rev 1
RTC_REFIN
27/97
Pinouts and pin description
Pin definitions (continued)
Pin name
(function after
reset)
Pin type
TSSOP20
UFQFPN28
UFQFPN32
LQFP48
Pin number
I/O structure
Table 8.
STM32F050xx
Pin functions
Notes
Alternate functions
29
18
18
-
PA8
I/O
FT
USART1_CK,
TIM1_CH1,
EVENTOUT,
MCO
30
19
19
17
PA9
I/O
FTf
USART1_TX,
TIM1_CH2,
I2C1_SCL(3)
FTf
USART1_RX,
TIM1_CH3,
TIM17_BKIN,
I2C1_SDA(3)
31
20
20
18
PA10
I/O
32
21
-
-
PA11
I/O
FT
USART1_CTS,
TIM1_CH4,
EVENTOUT
33
22
-
-
PA12
I/O
FT
USART1_RTS,
TIM1_ETR,
EVENTOUT
34
23
21
19
PA13
(SWDAT)
I/O
FT
35
-
-
-
PF6
I/O
FTf
I2C1_SCL(3)
36
-
-
-
PF7
I/O
FTf
I2C1_SDA(3)
37
24
22
20
PA14
(SWCLK)
I/O
FT
38
39
40
28/97
25
26
27
23
24
25
-
-
-
PA15
PB3
PB4
I/O
I/O
I/O
(4)
(4)
IR_OUT,
SWDAT
SWCLK,
USART1_TX(3)
FT
SPI1_NSS,
I2S1_WS,
TIM2_CH_ETR,
EVENTOUT,
USART1_RX(3)
FT
SPI1_SCK,
I2S1_CK,
TIM2_CH2,
EVENTOUT
FT
SPI1_MISO,
I2S1_MCK,
TIM3_CH1,
EVENTOUT
Doc ID 023683 Rev 1
Additional
functions
STM32F050xx
Pin definitions (continued)
Pin name
(function after
reset)
Pin type
TSSOP20
UFQFPN28
UFQFPN32
LQFP48
Pin number
I/O structure
Table 8.
Pinouts and pin description
Pin functions
Notes
Alternate functions
41
28
26
-
PB5
I/O
FT
SPI1_MOSI,
I2S1_SD,
I2C1_SMBA,
TIM16_BKIN,
TIM3_CH2
42
29
27
-
PB6
I/O
FTf
I2C1_SCL,
USART1_TX,
TIM16_CH1N
43
30
28
-
PB7
I/O
FTf
I2C1_SDA,
USART1_RX,
TIM17_CH1N
44
31
1
1
BOOT0
I
B
45
32
-
-
PB8
I/O
FTf
I2C1_SCL,
TIM16_CH1
FTf
I2C1_SDA,
IR_OUT,
TIM17_CH1,
EVENTOUT
Additional
functions
Boot memory selection
46
-
-
-
PB9
I/O
47
0
-
-
VSS
S
Ground
48
1
-
-
VDD
S
Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- these GPIOs must not be used as a current sources (e.g. to drive an LED).
2. After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the
Battery backup domain and BKP register description sections in the STM32F05xx reference manual.
3. This alternate feature is available on standard dies only.
4. After reset, these pins are configured as SWDAT and SWCLK alternate functions, and the internal pull-up on SWDAT pin
and internal pull-down on SWCLK pin are activated.
Doc ID 023683 Rev 1
29/97
Pin name
Alternate functions selected through GPIOA_AFR registers for port A
AF0
PA0
PA1
EVENTOUT
PA2
PA3
AF1
AF2
USART1_CKS(1)
TIM2_CH1_
ETR
USART1_TX(1)
TIM2_CH2
USART1_RX(1)
TIM2_CH3
USART1_CTS
(1)
AF3
AF4
Doc ID 023683 Rev 1
AF6
TIM16_CH1
EVENTOUT
TIM17_CH1
EVENTOUT
TIM2_CH4
PA4
SPI1_NSS,
I2S1_WS
PA5
SPI1_SCK,
I2S1_CK
PA6
SPI1_MISO,
I2S1_MCK
TIM3_CH1
TIM1_BKIN
PA7
SPI1_MOSI,
I2S1_SD
TIM3_CH2
TIM1_CH1N
PA8
MCO
USART1_CK
TIM1_CH1
USART1_TX
TIM1_CH2
I2C1_SCL(1)
I2C1_SDA(1)
PA9
AF5
USART1_RTS(1)
TIM14_CH1
AF7
Pinouts and pin description
30/97
Table 9.
TIM2_CH1_
ETR
PA10
TIM17_BKIN
USART1_RX
TIM1_CH3
PA11
EVENTOUT
USART1_CTS
TIM1_CH4
PA12
EVENTOUT
USART1_RTS
TIM1_ETR
PA13
SWDAT
IR_OUT
PA14
SWCLK
USART1_TX(1)
PA15
SPI1_NSS,
I2S1_WS
USART1_RX(1)
TIM2_CH1_
ETR
TIM14_CH1
EVENTOUT
EVENTOUT
1. This alternate feature is available on standard dies only.
STM32F050xx
Alternate functions selected through GPIOB_AFR registers for port B
Pin name
AF0
AF1
AF2
PB0
EVENTOUT
TIM3_CH3
TIM1_CH2N
PB1
TIM14_CH1
TIM3_CH4
TIM1_CH3N
PB3
SPI1_SCK, I2S1_CK
EVENTOUT
TIM2_CH2
PB4
SPI1_MISO, I2S1_MCK
TIM3_CH1
EVENTOUT
PB5
SPI1_MOSI, I2S1_SD
TIM3_CH2
TIM16_BKIN
PB6
USART1_TX
I2C1_SCL
TIM16_CH1N
PB7
USART1_RX
I2C1_SDA
TIM17_CH1N
I2C1_SCL
TIM16_CH1
I2C1_SDA
TIM17_CH1
AF3
STM32F050xx
Table 10.
PB2
Doc ID 023683 Rev 1
PB8
PB9
IR_OUT
PB10
(1)
TIM2_CH3
(1)
I2C1_SCL
PB11
EVENTOUT
I2C1_SDA
TIM2_CH4
PB12
SPI1_NSS(1)
EVENTOUT
TIM1_BKIN
PB13
(1)
SPI1_SCK
I2C1_SMBA
EVENTOUT
TIM1_CH1N
PB14
(1)
SPI1_MISO
TIM1_CH2N
PB15
SPI1_MOSI(1)
TIM1_CH3N
1. This alternate feature is available on standard dies only.
Pinouts and pin description
31/97
Memory mapping
5
STM32F050xx
Memory mapping
Figure 7.
STM32F050xx memory map
X&&&&&&&&
X&&
!("
X%
X%
X
#ORTEX-INTERNAL
PERIPHERALS
RESERVED
X#
X&&
!("
X
RESERVED
X!
X
X&&&&&&&
X&&&&#
X&&&&
X
!0"
RESERVED
X
/PTION BYTES
RESERVED
3YSTEMMEMORY
X
X&&&%#
!0"
X
X
RESERVED
X
0ERIPHERALS
X
X
&LASHMEMORY
X
32!X
RESERVED
#/$%
X
X
&LASHSYSTEMMEMORY
OR32!-DEPENDINGON
"//4CONFIGURATION
X
X
2ESERVED
-36
32/97
Doc ID 023683 Rev 1
STM32F050xx
Memory mapping
Table 11.
STM32F050x peripheral register boundary addresses
Bus
Boundary address
Size
Peripheral
0x4800 1800 - 0x5FFF FFFF
~384 MB
Reserved
0x4800 1400 - 0x4800 17FF
1KB
GPIOF
0x4800 1000 - 0x4800 13FF
1KB
Reserved
0x4800 0C00 - 0x4800 0FFF
1KB
Reserved
0x4800 0800 - 0x4800 0BFF
1KB
GPIOC
0x4800 0400 - 0x4800 07FF
1KB
GPIOB
0x4800 0000 - 0x4800 03FF
1KB
GPIOA
0x4002 4400 - 0x47FF FFFF
~128 MB
Reserved
0x4002 4000 - 0x4002 43FF
1KB
Reserved
0x4002 3400 - 0x4002 3FFF
3KB
Reserved
0x4002 3000 - 0x4002 33FF
1KB
CRC
0x4002 2400 - 0x4002 2FFF
3KB
Reserved
0x4002 2000 - 0x4002 23FF
1KB
FLASH Interface
0x4002 1400 - 0x4002 1FFF
3KB
Reserved
0x4002 1000 - 0x4002 13FF
1KB
RCC
0x4002 0400 - 0x4002 0FFF
3KB
Reserved
0x4002 0000 - 0x4002 03FF
1KB
DMA
0x4001 8000 - 0x4001 FFFF
32KB
Reserved
0x4001 5C00 - 0x4001 7FFF
9KB
Reserved
0x4001 5800 - 0x4001 5BFF
1KB
DBGMCU
0x4001 4C00 - 0x4001 57FF
3KB
Reserved
0x4001 4800 - 0x4001 4BFF
1KB
TIM17
0x4001 4400 - 0x4001 47FF
1KB
TIM16
0x4001 4000 - 0x4001 43FF
1KB
Reserved
0x4001 3C00 - 0x4001 3FFF
1KB
Reserved
0x4001 3800 - 0x4001 3BFF
1KB
USART1
0x4001 3400 - 0x4001 37FF
1KB
Reserved
0x4001 3000 - 0x4001 33FF
1KB
SPI1/I2S1
0x4001 2C00 - 0x4001 2FFF
1KB
TIM1
0x4001 2800 - 0x4001 2BFF
1KB
Reserved
0x4001 2400 - 0x4001 27FF
1KB
ADC
0x4001 0800 - 0x4001 23FF
7KB
Reserved
0x4001 0400 - 0x4001 07FF
1KB
EXTI
0x4001 0000 - 0x4001 03FF
1KB
SYSCFG
0x4000 8000 - 0x4000 FFFF
32KB
Reserved
AHB2
AHB1
APB
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Memory mapping
STM32F050xx
Table 11.
STM32F050x peripheral register boundary addresses (continued)
Bus
Boundary address
Size
Peripheral
0x4000 7C00 - 0x4000 7FFF
1KB
Reserved
0x4000 7800 - 0x4000 7BFF
1KB
Reserved
0x4000 7400 - 0x4000 77FF
1KB
Reserved
0x4000 7000 - 0x4000 73FF
1KB
PWR
0x4000 5C00 - 0x4000 6FFF
5KB
Reserved
0x4000 5800 - 0x4000 5BFF
1KB
Reserved
0x4000 5400 - 0x4000 57FF
1KB
I2C1
0x4000 4800 - 0x4000 53FF
3 KB
Reserved
0x4000 4400 - 0x4000 47FF
1KB
Reserved
0x4000 3C00 - 0x4000 43FF
2KB
Reserved
0x4000 3800 - 0x4000 3BFF
1KB
Reserved
0x4000 3400 - 0x4000 37FF
1KB
Reserved
0x4000 3000 - 0x4000 33FF
1KB
IWDG
0x4000 2C00 - 0x4000 2FFF
1KB
WWDG
0x4000 2800 - 0x4000 2BFF
1KB
RTC
0x4000 2400 - 0x4000 27FF
1KB
Reserved
0x4000 2000 - 0x4000 23FF
1KB
TIM14
0x4000 1400 - 0x4000 1FFF
3KB
Reserved
0x4000 1000 - 0x4000 13FF
1KB
Reserved
0x4000 0800 - 0x4000 0FFF
2KB
Reserved
0x4000 0400 - 0x4000 07FF
1KB
TIM3
0x4000 0000 - 0x4000 03FF
1KB
TIM2
APB
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STM32F050xx
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3.3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 8.
Pin loading conditions
Figure 9.
Pin input voltage
-#5PIN
-#5PIN
C = 50 pF
6).
-36
Doc ID 023683 Rev 1
-36
35/97
Electrical characteristics
6.1.6
STM32F050xx
Power supply scheme
Figure 10. Power supply scheme
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6
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-36
Caution:
Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
6.1.7
Current consumption measurement
Figure 11. Current consumption measurement scheme
*
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-36
36/97
Doc ID 023683 Rev 1
STM32F050xx
6.2
Electrical characteristics
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics,
Table 13: Current characteristics, and Table 14: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 12.
Voltage characteristics(1)
Symbol
VDD–VDDA
VIN(2)
|ΔVDDx|
|VSSX − VSS|
VESD(HBM)
Ratings
Min
Max
Unit
-
0.4
V
Input voltage on FT and FTf pins
VSS −0.3
VDD + 4.0
V
Input voltage on TTa pins
VSS −0.3
4.0
V
Input voltage on any other pin
VSS − 0.3
4.0
V
Variations between different VDD power pins
-
50
mV
Variations between all the different ground
pins
-
50
mV
Allowed voltage difference for VDD > VDDA
Electrostatic discharge voltage (human
body model)
see Section 6.3.11: Electrical
sensitivity characteristics
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 13: Current characteristics for the maximum
allowed injected current values.
Table 13.
Current characteristics
Symbol
Ratings
Max.
IVDD(Σ)
Total current into sum of all VDD_x and VDDSDx power lines
(source)(1)
120
IVSS(Σ)
Total current out of sum of all VSS_x and VSSSD ground lines
(sink)(1)
-120
IVDD(PIN)
Maximum current into each VDD_x or VDDSDx power pin (source)(1)
100
IVSS(PIN)
Maximum current out of each VSS_x or VSSSD ground pin (sink)(1)
-100
Output current sunk by any I/O and control pin
IIO(PIN)
ΣIIO(PIN)
Output current source by any I/O and control pin
IINJ(PIN)
- 25
80
Total output current sourced by sum of all IOs and control pins(2)
-80
Injected current on TC and RST
Injected current on TTa pins
ΣIINJ(PIN)
25
Total output current sunk by sum of all IOs and control pins(2)
Injected current on FT, FTf and B pins(3)
pin(4)
(5)
Total injected current (sum of all I/O and control pins)(6)
Unit
mA
-5/+0
±5
±5
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
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Electrical characteristics
STM32F050xx
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer to Table 12: Voltage characteristics for the maximum allowed input voltage values.
5. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 12: Voltage characteristics for the maximum allowed input voltage values. Negative injection
disturbs the analog performance of the device. See note (2) below Table 51: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 14.
Thermal characteristics
Symbol
TSTG
TJ
38/97
Ratings
Storage temperature range
Maximum junction temperature
Doc ID 023683 Rev 1
Value
Unit
–65 to +150
°C
150
°C
STM32F050xx
Electrical characteristics
6.3
Operating conditions
6.3.1
General operating conditions
Table 15.
General operating conditions
Symbol
Parameter
Conditions
Min
Max
fHCLK
Internal AHB clock frequency
0
48
fPCLK
Internal APB clock frequency
0
48
VDD
Standard operating voltage
2
3.6
2
3.6
2.4
3.6
1.65
3.6
–0.3
VDD+0.3
–0.3
VDDA+0.3
–0.3
5.5
BOOT0
0
5.5
LQFP48
-
364
-
526
-
169
-
182
VDDA(1)
VBAT
MHz
Analog operating voltage
(ADC not used)
Analog operating voltage
(ADC used)
Must have a potential equal to or
higher than VDD
Backup operating voltage
TC I/O
TTa I/O
VIN
PD
Unit
I/O input voltage
(2)
FT and FTf I/O
Power dissipation at TA = 85 °C UFQFPN32
for suffix 6 or TA = 105 °C for
UFQFPN28
suffix 7(3)
V
V
V
V
mW
TSSOP20
Ambient temperature for 6
suffix version
Maximum power dissipation
–40
85
Low power dissipation(4)
–40
105
Ambient temperature for 7
suffix version
Maximum power dissipation
–40
105
–40
125
6 suffix version
–40
105
7 suffix version
–40
125
°C
TA
TJ
Low power dissipation
(4)
°C
Junction temperature range
°C
1. When the ADC is used, refer to Table 49: ADC characteristics.
2. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 14: Thermal characteristics).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 14:
Thermal characteristics).
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Electrical characteristics
6.3.2
STM32F050xx
Operating conditions at power-up / power-down
The parameters given in Table 16 are derived from tests performed under the ambient
temperature condition summarized in Table 15.
Table 16.
Operating conditions at power-up / power-down
Symbol
Parameter
tVDD
tVDDA
6.3.3
Conditions
Min
Max
VDD rise time rate
0
∞
VDD fall time rate
20
∞
VDDA rise time rate
0
∞
VDDA fall time rate
20
∞
Unit
µs/V
Embedded reset and power control block characteristics
The parameter given in Table 17 is derived from tests performed under ambient temperature
and VDD supply voltage conditions summarized in Table 15: General operating conditions.
Table 17.
Embedded reset and power control block characteristics
Symbol
VPOR/PDR(1)
VPDRhyst
(1)
tRSTTEMPO(3)
Parameter
Power on/power down
reset threshold
Conditions
Min
Typ
Max
Unit
Falling edge
1.8(2)
1.88
1.96
V
Rising edge
1.84
1.92
2.0
V
-
40
-
mV
1.5
2.5
4.5
ms
PDR hysteresis
Reset temporization
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Guaranteed by design, not tested in production.
Table 18.
Symbol
40/97
Programmable voltage detector characteristics
Parameter
VPVD0
PVD threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
VPVD4
PVD threshold 4
Min(1)
Typ
Max(1)
Unit
Rising edge
2.1
2.18
2.26
V
Falling edge
2
2.08
2.16
V
Rising edge
2.19
2.28
2.37
V
Falling edge
2.09
2.18
2.27
V
Rising edge
2.28
2.38
2.48
V
Falling edge
2.18
2.28
2.38
V
Rising edge
2.38
2.48
2.58
V
Falling edge
2.28
2.38
2.48
V
Rising edge
2.47
2.58
2.69
V
Falling edge
2.37
2.48
2.59
V
Conditions
Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
Table 18.
Symbol
Programmable voltage detector characteristics (continued)
Parameter
Min(1)
Typ
Max(1)
Unit
Rising edge
2.57
2.68
2.79
V
Falling edge
2.47
2.58
2.69
V
Rising edge
2.66
2.78
2.9
V
Falling edge
2.56
2.68
2.8
V
Rising edge
2.76
2.88
3
V
Falling edge
2.66
2.78
2.9
V
Conditions
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
VPVD7
PVD threshold 7
VPVDhyst(2)
PVD hysteresis
-
100
-
mV
PVD current consumption
-
0.15
0.26
µA
IDD(PVD)
1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
6.3.4
Embedded reference voltage
The parameters given in Table 19 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 15: General operating
conditions.
Table 19.
Symbol
Embedded internal reference voltage
Parameter
VREFINT
Internal reference voltage
TS_vrefint (2)
ADC sampling time when
reading the internal
reference voltage
ΔVREFINT
Internal reference voltage
spread over the
temperature range
TCoeff
Conditions
Min Typ
Max
Unit
–40 °C < TA < +105 °C 1.16 1.2
1.25
V
–40 °C < TA < +85 °C
VDDA = 3 V ±10 mV
Temperature coefficient
1.16 1.2 1.24(1)
V
-
5.1
17.1(3)
µs
-
-
10(3)
mV
-
-
100(3) ppm/°C
1. Data based on characterization results, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
3. Guaranteed by design, not tested in production.
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Electrical characteristics
6.3.5
STM32F050xx
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
The data provided apply to standard dies only.
Typical and maximum current consumption
The MCU is placed under the following conditions:
●
All I/O pins are in input mode with a static value at VDD or VSS (no load)
●
All peripherals are disabled except when explicitly mentioned
●
The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz and 1 wait state above 24 MHz)
●
Prefetch is ON when the peripherals are enabled, otherwise it is OFF (to enable
prefetch the PRFTBE bit in the FLASH_ACR register must be set before clock setting
and bus prescaling)
●
When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 20 to Table 26 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 15: General
operating conditions.
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STM32F050xx
Table 20.
Electrical characteristics
Typical and maximum current consumption from VDD supply at VDD = 3.6
All peripherals enabled
Symbol
Parameter
Conditions
All peripherals disabled
Max @ TA(1)
fHCLK
Typ
Max @ TA(1)
25 °C 85 °C 105 °C
Supply
current in
Run mode,
executing
from Flash
External
clock (HSE
bypass)
Internal
clock (HSI)
IDD
Supply
current in
Run mode,
executing
from RAM
External
clock (HSE
bypass)
Internal
clock (HSI)
Supply
current in
Sleep
mode,
executing
from Flash
or RAM
External
clock (HSE
bypass)
Internal
clock (HSI)
Unit
Typ
25 °C 85 °C 105 °C
48 MHz
18.4
20.0
20.1
20.4
11.4
12.5
12.5
12.6
32 MHz
12.4
13.2
13.2
13.8
7.9
8.3
8.5
8.6
24 MHz
9.9
10.7
10.7
11.0
6.2
6.8
7.0
7.0
8 MHz
3.3
3.6
3.8
3.9
2.2
2.6
2.6
2.6
1 MHz
0.8
1.1
1.1
1.1
0.7
0.9
0.9
0.9
48 MHz
18.9
20.9
21.1
21.5
11.7
12.3
12.9
13.1
32 MHz
12.8
13.7
14.2
14.8
8.0
8.7
9.1
9.1
24 MHz
9.7
10.4
11.2
11.3
6.1
6.5
6.7
6.9
8 MHz
3.5
4.0
4.0
4.1
2.4
2.6
2.7
2.7
48 MHz
17.3
19.7
19.8
20.0
10.3
11.2
11.3
11.7
32 MHz
11.2
12.5
12.7
12.7
6.7
7.3
7.6
7.6
24 MHz
8.9
10.0
10.1
10.2
5.1
5.5
5.8
5.9
8 MHz
2.8
3.1
3.3
3.4
1.7
2.0
2.1
2.1
1 MHz
0.3
0.6
0.6
1.3
0.2
0.5
0.8
0.8
48 MHz
17.4
19.7
20.0
20.2
10.4
11.2
11.3
11.8
32 MHz
11.8
12.8
13.1
13.3
6.8
7.4
7.7
7.9
24 MHz
9.0
10.0
10.1
10.2
5.2
5.7
6.0
6.0
8 MHz
3.0
3.2
3.5
3.6
1.8
2.0
2.2
2.2
48 MHz
10.7
11.7
11.9
12.5
2.4
2.6
2.7
2.9
32 MHz
7.1
7.8
8.1
8.2
1.6
1.7
1.9
1.9
24 MHz
5.5
6.3
6.4
6.4
1.3
1.4
1.5
1.5
8 MHz
1.8
2.0
2.0
2.1
0.4
0.4
0.5
0.5
1 MHz
0.2
0.5
0.5
0.5
0.1
0.1
0.1
0.1
48 MHz
10.8
11.9
12.1
12.6
2.4
2.7
2.7
2.9
32 MHz
7.3
8.0
8.4
8.5
1.7
1.9
1.9
2.0
24 MHz
5.5
6.2
6.5
6.5
1.3
1.5
1.5
1.6
8 MHz
1.9
2.2
2.3
2.4
0.5
0.5
0.5
0.6
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mA
43/97
Electrical characteristics
Table 21.
STM32F050xx
Typical and maximum current consumption from the VDDA supply
VDDA = 2.4 V
Symbol Parameter
Conditions
(1)
VDDA = 3.6 V
Max @ TA(2)
fHCLK
Max @ TA(2)
25 °C
HSE
bypass,
PLL on
Supply
current in
Run mode,
code
executing
from Flash
or RAM
HSE
bypass,
PLL off
HSI clock,
PLL on
HSI clock,
PLL off
IDDA
Unit
Typ
Typ
85 °C 105 °C
25 °C
85 °C 105 °C
48 MHz
150
170
178
182
164
183
195
198
32 MHz
104
121
126
128
113
129
135
138
24 MHz
82
96
100
103
88
102
106
108
8 MHz
2.0
2.7
3.1
3.3
3.5
3.8
4.1
4.4
1 MHz
2.0
2.7
3.1
3.3
3.5
3.8
4.1
4.4
48 MHz
220
240
248
252
244
263
275
278
32 MHz
174
191
196
198
193
209
215
218
24 MHz
152
167
173
174
168
183
190
192
8 MHz
72
79
82
83
83.5
91
94
95
48 MHz
150
170
178
182
164
183
195
198
32 MHz
104
121
126
128
113
129
135
138
24 MHz
82
96
100
103
88
102
106
108
8 MHz
2.0
2.7
3.1
3.3
3.5
3.8
4.1
4.4
1 MHz
2.0
2.7
3.1
3.3
3.5
3.8
4.1
4.4
48 MHz
220
240
248
252
244
263
275
278
32 MHz
174
191
196
198
193
209
215
218
24 MHz
152
167
173
174
168
183
190
192
8 MHz
72
79
82
83
83.5
91
94
95
µA
HSE
bypass,
PLL on
Supply
current in
Sleep
mode,
code
executing
from Flash
or RAM
HSE
bypass,
PLL off
HSI clock,
PLL on
HSI clock,
PLL off
1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the
PLL is off, IDDA is independent from the frequency.
2. Data based on characterization results, not tested in production.
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Doc ID 023683 Rev 1
STM32F050xx
Table 22.
Electrical characteristics
Typical and maximum VDD consumption in Stop and Standby modes
Symbol Parameter
IDD
Max(1)
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
TA = TA = TA =
25 °C 85 °C 105 °C
Conditions
Regulator in run mode,
all oscillators OFF
Supply
current in Regulator in low-power
Stop mode mode, all oscillators
OFF
Supply
current in
Standby
mode
Typ @VDD (VDD = VDDA)
15
15.1 15.25 15.45 15.7
3.15 3.25 3.35 3.45
3.7
16
18(2)
38
55(2)
4
5.5(2)
22
41(2)
Unit
µA
LSI ON and IWDG ON
0.8
0.95 1.05
1.2
1.35
1.5
-
-
-
LSI OFF and IWDG
OFF
0.65 0.75 0.85 0.95
1.1
1.3
2(2)
2.5
3(2)
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production.
Table 23.
upply current
Typical and maximum VDDA consumption in Stop and Standby modes
Supply
current in
Stop mode
Supply
current in
Standby
mode
Supply
current in
Standby
mode
VDDA monitoring OFF
IDDA
Supply
current in
Stop mode
Max(1)
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
TA = TA = TA =
25 °C 85 °C 105 °C
Conditions
VDDA monitoring ON
Symbol Parameter
Typ @VDD (VDD = VDDA)
Regulator in run mode,
1.85
all oscillators OFF
2
2.15
2.3
2.45
2.6
3.5
3.5
4.5
Regulator in low-power
mode, all oscillators
1.85
OFF
2
2.15
2.3
2.45
2.6
3.5
3.5
4.5
LSI ON and IWDG ON 2.25
2.5
2.65 2.85 3.05
3.3
-
-
-
LSI OFF and IWDG
OFF
1.9
2.5
3.5
3.5
4.5
Regulator in run mode,
1.11 1.15 1.18 1.22 1.27 1.35
all oscillators OFF
-
-
-
Regulator in low-power
mode, all oscillators
1.11 1.15 1.18 1.22 1.27 1.35
OFF
-
-
-
LSI ON and IWDG ON
LSI OFF and IWDG
OFF
1.75
2
2.15
2.3
Unit
µA
1.5
1.58 1.65 1.78 1.91 2.04
-
-
-
1
1.02 1.05 1.05 1.15 1.22
-
-
-
1. Data based on characterization results, not tested in production.
Doc ID 023683 Rev 1
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Electrical characteristics
Table 24.
STM32F050xx
Typical and maximum current consumption from VBAT supply
Max(1)
Backup
domain
IDD_VBAT
supply
current
= 3.6 V
= 3.3 V
= 2.7 V
Conditions
= 2.4 V
Parameter
= 1.8 V
Symbol
= 1.65 V
Typ @ VBAT
LSE & RTC ON; “Xtal
mode”: lower driving
0.41 0.43 0.53 0.58 0.71 0.80
capability;
LSEDRV[1:0] = '00'
TA =
25 °C
TA =
85 °C
TA =
105 °C
0.85
1.1
1.5
Unit
µA
LSE & RTC ON; “Xtal
mode” higher driving
0.71 0.75 0.85 0.91 1.06 1.16
capability;
LSEDRV[1:0] = '11'
1.25
1.55
2
1. Data based on characterization results, not tested in production.
Typical current consumption
The MCU is placed under the following conditions:
46/97
●
VDD=VDDA=3.3 V
●
All I/O pins are in analog input configuration
●
The Flash access time is adjusted to fHCLK frequency (0 wait states from 0 to 24 MHz,
1 wait state above)
●
Prefetch is ON when the peripherals are enabled, otherwise it is OFF
●
When the peripherals are enabled, fPCLK = fHCLK
●
PLL is used for frequencies greater than 8 MHz
●
AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
●
A development tool is connected to the board and the parasitic pull-up current is around
30 µA
Doc ID 023683 Rev 1
STM32F050xx
Table 25.
Electrical characteristics
Typical current consumption in Run mode, code with data processing
running from Flash
Typ
Symbol
IDD
Parameter
Conditions
Supply current in Run
mode from VDD
supply
Running from
HSE crystal
clock 8 MHz,
code
executing
from Flash
IDDA
Supply current in Run
mode from VDDA
supply
fHCLK
Peripherals
enabled
Peripherals
disabled
48 MHz
18.4
11.4
36 MHz
13.9
8.9
32 MHz
12.4
7.9
24 MHz
9.9
6.2
16 MHz
6.6
4.3
8 MHz
3.3
2.2
4 MHz
1.7
1.6
2 MHz
1.3
1.2
1 MHz
0.8
0.7
500 kHz
0.6
0.6
48 MHz
140
140
36 MHz
109
109
32 MHz
96
96
24 MHz
76
76
16 MHz
51
51
8 MHz
1.7
1.7
4 MHz
1.6
1.6
2 MHz
1.5
1.5
1 MHz
1.1
1.1
500 kHz
1.1
1.1
Doc ID 023683 Rev 1
Unit
mA
µA
47/97
Electrical characteristics
Table 26.
STM32F050xx
Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ
Symbol
IDD
Parameter
Conditions
Supply current in
Sleep mode from VDD
supply
Running from
HSE crystal
clock 8 MHz,
code executing
from Flash or
RAM
IDDA
48/97
Supply current in
Sleep mode from
VDDA supply
fHCLK
Peripherals Peripherals
enabled
disabled
48 MHz
10.7
2.4
36 MHz
8.1
1.8
32 MHz
7.1
1.6
24 MHz
5.5
1.3
16 MHz
3.7
0.9
8 MHz
1.9
0.5
4 MHz
1.5
0.4
2 MHz
1.1
0.3
1 MHz
0.8
0.3
500 kHz
0.6
0.3
125 kHz
0.5
0.3
48 MHz
140
140
36 MHz
109
109
32 MHz
96
96
24 MHz
76
76
16 MHz
51
51
8 MHz
1.7
1.7
4 MHz
1.6
1.6
2 MHz
1.5
1.5
1 MHz
1.1
1.1
500 kHz
1.1
1.1
125 kHz
1.1
1.1
Doc ID 023683 Rev 1
Unit
mA
µA
STM32F050xx
Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 45: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 28: Peripheral current consumption), the I/Os used by an application also contribute to
the current consumption. When an I/O pin switches, it uses the current from the MCU supply
voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or
external) connected to the pin:
I SW = V DD × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
Doc ID 023683 Rev 1
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Electrical characteristics
Table 27.
Symbol
STM32F050xx
Switching output I/O current consumption
Parameter
Conditions(1)
VDD = 3.3 V
C =CINT
VDD = 3.3 V
CEXT = 0 pF
C = CINT + CEXT+ CS
VDD = 3.3 V
CEXT = 10 pF
C = CINT + CEXT+ CS
ISW
I/O current
consumption
VDD = 3.3 V
CEXT = 22 pF
C = CINT + CEXT+ CS
VDD = 3.3 V
CEXT = 33 pF
C = CINT + CEXT+ CS
VDD = 3.3 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
VDD = 2.4 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
1. CS = 7 pF (estimated value).
50/97
Doc ID 023683 Rev 1
I/O toggling
frequency (fSW)
Typ
4 MHz
0.07
8 MHz
0.15
16 MHz
0.31
24 MHz
0.53
48 MHz
0.92
4 MHz
0.18
8 MHz
0.37
16 MHz
0.76
24 MHz
1.39
48 MHz
2.188
4 MHz
0.32
8 MHz
0.64
16 MHz
1.25
24 MHz
2.23
48 MHz
4.442
4 MHz
0.49
8 MHz
0.94
16 MHz
2.38
24 MHz
3.99
4 MHz
0.64
8 MHz
1.25
16 MHz
3.24
24 MHz
5.02
4 MHz
0.81
8 MHz
1.7
16 MHz
3.67
4 MHz
0.66
8 MHz
1.43
16 MHz
2.45
24 MHz
4.97
Unit
mA
STM32F050xx
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 28. The MCU is placed
under the following conditions:
●
all I/O pins are in input mode with a static value at VDD or VSS (no load)
●
all peripherals are disabled unless otherwise mentioned
●
the given value is calculated by measuring the current consumption
●
–
with all peripherals clocked off
–
with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in
Table 12: Voltage characteristics
Table 28.
Peripheral current consumption
Typical consumption at 25 °C
Peripheral
Unit
IDD
IDDA
ADC(1)
0.53
0.964
CRC
0.10
-
DBGMCU
0.18
-
DMA
0.35
-
GPIOA
0.48
-
GPIOB
0.58
-
GPIOC
0.12
-
GPIOF
0.06
-
I2C1
0.43
-
PWR
0.22
-
SPI1/I2S1
0.63
-
SYSCFG
0.28
TIM1
1.01
-
TIM2
1.00
-
TIM3
0.78
-
TIM6
0.32
-
TIM14
0.45
-
TIM16
0.57
-
TIM17
0.59
-
USART1
1.07
-
WWDG
0.22
-
mA
1. ADC is in ready state after setting the ADEN bit in the ADC_CR register (ADRDY bit in ADC_ISR is high).
Doc ID 023683 Rev 1
51/97
Electrical characteristics
6.3.6
STM32F050xx
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,
the recommended clock input waveform is shown in Figure 12: High-speed external clock
source AC timing diagram.
Table 29.
High-speed external user clock characteristics
Parameter(1)
Symbol
Conditions
Min
Typ
Max
Unit
1
8
32
MHz
fHSE_ext
User external clock source
frequency
VHSEH
OSC_IN input pin high level voltage
0.7VDD
-
VDD
VHSEL
OSC_IN input pin low level voltage
VSS
-
0.3VDD
15
-
-
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
tr(HSE)
tf(HSE)
OSC_IN rise or fall time
V
ns
-
-
20
1. Guaranteed by design, not tested in production.
Figure 12. High-speed external clock source AC timing diagram
T7(3%(
6(3%(
6(3%,
TR(3%
TF(3%
T7(3%,
T
4(3%
-36
52/97
Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,
the recommended clock input waveform is shown in Figure 13.
Table 30.
Low-speed external user clock characteristics
Parameter(1)
Symbol
Conditions
Min
Typ
Max
Unit
-
32.768
1000
kHz
fLSE_ext
User External clock source
frequency
VLSEH
OSC32_IN input pin high level
voltage
0.7VDD
-
VDD
VLSEL
OSC32_IN input pin low level
voltage
VSS
-
0.3VDD
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time
450
-
-
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time
-
-
50
V
ns
1. Guaranteed by design, not tested in production.
Figure 13. Low-speed external clock source AC timing diagram
T7,3%(
6,3%(
6,3%,
TR,3%
TF,3%
T7,3%,
T
4,3%
-36
Doc ID 023683 Rev 1
53/97
Electrical characteristics
STM32F050xx
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 31. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 31.
Symbol
fOSC_IN
RF
HSE oscillator characteristics
Parameter
Conditions(1)
gm
tSU(HSE)(4)
Typ
Max(2)
Unit
4
8
32
MHz
-
200
-
kΩ
Oscillator frequency
Feedback resistor
During startup
IDD
Min(2)
HSE current consumption
Oscillator transconductance
Startup time
(3)
-
8.5
VDD=3.3 V, Rm= 30Ω,
CL=10 [email protected] MHz
-
0.4
-
VDD=3.3 V, Rm= 45Ω,
CL=10 [email protected] MHz
-
0.5
-
VDD=3.3 V, Rm= 30Ω,
CL=5 [email protected] MHz
-
0.8
-
VDD=3.3 V, Rm= 30Ω,
CL=10 [email protected] MHz
-
1
-
VDD=3.3 V, Rm= 30Ω,
CL=20 [email protected] MHz
-
1.5
-
Startup
10
-
-
mA/V
VDD is stabilized
-
2
-
ms
mA
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 14). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note:
54/97
For information on electing the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
Figure 14. Typical application with an 8 MHz crystal
2ESONATORWITH
INTEGRATEDCAPACITORS
#,
F(3%
/3#?).
-( Z
RESONATOR
#,
2%84
2&
"IAS
CONTROLLED
GAIN
/3#?/5 4
-36
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 32. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 32.
Symbol
IDD
gm
LSE oscillator characteristics (fLSE = 32.768 kHz)
Parameter
Conditions(1)
Min(2)
Typ
Max(2) Unit
LSEDRV[1:0]=00
lower driving capability
-
0.5
0.9
LSEDRV[1:0]= 01
medium low driving capability
-
-
1
LSEDRV[1:0] = 10
medium high driving capability
-
-
1.3
LSEDRV[1:0]=11
higher driving capability
-
-
1.6
LSEDRV[1:0]=00
lower driving capability
5
-
-
LSEDRV[1:0]= 01
medium low driving capability
8
-
-
LSEDRV[1:0] = 10
medium high driving capability
15
-
-
LSEDRV[1:0]=11
higher driving capability
25
-
-
VDD is stabilized
-
2
-
LSE current consumption
Oscillator
transconductance
tSU(LSE)(3) Startup time
µA
µA/V
s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Doc ID 023683 Rev 1
55/97
Electrical characteristics
STM32F050xx
Figure 15. Typical application with a 32.768 kHz crystal
2ESONATORWITH
INTEGRATEDCAPACITORS
#,
F,3%
/3#?).
$RIVE
PROGRAMMABLE
AMPLIFIER
K( Z
RESONATOR
#,
/3#?/5 4
-36
Note:
56/97
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
Doc ID 023683 Rev 1
STM32F050xx
6.3.7
Electrical characteristics
Internal clock source characteristics
The parameters given in Table 33 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 15: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI) RC oscillator
Table 33.
HSI oscillator characteristics(1)
Symbol
fHSI
TRIM
DuCy(HSI)
ACCHSI
Parameter
Conditions
Min
Typ
Frequency
-
8
HSI user trimming step
-
-
1(2)
%
-
55(2)
%
%
45(2)
Duty cycle
Accuracy of the HSI
oscillator (factory
calibrated)
Max
Unit
MHz
TA = –40 to 105 °C
–3.8(3)
-
4.6(3)
TA = –10 to 85 °C
–2.9(3)
-
2.9(3)
%
TA = 0 to 70 °C
–2.3(3)
-
2.2(3)
%
–1
-
1
%
TA = 25 °C
tsu(HSI)
HSI oscillator startup
time
1(2)
-
2(2)
µs
IDDA(HSI)
HSI oscillator power
consumption
-
80
100(2)
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 16. HSI oscillator accuracy characterization results
-!8
-).
4!; #=
-36
Doc ID 023683 Rev 1
57/97
Electrical characteristics
STM32F050xx
High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)
Table 34.
HSI14 oscillator characteristics(1)
Symbol
fHSI14
TRIM
Parameter
Conditions
Frequency
HSI14 user-trimming step
Min
Typ
-
14
-
DuCy(HSI14) Duty cycle
45
Accuracy of the HSI14
oscillator (factory calibrated)
TA = –10 to 85 °C
TA = 25 °C
tsu(HSI14)
IDDA(HSI14)
HSI14 oscillator startup time
HSI14 oscillator power
consumption
%
1
-
55
(2)
%
(3)
-
5.1
%
–3.2(3)
-
3.1(3)
%
–2.5
-
(3)
2.3
%
–1
(3)
TA = 0 to 70 °C
MHz
(3)
TA = –40 to 105 °C –4.2
ACCHSI14
Unit
(2)
-
(2)
Max
-
1
%
1(2)
-
2(2)
µs
-
100
150(2)
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 17. HSI14 oscillator accuracy characterization results
-!8
-).
4!; #=
-36
58/97
Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
Low-speed internal (LSI) RC oscillator
Table 35.
LSI oscillator characteristics(1)
Symbol
fLSI
Min
Typ
Max
Unit
30
40
50
kHz
LSI oscillator startup time
-
-
85
µs
LSI oscillator power consumption
-
0.75
1.2
µA
Frequency
tsu(LSI)(2)
IDDA(LSI)
Parameter
(2)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 36 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The event used to wake up the device depends from the current operating mode:
●
Stop or sleep mode: the wakeup event is WFE.
●
The wakeup pin used in sleep, stop and standby modes is PA0.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 15: General operating conditions.
Table 36.
Low-power mode wakeup timings
Typ @VDD
Symbol
Parameter
Conditions
Max Unit
= 2.0 V = 2.4 V = 2.7 V
tWUSTOP
Wakeup from Stop
mode
=3V
= 3.3 V
Regulator in run
mode
4.2
4.2
4.2
4.2
4.2
5
Regulator in low
power mode
8.05
7.05
6.6
6.27
6.05
9
60.35
55.6
53.5
52.02
50.96
1.1
1.1
1.1
1.1
1.1
µs
tWUSTANDBY Wakeup from
Standby mode
tWUSLEEP
Wakeup from Sleep
mode
Doc ID 023683 Rev 1
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Electrical characteristics
6.3.8
STM32F050xx
PLL characteristics
The parameters given in Table 37 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 15: General operating
conditions.
Table 37.
PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max
PLL input clock(1)
1(2)
8.0
24(2)
PLL input clock duty cycle
40(2)
-
fPLL_OUT
PLL multiplier output clock
16(2)
-
48
MHz
tLOCK
PLL lock time
-
-
200(2)
µs
-
300(2)
ps
fPLL_IN
JitterPLL
Cycle-to-cycle jitter
-
MHz
(2)
60
%
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT.
2. Guaranteed by design, not tested in production.
60/97
Doc ID 023683 Rev 1
STM32F050xx
6.3.9
Electrical characteristics
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 38.
Flash memory characteristics
Min
Typ
Max(1)
Unit
16-bit programming time TA = –40 to +105 °C
40
53.5
60
µs
Page (1 KB) erase time
TA = –40 to +105 °C
20
-
40
ms
tME
Mass erase time
TA = –40 to +105 °C
20
-
40
ms
Write mode
-
-
10
mA
IDD
Supply current
Erase mode
-
-
12
mA
Symbol
tprog
tERASE
Parameter
Conditions
1. Guaranteed by design, not tested in production.
Table 39.
Flash memory endurance and data retention
Value
Symbol
NEND
tRET
Parameter
Endurance
Data retention
Conditions
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
10
1 kcycle(2) at TA = 85 °C
30
1 kcycle
10
(2)
at TA = 105 °C
kcycles(2)
at TA = 55 °C
Unit
Min(1)
10
kcycles
Years
20
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
6.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 40. They are based on the EMS levels and classes
defined in application note AN1709.
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Electrical characteristics
Table 40.
STM32F050xx
EMS characteristics
Symbol
Parameter
Level/
Class
Conditions
VFESD
VDD = 3.3 V, LQFP64, TA = +25 °C,
Voltage limits to be applied on any I/O pin to
fHCLK = 48 MHz
induce a functional disturbance
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP64, TA = +25 °C,
fHCLK = 48 MHz
conforms to IEC 61000-4-4
3B
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
Corrupted program counter
●
Unexpected reset
●
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 41.
Symbol
SEMI
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EMI characteristics
Parameter
Peak level
Conditions
Monitored
frequency band
0.1 to 30 MHz
VDD = 3.6 V, TA = 25 °C,
30 to 130 MHz
LQFP64 package
compliant with IEC
130 MHz to 1GHz
61967-2
SAE EMI Level
Doc ID 023683 Rev 1
Max vs. [fHSE/fHCLK]
Unit
8/48 MHz
-3
28
dBµV
23
4
-
STM32F050xx
6.3.11
Electrical characteristics
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 42.
ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class Maximum value(1) Unit
VESD(HBM)
Electrostatic discharge
TA = +25 °C, conforming
voltage (human body model) to JESD22-A114
2
2000
VESD(CDM)
Electrostatic discharge
TA = +25 °C, conforming
voltage (charge device model) to JESD22-C101
II
500
V
1. Data based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 43.
Symbol
LU
6.3.12
Electrical sensitivities
Parameter
Conditions
Static latch-up class
TA = +105 °C conforming to JESD78A
Class
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (more
than 5 LSB TUE), out of conventional limits of current injection on adjacent pins (more than
–5 µA) or other functional failure (reset occurrence or oscillator frequency deviation, for
example).
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Electrical characteristics
STM32F050xx
The characterization results are given in Table 44.
Table 44. I/O current injection susceptibility
Functional
susceptibility
Symbol
IINJ
64/97
Description
Unit
Negative
injection
Positive
injection
Injected current on BOOT0
–0
NA
Injected current on all FT and FTf pins with induced
leakage current on adjacent pins less than –5 µA
–5
NA
Injected current on all TTa pins with induced leakage
current on adjacent pins less than –5 µA
–5
+5
Injected current on all TC & RESET pins with induced
leakage current on adjacent pins less than –5 µA
–5
+5
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mA
STM32F050xx
6.3.13
Electrical characteristics
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the conditions summarized in Table 15: General operating conditions. All
I/Os are CMOS and TTL compliant.
Table 45.
Symbol
VIL
I/O static characteristics
Parameter
Low level input
voltage
Conditions
High level input
voltage
Vhys
Ilkg
RPU
Weak pull-up
equivalent
resistor(3)
Unit
(1)
-
0.3 VDD+0.07
FT and FTf I/O
-
-
0.475 VDD–0.2(1)
BOOT0
-
-
0.3 VDD–0.3(1)
All I/Os except BOOT0 pin
-
-
0.3 VDD
-
-
0.5 VDD+0.2(1)
-
-
+0.95(1)
-
-
0.445
FT and FTf I/O
BOOT0
VDD+0.398(1)
0.2 VDD
0.7 VDD
V
V
-
(1)
-
TC and TTa I/O
-
200
FT and FTf I/O
-
100(1)
-
-
(1)
300
-
VSS ≤VIN ≤VDD
I/O TC, FT and FTf
-
-
±0.1
VSS ≤VIN ≤VDD
2 V≤VDD ≤VDDA ≤3.6 V
I/O TTa used in digital
mode
-
-
±0.1
VIN= 5 V
I/O FT and FTf
-
-
10
BOOT0
Input leakage
current (2)
Max
-
All I/Os except BOOT0 pin
Schmitt trigger
hysteresis
Typ
TC and TTa I/O
TC and TTa I/O
VIH
Min
mV
µA
VIN= 3.6 V,
2 V≤VDD ≤VIN
VDDA = 3.6 V
I/O TTa used in digital
mode
-
-
1
VSS ≤VIN ≤VDDA
2 V≤VDD ≤VDDA ≤3.6 V
I/O TTa used in analog
mode
-
-
±0.2
VIN = VSS
25
40
55
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Electrical characteristics
Table 45.
Symbol
STM32F050xx
I/O static characteristics (continued)
Parameter
RPD
Weak pull-down
equivalent
resistor(3)
CIO
I/O pin
capacitance
Conditions
Min
Typ
Max
Unit
VIN = VDD
25
40
55
kΩ
-
5
-
pF
1. Data based on design simulation only. Not tested in production.
2. Leakage could be higher than maximum value, if negative current is injected on adjacent pins.
3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
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STM32F050xx
Electrical characteristics
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 18 and Figure 19 for standard I/Os, and
in Figure 20 and Figure 21 for 5 V tolerant I/Os. The following curves are design simulation
results, not tested in production.
Figure 18. TC and TTa I/O input characteristics - CMOS port
VIL/VIH (V)
V DD
ard
tand
Ss
CMO
VIHmin 2.0
nts
eme
V IHmin
= 0.7
ir
requ
98
+0.3
45V DD
V IHmin
= 0.4
0.07
V DD+
= 0.3
V ILmax
1.3
Input range not
guaranteed
CMOS standard requirements VILmax = 0.3VDD
VILmax 0.7
0.6
VDD (V)
2.0
2.7
3.0
3.3
3.6
MS30255V1
Figure 19. TC and TTa I/O input characteristics - TTL port
VIL/VIH (V)
98
+0.3
45V DD
= 0.4
min
TTL standard requirements VIHmin = 2 V
V IH
VIHmin 2.0
x=
V ILma
1.3
0.07
D+
0.3V D
Input range not
guaranteed
VILmax 0.8
0.7
TTL standard requirements VILmax = 0.8 V
VDD (V)
2.0
2.7
3.0
3.3
3.6
MS30256V1
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Electrical characteristics
STM32F050xx
Figure 20. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port
VIL/VIH (V)
CMOS standard requirements VIH min= 0.7VDD
2.0
= 0.5
-0.2
75V DD
Input range not
guaranteed
1.0
0.2
V DD+
V IHmin
= 0.4
V ILmax
CMOS standard requirements VILmax = 0.3VDD
0.5
VDD (V)
2.0
3.6
MS30257V1
Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port
VIL/VIH (V)
TTL standard requirements VIHmin = 2 V
2.0
Input range not
guaranteed
1.0
0.2
V DD+
V IHmin
= 0.5
-0.2
75V DD
V ILmin
= 0.4
0.8
TTL standard requirements VILmax = 0.8 V
0.5
VDD (V)
2.0
2.7
3.6
MS30258V1
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STM32F050xx
Electrical characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
●
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 13: Current characteristics).
●
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 13: Current characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 15: General operating conditions. All I/Os are CMOS and TTL compliant (FT, TTa or
TC unless otherwise specified).
Table 46.
Symbol
Output voltage characteristics
Parameter
VOL(1)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOL (1)
Output low level voltage for an I/O pin
VOH (3)
Output high level voltage for an I/O pin
VOL(1)(4)
Output low level voltage for an I/O pin
VOH(3)(4)
Output high level voltage for an I/O pin
VOL(1)(4)
Output low level voltage for an I/O pin
VOH
(3)(4)
VOLFM+(1)
Conditions
Min
CMOS port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
-
0.4
VDD–0.4
-
-
0.4
2.4
-
-
1.3
VDD–1.3
-
-
0.4
VDD–0.4
-
-
0.4
V
TTL port(2)
IIO =+ 8mA
2.7 V < VDD < 3.6 V
IIO = +20 mA
2.7 V < VDD < 3.6 V
Output high level voltage for an I/O pin
IIO = +6 mA
2 V < VDD < 2.7 V
Output low level voltage for an FTf I/O
pin in FM+ mode
IIO = +20 mA
2.7 V < VDD < 3.6 V
Max Unit
V
V
V
V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 13:
Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 13: Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Data based on design simulation only. Not tested in production.
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Electrical characteristics
STM32F050xx
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 22 and
Table 47, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 15: General
operating conditions.
Table 47.
I/O AC characteristics(1)
OSPEEDRy
[1:0] value(1)
Symbol
Parameter
fmax(IO)out Maximum frequency(2)
x0
tf(IO)out
Output high to low level
fall time
tr(IO)out
Output low to high level
rise time
fmax(IO)out Maximum frequency(2)
01
tf(IO)out
Output high to low level
fall time
tr(IO)out
Output low to high level
rise time
fmax(IO)out Maximum
11
tf(IO)out
tr(IO)out
frequency(2)
Output high to low level
fall time
Output low to high level
rise time
fmax(IO)out Maximum frequency(2)
FM+
configuration
tf(IO)out
Output high to low level
fall time
tr(IO)out
Output low to high level
rise time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
Conditions
Min
Max
Unit
-
2
MHz
-
125(3)
-
125(3)
-
10
-
25(3)
-
25(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
50
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
30
CL = 50 pF, VDD = 2 V to 2.7 V
-
20
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
12(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
12(3)
CL = 50 pF, VDD = 2 V to 3.6 V
-
2(3)
CL = 50 pF, VDD = 2 V to 3.6 V
-
12(3)
-
34(3)
10
-
CL = 50 pF, VDD = 2 V to 3.6 V
CL = 50 pF, VDD = 2 V to 3.6 V
CL = 50 pF, VDD = 2 V to 3.6 V
ns
CL = 50 pF, VDD = 2 V to 3.6 V
MHz
ns
MHz
ns
MHz
ns
(4)
CL = 50 pF, VDD = 2 V to 3.6 V
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0091 reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 22.
3. Guaranteed by design, not tested in production.
4. When FM+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F05xxx reference manual RM0091
for a detailed description of FM+ I/O configuration.
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STM32F050xx
Electrical characteristics
Figure 22. I/O AC characteristics definition
90%
10%
50%
50%
90%
10%
EXT ERNAL
OUTPUT
ON 50pF
tr(I O)out
tr(I O)out
T
Maximum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131
6.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 45: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 48 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 15: General operating conditions.
Table 48.
NRST pin characteristics
Symbol
Min
Typ
Max
–0.3
-
0.8
VIH(NRST)(1) NRST input high level voltage
2
-
VDD+0.3
NRST Schmitt trigger voltage
hysteresis
-
200
-
mV
25
40
55
kΩ
-
-
100
ns
300
-
-
ns
VIL(NRST)(1)
Vhys(NRST)
RPU
Parameter
Conditions
NRST input low level voltage
Weak pull-up equivalent resistor(2)
VF(NRST)(1)
NRST input filtered pulse
VNF(NRST)(1)
NRST input not filtered pulse
Unit
V
VIN = VSS
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
Figure 23. Recommended NRST pin protection
6$$
%XTERNAL
RESETCIRCUIT
.234
205
)NTERNAL2ESET
&ILTER
—&
-36
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 48. Otherwise the reset will not be taken into account by the device.
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Electrical characteristics
6.3.15
STM32F050xx
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 49 are preliminary values derived
from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 15: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
Table 49.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog supply voltage for
ADC ON
2.4
-
3.6
V
fADC
ADC clock frequency
0.6
-
14
MHz
fS(1)
Sampling rate
0.05
-
1
MHz
-
-
823
kHz
-
-
17
1/fADC
0
-
VDDA
V
-
-
50
kΩ
fADC = 14 MHz
fTRIG(1)
External trigger frequency
VAIN
Conversion voltage range
RAIN(1)
External input impedance
RADC(1)
Sampling switch resistance
-
-
1
kΩ
CADC(1)
Internal sample and hold
capacitor
-
-
8
pF
tCAL(1)
Calibration time
tlatr(1)
JitterADC
Trigger conversion latency
fADC = 14 MHz
5.9
µs
83
1/fADC
fADC = fPCLK/2 = 14 MHz
0.196
µs
fADC = fPCLK/2
5.5
1/fPCLK
fADC = fPCLK/4 = 12 MHz
0.219
µs
fADC = fPCLK/4
10.5
1/fPCLK
fADC = fHSI14 = 14 MHz
0.188
-
0.259
µs
fADC = fHSI14
-
1
-
1/fHSI14
fADC = 14 MHz
0.107
-
17.1
µs
1.5
-
239.5
1/fADC
0
0
1
µs
18
µs
ADC jitter on trigger
conversion
tS(1)
Sampling time
tSTAB(1)
Power-up time
tCONV(1)
See Equation 1 and
Table 50 for details
Total conversion time
(including sampling time)
fADC = 14 MHz
14 to 252 (tS for sampling +12.5 for
successive approximation)
1. Guaranteed by design, not tested in production.
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1/fADC
STM32F050xx
Electrical characteristics
Equation 1: RAIN max formula
TS
R AIN < --------------------------------------------------------------- – R ADC
N+2
f ADC × C ADC × ln ( 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 50.
RAIN max for fADC = 14 MHz(1)
Ts (cycles)
tS (µs)
RAIN max (kΩ)
1.5
0.11
0.4
7.5
0.54
5.9
13.5
0.96
11.4
28.5
2.04
25.2
41.5
2.96
37.2
55.5
3.96
50
71.5
5.11
NA
239.5
17.1
NA
1. Guaranteed by design, not tested in production.
Table 51.
Symbol
ADC accuracy(1)(2) (3)
Parameter
Test conditions
Typ
Max(4)
±1.3
±2
±1
±1.5
±0.5
±1.5
±0.7
±1
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
±0.8
±1.5
ET
Total unadjusted error
±3.3
±4
EO
Offset error
±1.9
±2.8
EG
Gain error
±2.8
±3
ED
Differential linearity error
±0.7
±1.3
EL
Integral linearity error
±1.2
±1.7
ET
Total unadjusted error
±3.3
±4
EO
Offset error
±1.9
±2.8
EG
Gain error
±2.8
±3
ED
Differential linearity error
±0.7
±1.3
EL
Integral linearity error
±1.2
±1.7
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 3 V to 3.6 V
TA = 25 °C
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 2.7 V to 3.6 V
TA = −40 to 105 °C
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 2.4 V to 3.6 V
TA = 25 °C
Unit
LSB
LSB
LSB
1. ADC DC accuracy values are measured after internal calibration.
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Electrical characteristics
STM32F050xx
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not
affect the ADC accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
Figure 24. ADC accuracy characteristics
VDDA
1 LSBIDEAL EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4095
4094
4093
(2)
ET
7
(1)
6
5
4
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
(3)
EO
EL
3
ED
2
1 LSBIDEAL
1
0
1
VSSA
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
-36
Figure 25. Typical connection diagram using the ADC
6$$!
RAIN(1)
VAIN
Sample and hold ADC
converter
VT
0.6 V
RADC
AINx
Cparasitic
VT
0.6 V
IL±1 μA
12-bit
converter
CADC
-36
1. Refer to Table 49: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 10. The 10 nF capacitor
should be ceramic (good quality) and it should be placed as close as possible to the chip.
74/97
Doc ID 023683 Rev 1
STM32F050xx
6.3.16
Electrical characteristics
Temperature sensor characteristics
Table 52.
TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
-
±1
±2
°C
Average slope
4.0
4.3
4.6
mV/°C
V25
Voltage at 25 °C
1.34
1.43
1.52
V
tSTART(1)
Startup time
4
-
10
µs
TS_temp(1)(2)
ADC sampling time when reading the
temperature
17.1
-
-
µs
TL(1)
VSENSE linearity with temperature
Avg_Slope
(1)
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.17
VBAT monitoring characteristics
Table 53.
VBAT monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
KΩ
R
Resistor bridge for VBAT
-
50
-
Q
Ratio on VBAT measurement
-
2
-
Error on Q
–1
-
+1
%
ADC sampling time when reading the VBAT
1mV accuracy
5
-
-
µs
Er(1)
TS_vbat(1)(2)
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.18
Timer characteristics
The parameters given in Table 54 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 54.
Symbol
tres(TIM)
fEXT
ResTIM
TIMx(1) characteristics
Parameter
Conditions
Min
Max
Unit
1
-
tTIMxCLK
20.8
-
ns
0
fTIMxCLK/2
MHz
0
24
MHz
TIMx (except TIM2)
-
16
TIM2
-
32
Timer resolution time
fTIMxCLK = 48 MHz
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 48 MHz
Timer resolution
bit
Doc ID 023683 Rev 1
75/97
Electrical characteristics
Table 54.
STM32F050xx
TIMx(1) characteristics (continued)
Symbol
Parameter
tCOUNTER
16-bit counter clock period
tMAX_COUNT
Conditions
fTIMxCLK = 48 MHz
Maximum possible count
with 32-bit counter
fTIMxCLK = 48 MHz
Min
Max
Unit
1
65536
tTIMxCLK
0.0208
1365
µs
-
65536 × 65536
tTIMxCLK
-
89.48
s
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM6, TIM14, TIM15, TIM16 and TIM17
timers.
Table 55.
IWDG min/max timeout period at 40 kHz (LSI) (1)
Prescaler divider
PR[2:0] bits
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
/4
0
0.1
409.6
/8
1
0.2
819.2
/16
2
0.4
1638.4
/32
3
0.8
3276.8
/64
4
1.6
6553.6
/128
5
3.2
13107.2
/256
6 or 7
6.4
26214.4
Unit
ms
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from
30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the
phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of
uncertainty.
Table 56.
WWDG min-max timeout value @48 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
1
0
0.0853
5.4613
2
1
0.1706
10.9226
4
2
0.3413
21.8453
8
3
0.6826
43.6906
Unit
ms
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Doc ID 023683 Rev 1
STM32F050xx
6.3.19
Electrical characteristics
Communication interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under ambient temperature, fPCLK frequency and VDD supply voltage conditions
summarized in Table 15: General operating conditions.
The I2C interface meets the requirements of the standard I2C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
The I2C characteristics are described in Table 57. Refer also to Section 6.3.13: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 57.
I2C characteristics(1)
Standard mode
Symbol
Fast mode
Fast Mode Plus
Parameter
Unit
Min
Max
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
0.5
-
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
0.26
-
tsu(SDA)
SDA setup time
250
-
100
-
50
-
th(SDA)
SDA data hold time
0(3)
3450(2)
0(3)
900(2)
0(4)
450(2)
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
-
300
-
120
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
-
120
th(STA)
Start condition hold time
4.0
-
0.6
-
0.26
-
tsu(STA)
Repeated Start condition
setup time
4.7
-
0.6
-
0.26
-
tsu(STO)
Stop condition setup time
4.0
-
0.6
-
0.26
-
μs
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
-
1.3
-
0.5
-
μs
Cb
Capacitive load for each bus
line
-
400
-
400
-
550
pF
µs
ns
µs
1. The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when
I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in
production.
2. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.
3. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
4. The device must internally provide a hold time of at least 120ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
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Electrical characteristics
Table 58.
STM32F050xx
I2C analog filter characteristics(1)
Symbol
tSP
Parameter
Pulse width of spikes that are
suppressed by the analog filter
Min
Max
Unit
50
260
ns
1. Guaranteed by design, not tested in production.
Figure 26. I2C bus AC waveforms and measurement circuit
6$$
6$$
2
2
-#5
Ω
3$!
)#BUS
Ω
3#,
3 4!242%0%!4%$
3 4!24
3 4!24
TSU34!
3$!
TF3$!
TR3$!
TH34!
3#,
TW3#,(
TSU3$!
TW3#,,
TR3#,
TH3$!
3 4/0
TF3#,
TW34/34!
TSU34/
-36
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 59 for SPI or in Table 60 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 15: General operating conditions.
Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
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Doc ID 023683 Rev 1
STM32F050xx
Table 59.
Symbol
Electrical characteristics
SPI characteristics
Min
Max
Master mode
-
18
Slave mode
-
18
SPI clock rise and fall
time
Capacitive load: C = 15 pF
-
6
tsu(NSS)(1)
NSS setup time
Slave mode
4Tpclk
-
th(NSS)(1)
NSS hold time
Slave mode
2Tpclk + 10
-
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
Tpclk/2 -2
Tpclk/2 + 1
Master mode
4
-
Slave mode
5
-
Master mode
4
-
Slave mode
5
-
fSCK
1/tc(SCK)
tr(SCK)
tf(SCK)
Parameter
SPI clock frequency
(1)
tw(SCKH)
tw(SCKL)(1)
tsu(MI) (1)
tsu(SI)(1)
th(MI)
MHz
Data input hold time
ta(SO)(1)(2)
Data output access time
Slave mode, fPCLK = 20 MHz
0
3Tpclk
tdis(SO)(1)(3)
Data output disable time
Slave mode
0
18
(1)
Data output valid time
Slave mode (after enable edge)
-
22.5
tv(MO)(1)
Data output valid time
Master mode (after enable edge)
-
6
Slave mode (after enable edge)
11.5
-
Master mode (after enable edge)
2
-
25
75
tv(SO)
th(SO)
(1)
th(MO)
(1)
DuCy(SCK)
Unit
ns
Data input setup time
(1)
th(SI)(1)
Conditions
ns
Data output hold time
SPI slave input clock duty
Slave mode
cycle
%
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
Doc ID 023683 Rev 1
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Electrical characteristics
STM32F050xx
Figure 27. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
SCK Input
tSU(NSS)
CPHA= 0
CPOL=0
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
B I T1 IN
M SB IN
LSB IN
th(SI)
ai14134c
Figure 28. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
SCK Input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
th(SO)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
B I T1 IN
M SB IN
LSB IN
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
80/97
Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
Figure 29. SPI timing diagram - master mode(1)
High
NSS input
SCK Output
SCK Output
tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
MS BIN
tr(SCK)
tf(SCK)
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
M SB OUT
tv(MO)
B I T1 OUT
LSB OUT
th(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Doc ID 023683 Rev 1
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Electrical characteristics
STM32F050xx
I2S characteristics
Table 60.
Symbol
fCK
1/tc(CK)
Parameter
I2S clock frequency
Conditions
Master mode (data: 16 bits, Audio
frequency = 48 kHz)
Slave mode
2
I S clock rise time
tr(CK)
2
I S clock fall time
tf(CK)
tw(CKH) (1)
I2S clock high time
Capacitive load CL = 15 pF
Min
Max
1.597
1.601
MHz
0
6.5
-
10
-
12
306
-
312
-
I2S clock low time
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
(1)
WS valid time
Master mode
2
-
th(WS) (1)
WS hold time
Master mode
2
-
tsu(WS) (1)
WS setup time
Slave mode
7
-
WS hold time
Slave mode
0
-
DuCy(SCK)
I2S slave input clock duty
cycle
Slave mode
25
75
tsu(SD_MR) (1)
Data input setup time
Master receiver
6
-
(1)
Data input setup time
Slave receiver
2
-
Master receiver
4
-
0.5
-
tw(CKL)
tv(WS)
th(WS)
(1)
ns
(1)
tsu(SD_SR)
th(SD_MR)(1)(2)
th(SD_SR)
(1)(2)
%
Data input hold time
Slave receiver
tv(SD_ST) (1)(2)
Data output valid time
Slave transmitter (after enable
edge)
-
20
th(SD_ST) (1)
Data output hold time
Slave transmitter (after enable
edge)
13
-
tv(SD_MT) (1)(2)
Data output valid time
Master transmitter (after enable
edge)
-
4
th(SD_MT) (1)
Data output hold time
Master transmitter (after enable
edge)
0
-
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.
82/97
Unit
Doc ID 023683 Rev 1
ns
STM32F050xx
Electrical characteristics
Figure 30. I2S slave timing diagram (Philips protocol)
CK Input
tc(CK)
CPOL = 0
CPOL = 1
tw(CKH)
th(WS)
tw(CKL)
WS input
tv(SD_ST)
tsu(WS)
SDtransmit
LSB transmit(2)
MSB transmit
Bitn transmit
tsu(SD_SR)
LSB receive(2)
SDreceive
th(SD_ST)
LSB transmit
th(SD_SR)
MSB receive
Bitn receive
LSB receive
ai14881b
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 31. I2S master timing diagram (Philips protocol)
tf(CK)
tr(CK)
CK output
tc(CK)
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS)
th(WS)
tw(CKL)
WS output
tv(SD_MT)
SDtransmit
LSB transmit(2)
MSB transmit
LSB receive(2)
LSB transmit
th(SD_MR)
tsu(SD_MR)
SDreceive
Bitn transmit
th(SD_MT)
MSB receive
Bitn receive
LSB receive
ai14884b
1. Data based on characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Package characteristics
STM32F050xx
7
Package characteristics
7.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
84/97
Doc ID 023683 Rev 1
STM32F050xx
Package characteristics
Figure 32. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline
D
ccc C
D1
D3
A
A2
25
36
24
37
L1
b
E3 E1 E
48
Pin 1
identification
13
1
L
A1
K
c
12
5B_ME
1. Drawing is not to scale.
Table 61.
LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
A
Max
Min
Typ
1.600
A1
0.050
A2
1.350
b
0.170
c
0.090
D
8.800
D1
6.800
D3
Max
0.0630
0.150
0.0020
1.400
1.450
0.0531
0.0551
0.0571
0.220
0.270
0.0067
0.0087
0.0106
0.200
0.0035
9.000
9.200
0.3465
0.3543
0.3622
7.000
7.200
0.2677
0.2756
0.2835
5.500
0.0059
0.0079
0.2165
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
5.500
0.2165
e
0.500
0.0197
L
0.450
L1
k
ccc
0.600
0.750
0.0177
1.000
0°
3.5°
0.0236
0.0295
0.0394
7°
0.080
0°
3.5°
7°
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 023683 Rev 1
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Package characteristics
STM32F050xx
Figure 33. LQFP48 recommended footprint
0.50
1.20
9.70
0.30
25
36
37
24
0.20
7.30
5.80
7.30
48
13
12
1
1.20
5.80
9.70
ai14911b
1. Drawing is not to scale.
2. Dimensions are in millimeters.
86/97
Doc ID 023683 Rev 1
STM32F050xx
Package characteristics
Figure 34. UFQFPN32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline
Seating plane
C
ddd
C
A
A1
A3
D
e
16
9
17
8
E
b
E2
24
1
L
32
Pin # 1 ID
R = 0.30
D2
L
Bottom view
A0B8_ME
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device ground and must
be connected. It is referred to as pin 0 in Table 8: Pin definitions.
Table 62.
UFQFPN32 – 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package
mechanical data
inches(1)
millimeters
Dim.
Min
Typ
Max
Min
Typ
Max
A
0.5
0.55
0.6
0.0197
0.0217
0.0236
A1
0.00
0.02
0.05
0
0.0008
0.0020
A3
0.152
0.006
b
0.18
0.23
0.28
0.0071
0.0091
0.0110
D
4.90
5.00
5.10
0.1929
0.1969
0.2008
D2
3.50
0.1378
E
4.90
5.00
5.10
0.1929
0.1969
0.2008
E2
3.40
3.50
3.60
0.1339
0.1378
0.1417
e
L
ddd
0.500
0.30
0.40
0.0197
0.50
0.08
0.0118
0.0157
0.0197
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 023683 Rev 1
87/97
Package characteristics
STM32F050xx
Figure 35. UFQFPN32 recommended footprint
1. Drawing is not to scale.
2. Dimensions are in millimeters.
88/97
Doc ID 023683 Rev 1
STM32F050xx
Package characteristics
Figure 36. UFQFPN28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline
$
"
$
!
3EATING
0LANE
#OX 0INCORNER
% %
,
,
0IN)$
$ETAIL:
$ETAIL:
E
4
2O4YP
!
!
3EATING
0LANE
B
!"?-%?6
1. Drawing is not to scale.
2. Dimensions are in millimeters.
3. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
Table 63.
X
UFQFPN28 – 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.5
0.55
0.6
0.0197
0.0217
0.0236
A1
-0.05
0
0.05
-0.002
0
0.002
D
3.9
4
4.1
0.1535
0.1575
0.1614
D1
2.9
3
3.1
0.1142
0.1181
0.122
E
3.9
4
4.1
0.1535
0.1575
0.1614
E1
2.9
3
3.1
0.1142
0.1181
0.122
L
0.3
0.4
0.5
0.0118
0.0157
0.0197
L1
0.25
0.35
0.45
0.0098
0.0138
0.0177
T
b
e
0.152
0.2
0.25
0.006
0.3
0.5
0.0079
0.0098
0.0118
0.0197
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 023683 Rev 1
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Package characteristics
STM32F050xx
Figure 37. UFQFPN28 recommended footprint
1. Dimensions are in millimeters
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
90/97
Doc ID 023683 Rev 1
!"?-%?&0
STM32F050xx
Package characteristics
Figure 38. TSSOP20 - 20-pin thin shrink small outline
$
C
%
%
K
AAA #0
,
!
!
!
,
B
E
9!?-%
1. Drawing is not to scale.
Table 64.
TSSOP20 – 20-pin thin shrink small outline package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
A
Max
Min
Typ
1.2
A1
0.05
A2
0.8
b
0.0472
0.15
0.002
1.05
0.0315
0.19
0.3
0.0075
0.0118
c
0.09
0.2
0.0035
0.0079
D
6.4
6.5
6.6
0.252
0.2559
0.2598
E
6.2
6.4
6.6
0.2441
0.252
0.2598
E1
4.3
4.4
4.5
0.1693
0.1732
0.1772
e
L
0.65
0.45
L1
k
aaa
1
0.6
0.0394
0.0413
0.0256
0.75
0.0177
1
0.0°
0.0059
0.0236
0.0295
0.0394
8.0°
0.1
0.0°
8.0°
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 023683 Rev 1
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Package characteristics
STM32F050xx
Figure 39. TSSOP20 recommended footprint
1. Dimensions are in millimeters
92/97
Doc ID 023683 Rev 1
STM32F050xx
7.2
Package characteristics
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 15: General operating conditions on page 39.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
●
TA max is the maximum ambient temperature in °C,
●
ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
●
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
●
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 65.
Package thermal characteristics
Symbol
ΘJA
7.2.1
Parameter
Value
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm
55
Thermal resistance junction-ambient
UFQFPN32 - 5 × 5 mm
38
Unit
°C/W
Thermal resistance junction-ambient
UFQFPN28 - 4 × 4 mm
118
Thermal resistance junction-ambient
TSSOP20
110
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
7.2.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Part numbering.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F05xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
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Package characteristics
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Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 80 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Table 65 TJmax is calculated as follows:
–
For LQFP48, 55 °C/W
TJmax = 80 °C + (55°C/W × 447 mW) = 80 °C + 24.585 °C = 104.585 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Table 15:
General operating conditions on page 39.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Part numbering).
Note:
With this given PDmax we can find the TAmax allowed for a given device temperature range
(order code suffix 6 or 7).
Suffix 6: TAmax = TJmax - (55°C/W × 447 mW) = 105-24.585 = 80.415 °C
Suffix 7: TAmax = TJmax - (55°C/W × 447 mW) = 125-24.585 = 100.415 °C
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
Using the values obtained in Table 65 TJmax is calculated as follows:
–
For LQFP48, 55 °C/W
TJmax = 100 °C + (55 °C/W × 134 mW) = 100 °C + 7.37 °C = 107.37 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Part numbering) unless we reduce the power dissipation in order to be able to
use suffix 6 parts.
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8
Part numbering
Part numbering
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Example:
STM32
F
050
C
6
T
6
A
x
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
050 = STM32F050xx
Pin count
F = 20 pins
G = 28 pins
K = 32 pins
C = 48 pins
Code size
4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory
Package
P = TSSOP
U = UFQFPN
T = LQFP
Temperature range
6 = –40 °C to +85 °C
7 = –40 °C to +105 °C
Internal code
A = non-optimized die
Blank = standard die
Options
xxx = programmed parts
TR = tape and real
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Revision history
9
STM32F050xx
Revision history
Table 66.
96/97
Document revision history
Date
Revision
22-Nov-2012
1
Changes
Initial release
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