SANYO ENA1416C

Ordering number : ENA1416C
Bi-CMOS IC
LV8111V
For Polygon Mirror Motor
3-phase Brushless Motor Driver
Overview
The LV8111V is a 3-phase brushless motor driver for polygon mirror motor driving of LBP.
A circuit needed to drive of polygon mirror motor can be composed of a single-chip. Also, the output transistor is made
DMOS by using BiDC process, and by adopting the synchronous rectification method, the lower power consumption
(Heat generation) is achieved.
Features
• 3-phase bipolar drive
• Direct PWM drive + synchronous rectification
• IO max1 = 2.5A
• IO max1 = 3.0A (t ≤ 0.1ms)
• Output current control circuit
• PLL speed control circuit
• Phase lock detection output (with mask function)
• Compatible with Hall FG
• Provides a 5V regulator output
• Full complement of on-chip protection circuits, including lock
protection, current limiter, under-voltage protection, and thermal
shutdown protection circuits
• Circuit to switch slowing down method while stopped
(Free run or Short-circuit brake)
• Constraint protection detection signal switching circuit (FG or LD)
• Forward / Reverse switching circuit
• Hall bias pin (Bias current cut in a stopped state)
• SDCC (Speed Detection Current Control) function
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Supply voltage
Symbol
Conditions
Ratings
Unit
VCC max
VCC pin
37
V
VG max
VG pin
42
V
IO max1
*1
2.5
A
IO max2
t ≤ 0.1ms *1
3.0
A
Allowable Power dissipation
Pd max
Mounted on a specified board *2
1.7
W
Operation temperature
Topr
-25 to +80
°C
Storage temperature
Tstg
-55 to +150
°C
Junction temperature
Tj max
150
°C
Output current
*1. Tj max = 150°C must not be exceeded.
Continued on next page.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment. The products mentioned herein
shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life,
aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system,
safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives
in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any
guarantee thereof. If you should intend to use our products for new introduction or other application different
from current conditions on the usage of automotive device, communication device, office equipment, industrial
equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the
intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely
responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer ' s products or
equipment.
31412 SY 20120224-S00003 / O1409 SY 20090916-S00007 / 60309 MS 20090521-S00002 / 22509 MS 20090212-S00001 No.A1416-1/13
LV8111V
Continued from preceding page.
*2. Specified board: 114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Allowable Operating Ranges at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage range
VCC
10 to 35
V
5V constant voltage output current
IREG
0 to -30
mA
LD pin applied voltage
VLD
0 to 5
V
LD pin output current
ILD
0 to 15
mA
FG pin applied voltage
VFG
0 to 5
V
FG pin output current
IFG
0 to 15
mA
HB pin output current
IHB
0 to -30
mA
Electrical Characteristics at Ta = 25°C, VCC = 24V
Ratings
Parameter
Symbol
Conditions
Unit
min
Current drain
typ
ICC1
ICC2
In a stop state
max
5.5
6.5
mA
1.0
1.5
mA
5V Constant Voltage Output
Output voltage
VREG
5.0
5.35
V
Line regulation
ΔVREG1
VCC = 10 to 35V
4.65
20
100
mV
Load regulation
ΔVREG2
IO = -5 to -20mA
25
60
mV
Temperature coefficient
ΔVREG3
Design target value *
Output ON resistance
RON
IO = 1A , Sum of the lower and upper side
outputs
Output leakage current
IOleak
Design target value *
Lower side Diode forward voltage
VD1
Upper side Diode forward voltage
VD2
0
mV/°C
Output Block
1.5
1.9
Ω
10
μA
ID = -1A
1.0
1.35
V
ID = 1A
1.0
1.35
V
Charge Pump Output (VG pin)
Output voltage
VGOUT
VCC+4.9
V
CP1 pin
Output ON resistance (High level)
VOH(CP1)
ICP1 = -2mA
500
700
Ω
Output ON resistance (Low level)
VOL(CP1)
ICP1 = 2mA
300
400
Ω
Hall Amplifier Block
Input bias current
IHB(HA)
Common mode input voltage range
VICM
-2
Hall input sensitivity
μA
-0.5
0.5
VREG-2.0
80
V
mVp-p
Hysteresis
ΔVIN(HA)
Input voltage L → H
VSLH
12
mV
Input voltage H → L
VSHL
-12
mV
15
24
42
mV
Hall Bias (HB pin) P-channel Output
20
30
Ω
10
μA
Output voltage ON resistance
VOL(HB)
IHB = -20mA
Output leakage current
IL(HB)
VO = 0V
Input amplifier gain
GFG
Design target value *
5
Input hysteresis (H → L)
VSHL(FGS)
Input referred, Design target value *
0
mV
Input hysteresis (L → H)
VSLH(FGS)
Input referred, Design target value *
10
mV
hysteresis
VFGL
Input referred, Design target value *
10
mV
FG Amplifier Schmitt Block (IN1)
times
* Design target value, Do not measurement.
Continued on next page.
No.A1416-2/13
LV8111V
Continued from preceding page.
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
FGFIL pin
High level output voltage
VOH(FGFIL)
2.7
3.0
3.3
V
Low level output voltage
VOL(FGFIL)
0.75
0.85
0.95
V
External capacitor charge current
ICHG1
VCHG1 = 1.5V
-5
-4
-3
μA
External capacitor discharge current
ICHG2
VCHG2 = 1.5V
Amplitude
V(FGFIL)
3
4
5
1.95
2.15
2.35
μA
Vp-p
FG Output
Output ON resistance
VOL(FG)
IFG = 7mA
Output leakage current
IL(FG)
VO = 5V
20
30
Ω
10
μA
V
PWM Oscillator
High level output voltage
VOH(PWM)
2.95
3.2
3.45
Low level output voltage
VOL(PWM)
1.3
1.5
1.7
V
External capacitor charge current
ICHG(PWM)
VPWM = 2V
-90
-70
-50
μA
Oscillation frequency
f(PWM)
C = 150pF
180
225
270
kHz
Amplitude
V(PWM)
1.5
1.7
1.9
Vp-p
Recommended operation frequency
fOPR
15
300
kHz
range
CSD Oscillation Circuit
High level output voltage
VOH(CSD)
2.7
3.0
3.3
V
Low level output voltage
VOL(CSD)
0.8
1.0
1.2
V
Amplitude
V(CSD)
1.75
2.0
2.25
Vp-p
External capacitor charge current
ICHG1(CSD) VCHG1 = 2.0V
-14
-10
-6
μA
External Capacitor Discharge Current
ICHG2(CSD) VCHG2 = 2.0V
8
11
14
μA
Oscillation frequency
f(CSD)
C = 0.068μF, Design target value *
30
40
50
Hz
Output ON resistance (high level)
VPDH
IOH = -100μA
500
700
Ω
Output ON resistance (low level)
VPDL
IOL = 100μA
500
700
Ω
Output ON resistance
VOL(LD)
ILD = 10mA
20
30
Ω
Output leakage current
IL(LD)
VO = 5V
10
μA
VIO(ER)
Design target value *
+10
mV
+1
μA
Phase comparing output
Phase Lock Detection Output
Error Amplifier Block
Input offset voltage
-10
Input bias current
IB(ER)
High level output voltage
VOH(ER)
IOH = -100μA
EI+0.7
-1
EI+0.85
EI+1.0
V
Low level output voltage
VOL(ER)
IOL = 100μA
EI-1.75
EI-1.6
EI-1.45
V
DC bias level
VB(ER)
-5%
VREG/2
5%
V
0.5
0.55
0.6
times
VRF
0.465
0.515
0.565
V
Operation voltage
VSD
8.3
8.7
9.1
V
Hyteresis
ΔVSD
0.2
0.35
0.5
V
-4.5
-3.0
-1.5
μA
3.25
3.5
3.75
V
150
175
°C.
30
°C
Current Control Circuit
Drive gain
GDF
While phase locked
Current Limiter Circuit (pins RF and RFS)
Limiter voltage
Under-voltage Protection
CLD Circuit
External capacitor charge current
ICLD
Operation voltage
VH(CLD)
VCLD = 0V
Thermal Shutdown Operation
Thermal shutdown operation
TSD
Design target value (Junction temperature)
ΔTSD
Design target value (Junction temperature)
temperature
Hysteresis
* Design target value, Do not measurement.
Continued on next page.
No.A1416-3/13
LV8111V
Continued from preceding page.
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
CLK pin
External input frequency
fI(CLK)
0.1
10
High level input voltage
VIH(CLK)
2.0
VREG
kHz
V
Low level input voltage
VIL(CLK)
0
1.0
V
Input open voltage
VIO(CLK)
VREG-0.5
VREG
V
Hysteresis
VIS(CLK)
0.2
0.3
0.4
V
High level input current
IIH(CLK)
VCLK = VREG
-10
0
+10
μA
Low level input current
IIL(CLK)
VCLK = 0V
-110
-85
-60
μA
VREG
V
V
CSDSEL pin
High level input voltage
VIH(CSD)
2.0
Low level input voltage
VIL(CSD)
0
1.0
Input open voltage
VIO(CSD)
VREG-0.5
VREG
V
High level input current
IIH(CSD)
VCSD = VREG
Low level input current
IIL(CSD)
VCSD = 0V
-10
0
+10
μA
-110
-85
-60
μA
VREG
V
V
S/S pin
High level input voltage
VIH(SS)
2.0
Low level input voltage
VIL(SS)
0
1.0
Input open voltage
VIO(SS)
VREG-0.5
VREG
V
Hysteresis
VIS(SS)
0.2
0.3
0.4
V
High level input current
IIH(SS)
VS/S = VREG
-10
0
+10
μA
Low level input current
IIL(SS)
VS/S =0V
-110
-85
-60
μA
VREG
V
V
BRSEL pin
High level input voltage
VIH(BRSEL)
2.0
Low level input voltge
VIL(BRSEL)
0
1.0
Input open voltage
VIO(BRSEL)
VREG-0.5
VREG
V
High level input current
IIH(BRSEL)
VBRSEL = VREG
Low level input current
IIL(BRSEL)
VBRSEL = 0V
-10
0
+10
μA
-110
-85
-60
μA
VREG
V
V
F/R pin
High level input voltage
VIH(FR)
2.0
Low level input voltage
VIL(FR)
0
1.0
Input open voltage
VIO(FR)
VREG-0.5
VREG
V
High level input current
IIH(FR)
VF/R = VREG
Low level input current
IIL(FR)
VF/R = 0V
-10
0
+10
μA
-110
-85
-60
μA
No.A1416-4/13
LV8111V
Package Dimensions
unit : mm (typ)
3333
TOP VIEW
SIDE VIEW
BOTTOM VIEW
15.0
44
23
(3.5)
0.5
5.6
7.6
(4.7)
22
0.22
0.65
0.2
1.7MAX
1
(0.68)
0.1 (1.5)
SIDE VIEW
SANYO : SSOP44K(275mil)
Pd max -- Ta
Allowable power dissipation, Pd max -- W
2.0
Specified board: 114.3×76.1×1.6mm3
glass epoxy board.
1.7
1.5
1.0
0.95
0.5
0
-20
0
20
40
60
80
100
Ambient temperature, Ta -- °C
IN3+
IN2−
IN2+
IN1−
IN1+
31
30
29
28
27
26
25
24
23
14
15
16
17
18
19
20
21
22
EO
TOC
GND
HB
34
EI
35
IN3−
36
PD
37
SUB
38
PH
RF
39
GND2
RFS
40
FGFIL
VCC2
41
FC
VCC1
42
OUT3
VG
43
OUT2
CP1
44
OUT1
CP2
Pin Assignment
33
32
2
3
4
5
6
7
8
9
10
LD
S/S
VREG
BRSEL
CSDSEL
F/R
CLD
CSD
FG
11
12
PWM
1
CLK
LV8111V
13
Top view
No.A1416-5/13
LV8111V
Block Diagram and Application Circuit Example
PWM
CSDSEL
PD
CSDSEL
CSD
CSD
OSC
COUNT
PWM
OSC
LOGIC
EI
VREG
BRSEL
BRSEL
LOGIC
EO
TOC
S/S
S/S
COMP
F/R
FC
PEAK
HOLD
PH
F/R
TSD
LD output
CONT
AMP
LD
LD
CLD
LD
MASK
VREG
VREG
PLL
CLK input
FG output
CLK
VCC
LVDS
VCC1
VCC2
CLK
CNTROL
CIRCUIT
FG
VG
FG
CHARGE
PUMP
CP1
CP2
FGFIL
FILTER
OUT1
DRIVER
OUT2
HALL HYS AMP
IN1+
IN1−
IN2+
IN2−
IN3+
HB
IN3−
HB
CURR
LIM
RFS
OUT3
SUB
RF
GND
GND2
No.A1416-6/13
LV8111V
Pin Function
Pin No.
1
Pin name
CLK
Function
Equivalent circuit
Clock input pin (10kHz maximum)
VREG
55kΩ
5kΩ
10kΩ
1
2
LD
Phase lock detection output pin.
VREG
Goes ON during PLL-phase lock.
Open drain output.
2
3
S/S
Start/Stop input pin.
VREG
START with a low-level input.
STOP with a high-level input or open input
55kΩ
5kΩ
10kΩ
3
4
VREG
5V regulator output pin.
VCC
(the control circuit power supply)
50Ω
Connect a capacitor between this pin and GND for
stabilization.
4
5
BRSEL
Brake selection pin.
VREG
By low level, short-circuit braking when the S/S pin is in a
stopped state.
(Brake for the inspection process)
55kΩ
5kΩ
5
6
CSDSEL
Motor constraint protection detection signal selection pin.
VREG
Select FG with low,
and LD with high or in an open state.
55kΩ
5kΩ
6
Continued on next page.
No.A1416-7/13
LV8111V
Continued from preceding page.
Pin No.
7
Pin name
F/R
Function
Pin to select Forward / Reverse.
Equivalent circuit
VREG
55kΩ
5kΩ
7
8
CLD
Pin to set phase lock signal mask time.
VREG
Connect a capacitor between this pin and GND.
If there is no need for masking, this pin must be left open.
500Ω
8
2kΩ
9
CSD
Pin for both the constraint protection circuit operation time
VREG
and the initial reset pulse setting.
Connect a capacitor between this pin and GND.
If the motor constraint protection circuit is not used,
500Ω
a capacitor and a resistor must be connected in parallel
9
between the CSD pin and GND.
10
FG
FG Schmitt output pin.
VREG
Open drain output.
10
12
PWM
Pin to set the oscillation frequency of PWM.
VREG
Connect a capacitor between this pin and GND.
200Ω
12
2kΩ
14
FC
Frequency characteristics correction pin of the current
VREG
limiter circuit.
Connect a capacitor between this pin and GND.
500Ω
14
110kΩ
Continued on next page.
No.A1416-8/13
LV8111V
Continued from preceding page.
Pin No.
15
Pin name
FGFIL
Function
FG filter pin.
Equivalent circuit
VREG
When the noise of the FG signal is a problem, connect a
capacitor between this pin and GND for stabilization.
15kΩ
500Ω
15
16
PH
Pin to stabilize the RF waveform.
VREG
Connect a capacitor between this pin and GND.
500Ω
16
10kΩ
17
PD
Phase comparison output pin.
VREG
The phase error is output by the duty changing of the pulse.
500Ω
17
18
EI
Error amplifier input pin.
VREG
500Ω
18
19
EO
Error amplifier output pin.
VREG
19
100kΩ
20
TOC
Torque command voltage input pin.
VREG
Normally, this pin must be connected with the EO pin.
20
21
GND
Ground pin of the control circuit block.
Continued on next page.
No.A1416-9/13
LV8111V
Continued from preceding page.
Pin No.
22
Pin name
HB
Function
Equivalent circuit
Hall element bias current pin.
VREG
Goes ON when the S/S pin is in a start state.
Goes OFF when the S/S pin is in an stopped state.
22
23
24
25
26
27
28
IN1+
IN1−
Hall amplifier input pin.
IN2+
IN2−
In reverse case is a low-level state.
IN3+
IN3−
desirable in the Hall sensor inputs.
The input amplitude of 100mVp-p or more (differential) is
If noise on the Hall inputs is a problem, that noise must be
excluded by inserting capacitors across the inputs.
29
SUB
VREG
A high level state of logic is recognized when IN+ > IN−.
500Ω
500Ω
24 26 28
23 25 27
Frame ground pin. This pin is connected with the GND2 pin.
30
GND2
Ground pin of the output circuit block.
32
OUT3
Output pin.
34
OUT2
As for PWM, Duty control is executed on the upper- side
36
OUT1
FET.
VCC
32 34 36
38
RF
Source pin of output MOSFET (lower-side).
38
Connect a low resistance (Rf) between this pin and GND.
39
RFS
Output current detection pin.
VREG
Connect to RF pin.
5kΩ
39
40
VCC2
Power supply pin.
Connect a capacitor between this pin and GND for
stabilization.
41
VCC1
42
VG
Power supply pin for control.
Charge pump output pin (Power supply for the upper side
FET gate).
VCC
Connect a capacitor between this pin and VCC.
500Ω
44
100Ω
43
CP1
Pin to connect a capacitor for charge pump.
44
CP2
Connect a capacitor between CP1 and CP2.
42
43
No.A1416-10/13
LV8111V
3-phase Logic Truth Table
(IN = “H” indicates the state where in IN+ > IN−)
F/R = H
F/R = L
Output
IN1
IN2
IN3
IN1
IN2
IN3
OUT1
OUT2
OUT3
H
L
H
L
H
L
L
H
M
H
L
L
L
H
H
L
M
H
H
H
L
L
L
H
M
L
H
L
H
L
H
L
H
H
L
M
L
H
H
H
L
L
H
M
L
L
L
H
H
H
L
M
H
L
S/S Pin
BRSEL Pin
Input state
Mode
Input state
High or Open
Stop
High or Open
While stopped
Free run
Low
Start
Low
Short-circuit brake
CSDSEL Pin
Input state
Mode
High or Open
LD standard
Low
FG standard
LV8111V Description
1. Speed Control Circuit
This IC can realize a high efficiency, low-jitter, a stable rotation by adopting the PLL speed control method.
This the PLL circuit compares the phase difference of the edge between the CLK signal and the FG signal and controls
by using the output of error. The FG servo frequency under control becomes congruent with the CLK frequency.
fFG (Servo) = fCLK
2. Output Drive Circuit
This IC adopts the direct PWM drive method to reduce power loss in the output. Adjusts the driving force of the motor
by changing on-duty of output transistor. The PWM switching of the output is performed by the upper-side output
transistor.
Also, this IC has a parasitic diode of the output DMOS as a regeneration route when the PWM switching is off.
But, this IC is cut down the fever than the diode regeneration by performing synchronous rectification.
3. Current Limiter Circuit
This IC limits the (peak) current at the value
I = VRF / Rf (VRF = 0.515V (typical), Rf : current detection resister)).
The current limitation operation consists of reducing the PWM output on duty to suppress the current.
To prevent malfunction of the current limitation operation when the reverse recovery current of diode is detected, the
operation has a delay (approximately 300ns). In case of a coil resistance of motor is small or small inductance, since
the current change at start-up is fast, there is a possibility that the current more than specified current is flowed by this
delay.
It is necessary to set the current increases by the delay.
4. Power Saving Circuit
This IC becomes the power saving state of decreasing the consumption current in the stop state. The bias current of the
majority circuits is cut in the power saving state. Also, 5V regulator output is output in the power saving state.
5. Reference Clock
Note that externally-applied clock signal has no noise of chattering. The input circuit has a hysteresis.
But, if noise is a problem, that noise must be excluded by inserting capacitors across the inputs.
If clock input goes to the no input state when the IC is in the start state, the drive is turned off after a few rotation of
motor if the motor constrained protection circuit does operate. (Clock disconnection protection)
No.A1416-11/13
LV8111V
6. PWM Frequency
The PWM frequency is determined by using a capacitor C (F) connected to the PWM pin.
fPWM ≈ 1 / (29500 × C ) … 150pF or more
fPWM ≈ 1 / (32000 × C ) … 100pF or more, less than 150pF
The frequency is oscillated at about 225kHz when a capacitor of 150pF is connected.
The GND of a capacitor must be placed as close to the control block GND (GND pin ) of the IC as possible to reduce
influence of the output.
7. Hall Effect Sensor Input Signals
The signal input of the amplitude of hysteresis of 42mV max or more is required in the Hall effect sensor inputs.
Also, an input amplitude of over 100mVp-p is desirable in the Hall effect sensor inputs in view of influence of noise.
If the output waveform (when the phase changes ) is distorted by noise, that noise must be excluded by inputting
capacitors across the inputs.
8. FG Signals
The Hall signal of IN1 is used as the FG signal in the IC. If noise is a problem, the noise of the FG signal can be
excluded by inserting a capacitor between the FGFIL pin and GND.
Note that normal operation becomes impossible if the value of the capacitor is overlarge. Also, note that the trouble of
noise occurs easily when the position of GND of a capacitor is incorrect.
9. Constraint Protection Circuit
This IC has an on-chip constraint protection circuit to protect the IC and the motor in motor constraint mode. when the
CSDSEL pin is set to the high level or open input, if the LD output remains high (unlocked statement) for a fixed
period in the start state, this circuit operates. In the low level setting case, if the FG signal is not switched for a fixed
period in the start state, this circuit is operates. Also, the upper-side output transistor is turned off while the constraint
protection circuit is operating. This time is set by the capacitance of the capacitor attached to the CSD pin.
The set time (in seconds) is 102 × C (μF)
When a capacitor of 0.068μF is attached, the protection time becomes about 7.0 seconds.
The set time must be set well in advance for the motor start-up time. When the motor is decelerated by switching the
clock frequency, this protection circuit is not operated. To clear the motor constrained state, the S/S pin is switched
into a stop state or the power must be turned off and reapplied. Since the CSD pin also functions as the power-on reset
pin, if the CSD pin were connected directly to ground, the logic circuit goes to the reset state and the speed cannot be
controlled.
Therefore, if the motor constraint protection circuit is not used, a resistor of about 220kΩ and a capacitor of about
4700pF must be connected in parallel between the CSD pin and GND.
10. Phase Lock Signals
(1) Phase lock range
This IC has no the speed system counter. The speed error range in the phase lock state is indeterminable only by the
characteristics of the IC. ( because the accelerations of the change in FG frequency influences.)
When it is necessary to specify for the speed error as a motor, the value obtained while the motor is actually operating
must be measured. Since the speed error occurs easily when the accelerations of FG is large, the speed error will be
the largest when the IC goes into the lock state during start-up or the unlocked state by switching the clock.
(2) Phase lock signal mask functions
When the IC goes into the lock state during start-up or the unlocked state by switching the clock, the low signal for a
short-time by using the hunting when the IC goes into the locked state is masked. Therefore, the lock signal is output
in stable state. But, the mask time duration causes the delay of the lock signal output. The mask time is set by the
capacitance of the capacitor attached between the CLD pin and GND.
The mask time (seconds) is 1.8 × C (μF)
When a capacitor of 0.1μF is attached, the mask time becomes about 180ms.
If the signals should be masked completely, the mask time must be set well in advance.
When there is no need for masking, the CLD pin must be left open.
No.A1416-12/13
LV8111V
11. Power Supply Stabilization
Since this IC is used in applications that draw large output currents and adopts the drive method by switching, the
power-Supply line is subject to fluctuations. Therefore, capacitors with capacitances adequate to stabilize the
power-supply voltage must be connected between the VCC pin and GND. The ground-side a capacitor must be
connected as close to the GND2 pin of power GND as possible. If it is impossible to connect a capacitor (electrolytic
capacitor) near the pin, the ceramic capacitor of about 0.1μF must be connected as close to the pin as possible.
If diodes are inserted in the power-supply line to prevent IC destruction due to reverse power supply connection,
Since this makes the power-supply voltage even more subject to fluctuations, even larger capacitors will be required.
12. VREG Stabilization
To stabilize the VREG voltage that is the power supply of the control circuit, connect a capacitor of 0.1μF or more.
GND of the capacitor must be attached as close to the control block GND (GND1 pin) of the IC as possible.
13. Error Amplifier
External components of the error amplifier block must be placed as close to the IC as possible to reduce influence of
noise.
Also, these components must be placed as separate from the motor as possible.
14. IC Reverse Metal
To improve heat radiation, the metal part on the reverse of IC is stuck fast to the substrate by using highly-conduction
solder.
15. SDCC (Speed Detection Current Control) function
The SDCC circuit controls the speed detection current. It limits the current to 87.5% of the specified current to reduce
acceleration of the motor when the rotation of the motor exceeds 95% of its target speed. This enables stabilized phase
lock pull-in and minimizes the variation in startup time.
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This catalog
catalog provides
provides information
information as
asofofFebruary,
March, 2012.
2009.Specifications
Specifications and
and information
information herein
herein are
are subject
to change without notice.
PS No.A1416-13/13