GM76V8128CL/CLL LG Semicon Co.,Ltd. 131,072 WORDS x 8 BIT CMOS STATIC RAM Description Pin Configuration The GM76V8128CL/CLL is a 1,048,576 bits static random access memory organized as 131,072 words by 8 bits. Using a 0.6um advanced CMOS technology and it provides high speed operation with minimum cycle time of 70/85ns. The device is placed in a low power standby mode with /CS1 high or CS2 low and the output enable (/OE) allows fast memory access. Thus it is suitable for high speed and low power applications, especially where battery back-up is required. NC 1 32 VCC A16 2 31 A15 A14 3 30 CS2 A12 4 29 /WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 /OE A2 10 23 A10 A1 11 22 /CS1 A0 12 21 I/O7 I/O0 13 20 I/O6 Features I/O1 14 19 I/O5 I/O2 15 18 I/O4 VSS 16 17 I/O3 (Top View) Block Diagram ........ * Fast Speed : 70/85ns * Low Power Standby and Low Power Operation Standby : 72uW Max. at TA = - 40 ~ 85C(LLE/LLI) 108uW Max. at TA = - 40 ~ 85C(LE/LI) 72uW Max. at TA = 0 ~ 70C(LL) 180uW Max. at TA = 0 ~ 70C(L) Operation : 144mW (Max) * Completely Static RAM : No Clock or Timing Strobe Required * Equal Access and Cycle Time * TTL compatible inputs and outputs * Capability of Battery Back-up Operation * Single + 3.3V+/-0.3V Operation * Standard 32 DIP, SOP and TSOP-I,STSOP-I A0 * Temperature Range A1 Commercial(0¡-70C) : GM76V8128C A2 Extended (-25 ~ 85C) : GM76V8128C-E Industrial (-40 ~ 85C) : GM76V8128C-I 10 1024 MEMORY CELL ARRAY X 1024 x 128 x 8 Decoder (128K x 8) Address Buffer Chip Select Input /OE Output Enable Input I/O0-I/O7 Data Inputs/Outputs VCC Power Supply (3.0V ~3.6V) VSS Ground NC No Connection /CS1, CS2 /CS1 CS2 8 Chip Control /OE /OE, /WE /WE Chip Control I/O Buffer I/O7 /CS1, CS2 Column Select I/O6 Write Enable Input Y Decorder A16 I/O5 /WE 128 I/O3 Address Inputs 128 x 8 7 A15 I/O2 A0-A16 A14 I/O1 Function I/O0 Pin I/O4 Pin Description 97 GM76V8128CL/CLL Absolute Maximum Ratings* Symbol Parameter Rating Unit 0 ~ 70 C GM76V8128C-E -25 ~ 85 C GM76V8128C-I -40 ~ 85 C -55 ~ 150 C 260, 10 (at lead) C, S -0.5 ~ 4.6 V GM76V8128C TA Ambient Temperature under Bias TSTG Storage Temperature TSOL Soldering Temperature and Time VCC Supply Voltage VIN Input Voltage -0.5 ~ VCC + 0.5 V VI/O Input and Output Voltage -0.5 ~ VCC + 0.5 V PD Power Dissipation 0.7 W *: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions (TA = - 40 ~ 85C) Symbol Parameter Min Typ Max Unit VCC Supply Voltage 3.0 3.3 3.6 V VIH Input High Voltage 2.2 - VCC + 0.3 V VIL Input Low Voltage -0.3* - 0.4 V *Note :VIL(min) = -3.0V for <= 50ns pulse Truth Table /CS1 CS2 /OE /WE A0 to A16 DATA I/O MODE L H L H Stable Output Data Read L H X L Stable Input Data Write L H H H Stable Hi-Z Output Disable H X X X - Hi-Z X L X X - Hi-Z Standby *Note: X means don't care 98 GM76V8128CL/CLL DC Operating Characteristics (VCC = 3.3V+/-0.3V, TA = - 40 ~ 85C) Symbol Parameter Conditions Min *Typ Max Unit II(L) Input Leakage Current VIN = 0 to VCC -1 - 1 uA IO(L) Output Leakage Current /CS1 = VIH or CS2 = VIL /OE = VIH, VSS <=VOUT<=VCC -1 - 1 uA VOH High Level Output Voltage IOH = -1.0mA 2.4 - - V VOL Low Level Output Voltage IOL = 2.1mA - - 0.4 V ICC Operating Supply Current /CS1 = VIL and CS2 = VIH VIN = VIH/VIL, IOUT = 0mA - - 5 mA /CS1 = VIL and CS2 = VIH VIN = VIH/VIL IOUT = 0mA tcycle = Min, cycle - - 40 mA /CS1 = 0.2V, CS2 = VCC-0.2V VIN = VCC - 0.2V/0.2V IOUT = 0mA tcycle = 1us - - 5 mA 0.5 mA ICC1 Average Operating Current ICC2 ICCS1 Standby Current(TTL) /CS1 = VIH, CS2 = VIL - - ICCS2 Standby GM76V8128C Current(CMOS) L - Version /CS1 = VCC-0.2V, LL - Version CS2 = 0.2V L - Version LL - Version - - 50 20 uA - - 30 20 uA GM76V8128C-E GM76V8128C-I *Typ. Values are measured at 25C Capacitance (f = 1MHZ, TA = 25C) Symbol Parameter Test Conditions Min Max Unit CIN Input Capacitance VI = 0V - 6 pF CI/O Output Capacitance VO = 0V - 8 pF *Note: This parameter is sampled and not 100% tested. AC Operating Characteristics Test Conditions (VCC = 3.3V+/-0.3V, TA = - 40 ~ 85C, unless otherwise noted.) Parameter Input Pulse Level Value 0.4 to 2.2V Input Rise and Fall Time 5ns Input and Output Timing Reference Levels 1.5V Output Load CL = 100 pF + 1TTL Load 99 GM76V8128CL/CLL AC Operating Characteristics (VCC = 3.3V+/-0.3V, TA = - 40 ~ 85C) Read Cycle GM76V8128C-70 Symbol GM76V8128C-85 Parameter Unit Min Max Min Max 70 - 85 - ns tRC Read Cycle Time tAA Address Access Time - 70 - 85 ns tACS1 Chip Select 1 Access Time - 70 - 85 ns tACS2 Chip Select 2 Access Time - 70 - 85 ns tOE Output Enable Access Time - 35 - 45 ns tCLZ1 Chip Select 1 Output Setup Time 5 - 10 - ns tCHZ1 Chip Select 1 Output Floating - 25 - 30 ns tCLZ2 Chip Select 2 Output Setup Time 5 - 10 - ns tCHZ2 Chip Select 2 Output Floating - 25 - 30 ns tOLZ Output Enable Output Setup Time 0 - 0 - ns tOHZ Output Enable Output Floating - 25 - 30 ns tOH Output Hold Time 10 - 10 - ns Write Cycle Symbol Parameter GM76V8128C-70 GM76V8128C-85 Min Max Min Max Unit tWC Write Cycle Time 70 - 85 - ns tCW1 Chip Select Time 1 65 - 75 - ns tCW2 Chip Select Time 2 65 - 75 - ns tAW Address Enable Time 60 - 70 - ns tAS Address Setup Time 0 - 0 - ns tWP Write Pulse Width 50 - 60 - ns tWR Write Recovery Time 0 - 0 - ns tDW Input Data Setup Time 30 - 35 - ns tDH Input Data Hold Time 0 - 0 - ns tWHZ Write to Output in High-Z - 25 - 30 ns tOW Output Active from End of Write 0 - 0 - ns 100 GM76V8128CL/CLL Timing Waveforms Read Cycle (Note 1) tRC ADD tAA tACS1 /CS1 tCLZ1 tACS2 tCHZ1 CS2 tCLZ2 tOE tCHZ2 tOLZ /OE tOHZ tOH DOUT High-Z VALID DATA 101 GM76V8128CL/CLL Write Cycle (1) (/WE Controlled) (Notes 2, 3, 4) tWC ADD tAS tWR tAW tWP /WE tCW1 /CS1 tCW2 CS2 tWHZ tOW DOUT tDW DIN 102 tDH VALID DATA GM76V8128CL/CLL Write Cycle (2) (/CS1 Controlled) (Notes 4) tWC ADD tAS tWR tWP /WE tCW1 /CS1 tCW2 CS2 tWHZ tCLZ DOUT tDW DIN tDH VALID DATA 103 GM76V8128CL/CLL Write Cycle (3) (CS2 Controlled) (Notes 4) tWC ADD tAS tWR tWP /WE tCW2 CS2 tCW1 /CS1 tWHZ tCLZ DOUT tDW DIN tDH VALID DATA Notes: 1. /WE is High for Read Cycle. 2. Assuming that /CS1 Low transition or CS2 High transition occurs coincident with or after /WE Low transition. Outputs remain in a high impedance state. 3. Assuming that /CS1 High transition or CS2 Low transition occurs coincident with or prior to /WE High transition. Outputs remain in a high impedance state. 4. Assuming that /OE is high for write cycle. Outputs are in a high impedance state during this period. 104 GM76V8128CL/CLL Data Retention Characteristics Symbol Parameter VCCR Data Retention Supply Voltage ICCR Data Retention Current GM76V8128C GM76V8128C-E GM76V8128C-I tCDR Chip Select to Data Retention Time tR Operation Recovery Time VCC=3.0V Min Typ Max Unit 2.0 - 3.6 V L - Version LL - Version - 1 0.5 50 20* L - Version LL - Version - 1 0.5 30 20* 0 - - ns tRC** - - ns uA * 3uA max at TA = 0 ~ 40C ** tRC = Read Cycle * Low VCC Data Retention Mode: (1) /CS1 Controlled tCDR tR Data Retention Mode VCC 3.0V 2.2V VCCR1 /CS1 >= VCCR - 0.2V /CS1 0V * Low VCC Data Retention Mode: (2) CS2 Controlled tCDR Data Retention Mode tR VCC 3.0V CS2 VCCR2 CS2 <= 0.2V 0.4V 0V Notes: In Data Retention Mode, CS2 controls the Address, /WE, /CS1, /OE and DIN buffer. If CS2 controls data retention mode, VIN for these inputs can be in the high impedance state. If /CS1 controls the > VCCR - 0.2V or CS2<=0.2V. The other input levels data retention mode, CS2 must satisfy either CS2 _ (Address, /WE, /OE, I/O) can be in the high impedance state. 105 GM76V8128CL/CLL Package Dimensions Unit: Inches (mm) 32 DIP 0.540(13.72) TYP 0.600(15.24) MIN 0.625(15.88) MAX 0.045(1.14) MIN 0.055(1.40) MAX 0.008(0.200) MIN 0.015(0.380) MAX 0.15(3.81) TYP 0.016(0.41) MIN 0.020(0.51) MAX o 0.600(15.240) TYP 0 ~ 15 1.645(41.78) MIN 1.665(42.29) MAX 0.165(4.191) MIN 0.190(4.83) MAX 0.125(3.18) MIN 0.135(3.43) MAX 0.015(0.38) MIN 0.100(2.54) TYP 32 SOP 0.02(0.53) MIN 0.04(1.04) MAX 0.55(14.05) MIN 0.57(14.40) MAX 0.435(11.05) MIN 0.445(11.30) MAX 0~8 0.004(0.10) MIN 0.010(0.254) MAX 0.799(20.30) MIN 0.815(20.70) MAX 0.014(0.35) MIN 0.020(0.50) MAX 106 0.086(2.18) MIN 0.090(2.29) MAX 0.050(1.27) TYP 0.004(0.102) MIN 0.010(0.254) MAX GM76V8128CL/CLL 0.313(7.95) MIN 0.327(8.30) MAX /OE A10 /CS1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 0.720(18.30) MIN 0.728(18.50) MAX 0.006(0.15) MIN 0.010(0.25) MAX 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 /WE CS2 A15 VCC N.C A16 A14 A12 A7 A6 A5 A4 0.020(0.50) TYP 32 TSOP I (8x20mm) 0.006(0.15) MIN 0.000(0.00) MAX 0.780(19.80) MIN 0.795(20.20) MAX 0.039(1.0) MIN 0.047(1.2) MAX 0.016(0.40) MIN 0.024(0.60) MAX /OE A10 /CS1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 0.461(11.70) MIN 0.467(11.86) MAX 0.006(0.15) MIN 0.009(0.25) MAX 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0.311(7.95) MIN 0.320(8.2) MAX A11 A9 A8 A13 /WE CS2 A15 VCC N.C A16 A14 A12 A7 A6 A5 A4 0.020(0.5) TYP 32Small TSOP-I(8x13.4mm) 0.002(0.05) MIN 0.006(0.15) MAX 0.527(13.30) MIN 0.528(13.50) MAX 0.035(1.2) MIN 0.044(1.0) MAX 0.020(0.6) MIN 0.019(0.4) MAX 107